diff --git a/OWNERS b/OWNERS
new file mode 100644
index 0000000..79003ba
--- /dev/null
+++ b/OWNERS
@@ -0,0 +1,4 @@
+per-file powerhint.json = jychen@google.com,jenhaochen@google.com,wvw@google.com,joaodias@google.com
+
+# per-file for Pixel device makefiles, see go/pixel-device-mk-owner-checklist for details.
+per-file *.mk,*/BoardConfig.mk=file:device/google/gs-common:master:/OWNERS
diff --git a/audio/felix/audio-tables.mk b/audio/felix/audio-tables.mk
index 0ab8715..8fb6642 100644
--- a/audio/felix/audio-tables.mk
+++ b/audio/felix/audio-tables.mk
@@ -20,10 +20,12 @@
 PRODUCT_COPY_FILES += \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration_bluetooth_legacy_hal.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_bluetooth_legacy_hal.xml \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration.xml \
+    device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration_le_offload_disabled.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_le_offload_disabled.xml \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration_a2dp_offload_disabled.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_a2dp_offload_disabled.xml \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_platform_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_platform_configuration.xml \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/sound_trigger_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/sound_trigger_configuration.xml \
-    frameworks/av/services/audiopolicy/config/bluetooth_with_le_audio_policy_configuration_7_0.xml:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_audio_policy_configuration_7_0.xml
+    device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/bluetooth_with_le_audio_policy_configuration_7_0.xml:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_audio_policy_configuration_7_0.xml \
+    device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_volumes.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_volumes.xml
 
 # AudioEffectHAL Configuration
 PRODUCT_COPY_FILES += \
@@ -42,6 +44,7 @@
 # Audio tuning
 PRODUCT_COPY_FILES += \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/tuning/bluenote/recording.gatf:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/recording.gatf \
+    device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/tuning/bluenote/smartfeature.gstf:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/smartfeature.gstf \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/BLUETOOTH.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/BLUETOOTH.dat \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSFREE.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSFREE.dat \
     device/google/felix/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSET.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSET.dat \
diff --git a/audio/felix/config/audio_effects.xml b/audio/felix/config/audio_effects.xml
index 1718057..11e66e5 100644
--- a/audio/felix/config/audio_effects.xml
+++ b/audio/felix/config/audio_effects.xml
@@ -5,11 +5,12 @@
         <library name="reverb" path="libreverbwrapper.so"/>
         <library name="visualizer_sw" path="libvisualizer.so"/>
         <library name="downmix" path="libdownmix.so"/>
-        <library name="dynamics_processing" path="libdynproc.so"/>
+        <library name="dynamics_processing_sw" path="libdynproc.so"/>
         <library name="loudness_enhancer" path="libldnhncr.so"/>
         <library name="proxy" path="libeffectproxy.so"/>
         <library name="offload_effect" path="liboffloadeffect.so"/>
         <library name="haptic_generator" path="libhapticgenerator.so"/>
+        <library name="spatializer" path="libspatialaudio.so"/>
     </libraries>
     <effects>
         <effectProxy name="bassboost" library="proxy" uuid="2f0871a2-c93c-4824-9664-42eb2909f2ef">
@@ -45,12 +46,16 @@
             <libsw library="visualizer_sw" uuid="d069d9e0-8329-11df-9168-0002a5d5c51b"/>
             <libhw library="offload_effect" uuid="99fb2ecb-3426-4a0e-8082-1a1da5604b7d"/>
         </effectProxy>
+        <effectProxy name="dynamics_processing" library="proxy" uuid="dcf01474-8982-11ec-a8a3-0242ac120002">
+            <libsw library="dynamics_processing_sw" uuid="e0e6539b-1781-7261-676f-6d7573696340"/>
+            <libhw library="offload_effect" uuid="1bf15eb7-8f49-4fd8-8380-0767fd5680f3"/>
+        </effectProxy>
         <effect name="downmix" library="downmix" uuid="93f04452-e4fe-41cc-91f9-e475b6d1d69f"/>
         <effect name="loudness_enhancer" library="loudness_enhancer" uuid="fa415329-2034-4bea-b5dc-5b381c8d1e2c"/>
         <effect name="aec" library="offload_effect" uuid="28c28780-ec8b-48b6-8590-8c84557d797d"/>
         <effect name="ns" library="offload_effect" uuid="62ff2836-d050-43c3-9c2d-94a73dad2c64"/>
         <effect name="haptic_generator" library="haptic_generator" uuid="97c4acd1-8b82-4f2f-832e-c2fe5d7a9931"/>
-        <effect name="dynamics_processing" library="dynamics_processing" uuid="e0e6539b-1781-7261-676f-6d7573696340"/>
+        <effect name="spatializer" library="spatializer" uuid="cc4677de-ff72-11eb-9a03-0242ac130003"/>
     </effects>
     <postprocess>
     </postprocess>
diff --git a/audio/felix/config/audio_platform_configuration.xml b/audio/felix/config/audio_platform_configuration.xml
index 9a55347..bd62349 100644
--- a/audio/felix/config/audio_platform_configuration.xml
+++ b/audio/felix/config/audio_platform_configuration.xml
@@ -35,6 +35,7 @@
         <intf id="BE_VIRTUAL_VOICE_RX_TUNING" block_id="19"/>
         <intf id="BE_VIRTUAL_VOICE_TX_TUNING" block_id="19"/>
         <intf id="BE_HW_TX_INTF_0" block_id="134,128,137"/>
+        <intf id="BE_VIRTUAL_CRYSTAL_CLEAR_AUDIO_TUNING" block_id="138"/>
     </hw_intf>
 
     <product_lists>
@@ -177,18 +178,19 @@
         <!-- for output with AUDIO_OUTPUT_FLAG_PRIMARY|AUDIO_OUTPUT_FLAG_FAST, 4 * 10ms buffer -->
         <usecase id="UC_LOW_LATENCY_PLAYBACK" dev1="1" dyn_path="true" dsp_vol="false" mmap="false" period="10" period_num="4"/>
         <!-- for output with AUDIO_OUTPUT_FLAG_MMAP_NOIRQ, 80 periods * 48 frames/period(=1ms w/ 48k sample rate) * 4 bytes/frame = 15360 bytes -->
-        <usecase id="UC_MMAP_PLAYBACK" dev1="0" dyn_path="true" dsp_vol="false" mmap="true" period="1" period_num="80"/>
+        <usecase id="UC_MMAP_PLAYBACK" dev1="0" dyn_path="true" dsp_vol="false" mmap="true" period="1" period_num="40"/>
         <!-- for output with AUDIO_OUTPUT_FLAG_DEEP_BUFFER, 4 * 20ms buffer -->
         <usecase id="UC_DEEP_BUFFER_PLAYBACK" dev1="5" dyn_path="true" dsp_vol="false" mmap="false" period="20" period_num="4"/>
         <!-- dev1: voice-call downlink dev2: voice-clal uplink -->
         <usecase id="UC_VOICE_CALL" dev1="4" dev2="11"/>
-        <usecase id="UC_IMMERSIVE_PLAYBACK" dev1="3"/>
+        <!-- for output with flag AUDIO_OUTPUT_SPATIALIZER -->
+        <usecase id="UC_IMMERSIVE_PLAYBACK" dev1="3" dyn_path="true" dsp_vol="false" mmap="false" period="10" period_num="3"/>
         <!-- for output with AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD, 4 * 128KB buffer -->
         <usecase id="UC_COMPRESSED_OFFLOAD_PLAYBACK" dev1="6" dyn_path="true" dsp_vol="true" mmap="false" period="131072" period_num="4" pre_proc_id="14"/>
         <!-- dev1: audio dev2: haptic -->
         <usecase id="UC_HAPTIC_AUDIO" dev1="2" dev2="7" period="10" period_num="4"/>
         <!-- for VOIP output, 4 * 10ms buffer -->
-        <usecase id="UC_VOIP_PLAYBACK" dev1="16" dyn_path="true" dsp_vol="true" mmap="false" period="10" period_num="4"/>
+        <usecase id="UC_VOIP_PLAYBACK" dev1="16" dyn_path="true" dsp_vol="true" mmap="false" period="10" period_num="4" pcm_ch="2"/>
         <!-- for input -->
         <usecase id="UC_AUDIO_RECORD" dev1="8" dyn_path="true" dsp_vol="false" mmap="false" period="20" period_num="4"/>
         <usecase id="UC_HOSTLESS_UL" dev1="15"/>
@@ -197,10 +199,10 @@
         <!-- for input wit AUDIO_INPUT_FLAG_FAST  480 periods * 1ms buffer, 16-bit, 2ch, buffer size 92160 bytes-->
         <usecase id="UC_LOW_LATENCY_AUDIO_RECORD" dev1="10" dyn_path="true" dsp_vol="false" mmap="true" period="1" period_num="480"/>
         <!-- for input wit AUDIO_INPUT_FLAG_MMAP_NOIRQ 240 periods * 1ms buffer, 32-bit,2 ch, buffer size 92160 bytes -->
-        <usecase id="UC_MMAP_RECORD" dev1="9" dyn_path="true" dsp_vol="false" mmap="true" period="1" period_num="240"/>
+        <usecase id="UC_MMAP_RECORD" dev1="9" dyn_path="true" mmap="true" period="1" period_num="240"/>
         <!-- for hifi -->
-        <usecase id="UC_HIFI_PLAYBACK" dev1="25"/>
-        <usecase id="UC_HIFI_RECORD" dev1="26"/>
+        <usecase id="UC_HIFI_PLAYBACK" dev1="25" period="20" period_num="4"/>
+        <usecase id="UC_HIFI_RECORD" dev1="26" period="20" period_num="4"/>
     </usecase_attr>
 
     <dsp_latency>
@@ -218,6 +220,10 @@
             <be_cfg be_id="OUT_A2DP_BE_CFG" latency="180000"/>
         </usecase>
 
+        <usecase id="UC_IMMERSIVE_PLAYBACK" type="playback">
+            <be_cfg be_id="OUT_A2DP_BE_CFG" latency="100000"/>
+        </usecase>
+
         <usecase id="UC_AUDIO_RECORD" type="capture">
             <be_cfg be_id="IN_CAMCORDER_LANDSCAPE_BE_CFG" latency="160000"/>
             <be_cfg be_id="IN_CAMCORDER_INVERT_LANDSCAPE_BE_CFG" latency="160000"/>
@@ -225,6 +231,8 @@
             <be_cfg be_id="IN_CAMCORDER_SELFIE_LANDSCAPE_BE_CFG" latency="160000"/>
             <be_cfg be_id="IN_CAMCORDER_SELFIE_INVERT_LANDSCAPE_BE_CFG" latency="160000"/>
             <be_cfg be_id="IN_CAMCORDER_SELFIE_PORTRAIT_BE_CFG" latency="160000"/>
+            <be_cfg be_id="IN_CAMCORDER_MIC_BE_CFG" latency="160000"/>
+            <be_cfg be_id="IN_CAMCORDER_TRIPLE_MIC_BE_CFG" latency="160000"/>
             <be_cfg be_id="IN_BTSCO_MIC_BE_CFG" latency="40000"/>
             <be_cfg be_id="IN_BTSCO_MIC_NREC_BE_CFG" latency="40000"/>
             <be_cfg be_id="IN_BTSCO_MIC_WB_BE_CFG" latency="40000"/>
@@ -233,6 +241,11 @@
     </dsp_latency>
 
     <soundcard_name name="google,aoc-snd-card" />
+    <features>
+        <feature name="ThermalThrottle=Type:SKIN,Name:VIRTUAL-SKIN"/>
+        <feature name="BatteryThrottle=Type:BCL_VOLTAGE,Name:BCL_AUDIO_BAACL,Strategy:MediaSpeakerAndScreenOn"/>
+        <feature name="PlaybackThermalThrottle=PollWaitMs:20000,ThermistorName:VIRTUAL-SKIN,ThermistorType:SKIN,ThrottlingSeverity:LIGHT"/>
+    </features>
 
     <cfg_attr>
         <cfg id="OUT_SPEAKER_BE_CFG" intf_name="TDM_RX_0" mux="HW_MUX_GP_0" tuning_id="2"/>
@@ -267,6 +280,7 @@
         <cfg id="IN_USB_HEADSET_MIC_BE_CFG" mux="HW_MUX_GP_0"/>
         <cfg id="IN_VOICECALL_USB_HEADSET_MIC_BE_CFG" mux="HW_MUX_GP_0"/>
         <cfg id="IN_UNPROCESSED_USB_HEADSET_MIC_BE_CFG" mux="HW_MUX_GP_0"/>
+        <cfg id="IN_VOICE_RECOGN_MIC_BE_CFG" tuning_id="77"/>
     </cfg_attr>
 
     <xlate_id>
@@ -281,13 +295,14 @@
 
     <device_handle>
         <handler libname="audio_bt_aoc.so"/>
-        <handler libname="audio_usb_aoc.so" argu="MaxSamplingRate=96000,UnsupportedFormat=S24_LE"/>
+        <handler libname="audio_usb_aoc.so" argu="MaxSamplingRate=192000,UnsupportedFormat=S24_LE,MaxCapPacketInterval=125,MaxCapSampleRate=192000,MaxCapBitWidth=32,MaxCapChannel=2,EnableHifi192kMultichannel=0"/>
     </device_handle>
 
     <external_module>
-        <module libname="audio_waves_aoc.so" argu="Sink=SPK:1"/>
-        <module libname="audio_spk_35l41.so" argu="EnableDualControl"/>
-        <module libname="audio_fortemedia_aoc.so"/>
+        <module libname="audio_waves_aoc.so" argu="Sink=SPK:1 ThermistorsName=VIRTUAL-SKIN Extensions=StereoSpatializer" />
+        <module libname="audio_spk_35l41.so" argu="AcousticShockProtection"/>
+        <module libname="audio_cca_aoc.so"/>
+        <module libname="audio_fortemedia_aoc.so" argu="DL_CH=y VoIP_DLCHs=SPK:2,USB:2 VoIP_Rate=32000 BOOST_USB_SWB_CLK=y SHARED_MODULE=1130578253"/>
         <module libname="liboffloadeffect.so"/>
         <module libname="audio_amcs_ext.so"/>
         <module libname="audio_bluenote_aoc.so"/>
diff --git a/audio/felix/config/audio_policy_configuration.xml b/audio/felix/config/audio_policy_configuration.xml
index c8f3f6c..1b44390 100644
--- a/audio/felix/config/audio_policy_configuration.xml
+++ b/audio/felix/config/audio_policy_configuration.xml
@@ -17,7 +17,6 @@
         <module name="primary" halVersion="2.0">
             <attachedDevices>
                 <item>Speaker</item>
-                <item>Speaker Safe</item>
                 <item>Earpiece</item>
                 <item>Built-In Mic</item>
                 <item>Built-In Back Mic</item>
@@ -27,16 +26,17 @@
             </attachedDevices>
             <defaultOutputDevice>Speaker</defaultOutputDevice>
             <mixPorts>
-                <mixPort name="primary output" role="source" flags="AUDIO_OUTPUT_FLAG_PRIMARY AUDIO_OUTPUT_FLAG_FAST">
+                <mixPort name="primary output" role="source" flags="AUDIO_OUTPUT_FLAG_PRIMARY AUDIO_OUTPUT_FLAG_FAST"
+                         recommendedMuteDurationMs="40">
                     <profile name="" format="AUDIO_FORMAT_PCM_FLOAT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="deep buffer" role="source" flags="AUDIO_OUTPUT_FLAG_DEEP_BUFFER">
-                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                    <profile name="" format="AUDIO_FORMAT_PCM_FLOAT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="compressed_offload" role="source"
-                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING">
+                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING AUDIO_OUTPUT_FLAG_GAPLESS_OFFLOAD">
                     <profile name="" format="AUDIO_FORMAT_MP3"
                              samplingRates="8000 16000 24000 32000 44100 48000"
                              channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
@@ -60,11 +60,11 @@
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="mmap_no_irq_out" role="source" flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_MMAP_NOIRQ">
-                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                    <profile name="" format="AUDIO_FORMAT_PCM_FLOAT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
-                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_FAST AUDIO_OUTPUT_FLAG_DEEP_BUFFER">
-                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_SPATIALIZER">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="incall playback" role="source"
@@ -132,8 +132,6 @@
                 </devicePort>
                 <devicePort tagName="Speaker" type="AUDIO_DEVICE_OUT_SPEAKER" role="sink">
                 </devicePort>
-                <devicePort tagName="Speaker Safe" type="AUDIO_DEVICE_OUT_SPEAKER_SAFE" role="sink">
-                </devicePort>
                 <devicePort tagName="BT SCO" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO" role="sink">
                 </devicePort>
                 <devicePort tagName="BT SCO Headset" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO_HEADSET" role="sink">
@@ -154,20 +152,32 @@
                 <devicePort tagName="BT SCO Headset Mic" type="AUDIO_DEVICE_IN_BLUETOOTH_SCO_HEADSET" role="source">
                 </devicePort>
                 <devicePort tagName="BT A2DP Out" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP" role="sink"
-                            encodedFormats="AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
                              samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </devicePort>
                 <devicePort tagName="BT A2DP Headphones" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_HEADPHONES" role="sink"
-                            encodedFormats="AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
                              samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </devicePort>
                 <devicePort tagName="BT A2DP Speaker" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_SPEAKER" role="sink"
-                            encodedFormats="AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
                              samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </devicePort>
+                <devicePort tagName="BT BLE Headset" type="AUDIO_DEVICE_OUT_BLE_HEADSET" role="sink"
+                            encodedFormats="AUDIO_FORMAT_LC3">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+                <devicePort tagName="BT BLE Speaker" type="AUDIO_DEVICE_OUT_BLE_SPEAKER" role="sink"
+                            encodedFormats="AUDIO_FORMAT_LC3">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+                <devicePort tagName="BLE Headset Mic" type="AUDIO_DEVICE_IN_BLE_HEADSET" role="source">
+                </devicePort>
                 <devicePort tagName="USB Device In" type="AUDIO_DEVICE_IN_USB_DEVICE" role="source">
                 </devicePort>
                 <devicePort tagName="USB Headset In" type="AUDIO_DEVICE_IN_USB_HEADSET" role="source">
@@ -182,39 +192,41 @@
             <routes>
                 <route type="mix" sink="Speaker"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,immersive_out"/>
-                <route type="mix" sink="Speaker Safe"
-                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="Earpiece"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="BT A2DP Out"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT A2DP Headphones"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT A2DP Speaker"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT BLE Headset"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT BLE Speaker"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="USB Device Out"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
                 <route type="mix" sink="USB Headset Out"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
                 <route type="mix" sink="BT SCO"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Headset"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Car Kit"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="Telephony Tx" sources="incall playback,voice call tx" />
                 <route type="mix" sink="primary input"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic,BLE Headset Mic"/>
                 <route type="mix" sink="hotword input"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic,BLE Headset Mic"/>
                 <route type="mix" sink="incall capture" sources="Voice Call And Telephony Rx" />
                 <route type="mix" sink="voice call rx" sources="Voice Call And Telephony Rx" />
                 <route type="mix" sink="voip_tx"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic,BLE Headset Mic"/>
                 <route type="mix" sink="fast input"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="mmap_no_irq_in"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="hifi_input" sources="USB Device In,USB Headset In" />
                 <route type="mix" sink="echo_ref_input" sources="Echo Ref In"/>
             </routes>
diff --git a/audio/felix/config/audio_policy_configuration_a2dp_offload_disabled.xml b/audio/felix/config/audio_policy_configuration_a2dp_offload_disabled.xml
index 3c78481..eb8560c 100644
--- a/audio/felix/config/audio_policy_configuration_a2dp_offload_disabled.xml
+++ b/audio/felix/config/audio_policy_configuration_a2dp_offload_disabled.xml
@@ -17,7 +17,6 @@
         <module name="primary" halVersion="2.0">
             <attachedDevices>
                 <item>Speaker</item>
-                <item>Speaker Safe</item>
                 <item>Earpiece</item>
                 <item>Built-In Mic</item>
                 <item>Built-In Back Mic</item>
@@ -36,7 +35,7 @@
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="compressed_offload" role="source"
-                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING">
+                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING AUDIO_OUTPUT_FLAG_GAPLESS_OFFLOAD">
                     <profile name="" format="AUDIO_FORMAT_MP3"
                              samplingRates="8000 16000 24000 32000 44100 48000"
                              channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
@@ -63,8 +62,8 @@
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
-                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_FAST AUDIO_OUTPUT_FLAG_DEEP_BUFFER">
-                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_SPATIALIZER">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="incall playback" role="source"
@@ -132,8 +131,6 @@
                 </devicePort>
                 <devicePort tagName="Speaker" type="AUDIO_DEVICE_OUT_SPEAKER" role="sink">
                 </devicePort>
-                <devicePort tagName="Speaker Safe" type="AUDIO_DEVICE_OUT_SPEAKER_SAFE" role="sink">
-                </devicePort>
                 <devicePort tagName="BT SCO" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO" role="sink">
                 </devicePort>
                 <devicePort tagName="BT SCO Headset" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO_HEADSET" role="sink">
@@ -169,8 +166,6 @@
             <routes>
                 <route type="mix" sink="Speaker"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,immersive_out"/>
-                <route type="mix" sink="Speaker Safe"
-                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="Earpiece"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="USB Device Out"
@@ -178,11 +173,11 @@
                 <route type="mix" sink="USB Headset Out"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
                 <route type="mix" sink="BT SCO"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Headset"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Car Kit"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="Telephony Tx" sources="incall playback,voice call tx" />
                 <route type="mix" sink="primary input"
                        sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
@@ -193,9 +188,9 @@
                 <route type="mix" sink="voip_tx"
                        sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="fast input"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="mmap_no_irq_in"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="hifi_input" sources="USB Device In,USB Headset In" />
                 <route type="mix" sink="echo_ref_input" sources="Echo Ref In"/>
             </routes>
diff --git a/audio/felix/config/audio_policy_configuration_bluetooth_legacy_hal.xml b/audio/felix/config/audio_policy_configuration_bluetooth_legacy_hal.xml
index e21e5e4..1863d5a 100644
--- a/audio/felix/config/audio_policy_configuration_bluetooth_legacy_hal.xml
+++ b/audio/felix/config/audio_policy_configuration_bluetooth_legacy_hal.xml
@@ -17,7 +17,6 @@
         <module name="primary" halVersion="2.0">
             <attachedDevices>
                 <item>Speaker</item>
-                <item>Speaker Safe</item>
                 <item>Earpiece</item>
                 <item>Built-In Mic</item>
                 <item>Built-In Back Mic</item>
@@ -36,7 +35,7 @@
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
                 <mixPort name="compressed_offload" role="source"
-                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING">
+                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING AUDIO_OUTPUT_FLAG_GAPLESS_OFFLOAD">
                     <profile name="" format="AUDIO_FORMAT_MP3"
                              samplingRates="8000 16000 24000 32000 44100 48000"
                              channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
@@ -63,10 +62,6 @@
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
                              samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
                 </mixPort>
-                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_FAST AUDIO_OUTPUT_FLAG_DEEP_BUFFER">
-                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
-                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
-                </mixPort>
                 <mixPort name="incall playback" role="source"
                          flags="AUDIO_OUTPUT_FLAG_INCALL_MUSIC">
                     <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
@@ -132,8 +127,6 @@
                 </devicePort>
                 <devicePort tagName="Speaker" type="AUDIO_DEVICE_OUT_SPEAKER" role="sink">
                 </devicePort>
-                <devicePort tagName="Speaker Safe" type="AUDIO_DEVICE_OUT_SPEAKER_SAFE" role="sink">
-                </devicePort>
                 <devicePort tagName="BT SCO" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO" role="sink">
                 </devicePort>
                 <devicePort tagName="BT SCO Headset" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO_HEADSET" role="sink">
@@ -169,8 +162,6 @@
             <routes>
                 <route type="mix" sink="Speaker"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,immersive_out"/>
-                <route type="mix" sink="Speaker Safe"
-                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="Earpiece"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
                 <route type="mix" sink="USB Device Out"
@@ -178,11 +169,11 @@
                 <route type="mix" sink="USB Headset Out"
                        sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
                 <route type="mix" sink="BT SCO"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Headset"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="BT SCO Car Kit"
-                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx"/>
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
                 <route type="mix" sink="Telephony Tx" sources="incall playback,voice call tx" />
                 <route type="mix" sink="primary input"
                        sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
@@ -193,9 +184,9 @@
                 <route type="mix" sink="voip_tx"
                        sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="fast input"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="mmap_no_irq_in"
-                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In"/>
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
                 <route type="mix" sink="hifi_input" sources="USB Device In,USB Headset In" />
                 <route type="mix" sink="echo_ref_input" sources="Echo Ref In"/>
             </routes>
diff --git a/audio/felix/config/audio_policy_configuration_le_offload_disabled.xml b/audio/felix/config/audio_policy_configuration_le_offload_disabled.xml
new file mode 100644
index 0000000..bf54670
--- /dev/null
+++ b/audio/felix/config/audio_policy_configuration_le_offload_disabled.xml
@@ -0,0 +1,249 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<!-- Copyright (C) 2020 The Android Open Source Project
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+          http://www.apache.org/licenses/LICENSE-2.0
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+<audioPolicyConfiguration version="7.0" xmlns:xi="http://www.w3.org/2001/XInclude">
+    <globalConfiguration speaker_drc_enabled="false" call_screen_mode_supported="true" />
+    <modules>
+        <!-- Primary Audio HAL -->
+        <module name="primary" halVersion="2.0">
+            <attachedDevices>
+                <item>Speaker</item>
+                <item>Speaker Safe</item>
+                <item>Earpiece</item>
+                <item>Built-In Mic</item>
+                <item>Built-In Back Mic</item>
+                <item>Telephony Tx</item>
+                <item>Voice Call And Telephony Rx</item>
+                <item>Echo Ref In</item>
+            </attachedDevices>
+            <defaultOutputDevice>Speaker</defaultOutputDevice>
+            <mixPorts>
+                <mixPort name="primary output" role="source" flags="AUDIO_OUTPUT_FLAG_PRIMARY AUDIO_OUTPUT_FLAG_FAST">
+                    <profile name="" format="AUDIO_FORMAT_PCM_FLOAT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="deep buffer" role="source" flags="AUDIO_OUTPUT_FLAG_DEEP_BUFFER">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="compressed_offload" role="source"
+                         flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD AUDIO_OUTPUT_FLAG_NON_BLOCKING">
+                    <profile name="" format="AUDIO_FORMAT_MP3"
+                             samplingRates="8000 16000 24000 32000 44100 48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
+                    <profile name="" format="AUDIO_FORMAT_AAC_LC"
+                             samplingRates="8000 16000 24000 32000 44100 48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
+                    <profile name="" format="AUDIO_FORMAT_AAC_HE_V1"
+                             samplingRates="8000 16000 24000 32000 44100 48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
+                    <profile name="" format="AUDIO_FORMAT_AAC_HE_V2"
+                             samplingRates="8000 16000 24000 32000 44100 48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO AUDIO_CHANNEL_OUT_MONO"/>
+                </mixPort>
+                <mixPort name="haptic" role="source">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO_HAPTIC_AB" />
+                </mixPort>
+                <mixPort name="raw" role="source" flags="AUDIO_OUTPUT_FLAG_RAW AUDIO_OUTPUT_FLAG_FAST">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="mmap_no_irq_out" role="source" flags="AUDIO_OUTPUT_FLAG_DIRECT AUDIO_OUTPUT_FLAG_MMAP_NOIRQ">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="immersive_out" role="source" flags="AUDIO_OUTPUT_FLAG_SPATIALIZER">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="incall playback" role="source"
+                         flags="AUDIO_OUTPUT_FLAG_INCALL_MUSIC">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO" />
+                </mixPort>
+                <mixPort name="voice call tx" role="source">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_OUT_STEREO" />
+                </mixPort>
+                <mixPort name="voip_rx" role="source"
+                         flags="AUDIO_OUTPUT_FLAG_VOIP_RX">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                           samplingRates="48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+                <mixPort name="primary input" role="sink">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO AUDIO_CHANNEL_INDEX_MASK_3"/>
+                </mixPort>
+                <mixPort name="hotword input" role="sink" flags="AUDIO_INPUT_FLAG_HW_HOTWORD" maxActiveCount="0" >
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="8000 11025 12000 16000 22050 24000 32000 44100 48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+                </mixPort>
+                <mixPort name="incall capture" role="sink">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO"/>
+                </mixPort>
+                <mixPort name="voice call rx" role="sink">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO"/>
+                </mixPort>
+                <mixPort name="voip_tx" role="sink"
+                         flags="AUDIO_INPUT_FLAG_VOIP_TX">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000" channelMasks="AUDIO_CHANNEL_IN_MONO"/>
+                </mixPort>
+                <mixPort name="fast input" role="sink" flags="AUDIO_INPUT_FLAG_RAW AUDIO_INPUT_FLAG_FAST">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+                </mixPort>
+                <mixPort name="mmap_no_irq_in" role="sink" flags="AUDIO_INPUT_FLAG_MMAP_NOIRQ">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+                </mixPort>
+                <mixPort name="hifi_playback" role="source" />
+                <mixPort name="hifi_input" role="sink" />
+                <mixPort name="echo_ref_input" role="sink">
+                    <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
+                             samplingRates="48000"
+                             channelMasks="AUDIO_CHANNEL_IN_STEREO"/>
+                </mixPort>
+            </mixPorts>
+            <devicePorts>
+                <!-- Output devices declaration, i.e. Sink DEVICE PORT -->
+                <devicePort tagName="Earpiece" type="AUDIO_DEVICE_OUT_EARPIECE" role="sink">
+                </devicePort>
+                <devicePort tagName="Speaker" type="AUDIO_DEVICE_OUT_SPEAKER" role="sink">
+                </devicePort>
+                <devicePort tagName="Speaker Safe" type="AUDIO_DEVICE_OUT_SPEAKER_SAFE" role="sink">
+                </devicePort>
+                <devicePort tagName="BT SCO" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO" role="sink">
+                </devicePort>
+                <devicePort tagName="BT SCO Headset" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO_HEADSET" role="sink">
+                </devicePort>
+                <devicePort tagName="BT SCO Car Kit" type="AUDIO_DEVICE_OUT_BLUETOOTH_SCO_CARKIT" role="sink">
+                </devicePort>
+                <devicePort tagName="USB Device Out" type="AUDIO_DEVICE_OUT_USB_DEVICE" role="sink">
+                </devicePort>
+                <devicePort tagName="USB Headset Out" type="AUDIO_DEVICE_OUT_USB_HEADSET" role="sink">
+                </devicePort>
+                <devicePort tagName="Telephony Tx" type="AUDIO_DEVICE_OUT_TELEPHONY_TX" role="sink">
+                </devicePort>
+                <!-- Input devices declaration, i.e. Source DEVICE PORT -->
+                <devicePort tagName="Built-In Mic" type="AUDIO_DEVICE_IN_BUILTIN_MIC" role="source">
+                </devicePort>
+                <devicePort tagName="Built-In Back Mic" type="AUDIO_DEVICE_IN_BACK_MIC" role="source">
+                </devicePort>
+                <devicePort tagName="BT SCO Headset Mic" type="AUDIO_DEVICE_IN_BLUETOOTH_SCO_HEADSET" role="source">
+                </devicePort>
+                <devicePort tagName="BT A2DP Out" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP" role="sink"
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+                <devicePort tagName="BT A2DP Headphones" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_HEADPHONES" role="sink"
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+                <devicePort tagName="BT A2DP Speaker" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_SPEAKER" role="sink"
+                            encodedFormats="AUDIO_FORMAT_OPUS AUDIO_FORMAT_AAC AUDIO_FORMAT_SBC">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="44100 48000" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+                <devicePort tagName="USB Device In" type="AUDIO_DEVICE_IN_USB_DEVICE" role="source">
+                </devicePort>
+                <devicePort tagName="USB Headset In" type="AUDIO_DEVICE_IN_USB_HEADSET" role="source">
+                </devicePort>
+                <!-- AUDIO_DEVICE_IN_VOICE_CALL and AUDIO_DEVICE_IN_TELEPHONY_RX are in the same value -->
+                <devicePort tagName="Voice Call And Telephony Rx" type="AUDIO_DEVICE_IN_VOICE_CALL" role="source">
+                </devicePort>
+                <devicePort tagName="Echo Ref In" type="AUDIO_DEVICE_IN_ECHO_REFERENCE" role="source">
+                </devicePort>
+            </devicePorts>
+            <!-- route declaration, i.e. list all available sources for a given sink -->
+            <routes>
+                <route type="mix" sink="Speaker"
+                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,immersive_out"/>
+                <route type="mix" sink="Earpiece"
+                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx"/>
+                <route type="mix" sink="BT A2DP Out"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT A2DP Headphones"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT A2DP Speaker"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,immersive_out,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="USB Device Out"
+                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
+                <route type="mix" sink="USB Headset Out"
+                       sources="primary output,deep buffer,haptic,raw,compressed_offload,mmap_no_irq_out,voip_rx,hifi_playback,immersive_out"/>
+                <route type="mix" sink="BT SCO"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT SCO Headset"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="BT SCO Car Kit"
+                       sources="primary output,deep buffer,haptic,compressed_offload,voip_rx,raw,mmap_no_irq_out"/>
+                <route type="mix" sink="Telephony Tx" sources="incall playback,voice call tx" />
+                <route type="mix" sink="primary input"
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                <route type="mix" sink="hotword input"
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                <route type="mix" sink="incall capture" sources="Voice Call And Telephony Rx" />
+                <route type="mix" sink="voice call rx" sources="Voice Call And Telephony Rx" />
+                <route type="mix" sink="voip_tx"
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                <route type="mix" sink="fast input"
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                <route type="mix" sink="mmap_no_irq_in"
+                       sources="Built-In Mic,Built-In Back Mic,USB Device In,USB Headset In,BT SCO Headset Mic"/>
+                <route type="mix" sink="hifi_input" sources="USB Device In,USB Headset In" />
+                <route type="mix" sink="echo_ref_input" sources="Echo Ref In"/>
+            </routes>
+        </module>
+        <!-- Bluetooth Audio HAL -->
+        <xi:include href="bluetooth_audio_policy_configuration_7_0.xml"/>
+        <!-- Usb Audio HAL -->
+        <module name="usbv2" halVersion="2.0">
+            <mixPorts>
+                <mixPort name="usb_accessory output" role="source">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="44100" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </mixPort>
+            </mixPorts>
+            <devicePorts>
+                <devicePort tagName="USB Host Out" type="AUDIO_DEVICE_OUT_USB_ACCESSORY" role="sink">
+                    <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                             samplingRates="44100" channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+                </devicePort>
+            </devicePorts>
+            <routes>
+                <route type="mix" sink="USB Host Out"
+                       sources="usb_accessory output"/>
+            </routes>
+        </module>
+        <!-- Remote Submix Audio HAL -->
+        <xi:include href="r_submix_audio_policy_configuration.xml"/>
+    </modules>
+    <!-- End of Modules section -->
+    <!-- Volume section -->
+    <xi:include href="audio_policy_volumes.xml"/>
+    <xi:include href="default_volume_tables.xml"/>
+    <!-- End of Volume section -->
+</audioPolicyConfiguration>
diff --git a/audio/felix/config/audio_policy_volumes.xml b/audio/felix/config/audio_policy_volumes.xml
new file mode 100644
index 0000000..7570dff
--- /dev/null
+++ b/audio/felix/config/audio_policy_volumes.xml
@@ -0,0 +1,243 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Copyright (C) 2015 The Android Open Source Project
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+<!-- Volume section defines a volume curve for a given use case and device category.
+It contains a list of points of this curve expressing the attenuation in Millibels for a given
+volume index from 0 to 100.
+<volume stream=”AUDIO_STREAM_MUSIC” deviceCategory=””>
+<point>0,-9600</point>
+<point>100,0</point>
+</volume>
+-->
+
+<volumes>
+    <volume stream="AUDIO_STREAM_VOICE_CALL" deviceCategory="DEVICE_CATEGORY_HEADSET">
+        <point>0,-4200</point>
+        <point>33,-2800</point>
+        <point>66,-1400</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_VOICE_CALL" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>0,-2400</point>
+        <point>33,-1600</point>
+        <point>66,-800</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_VOICE_CALL" deviceCategory="DEVICE_CATEGORY_EARPIECE">
+        <point>0,-2400</point>
+        <point>33,-1600</point>
+        <point>66,-800</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_VOICE_CALL" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                             ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_VOICE_CALL" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                             ref="DEFAULT_NON_MUTABLE_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_SYSTEM" deviceCategory="DEVICE_CATEGORY_HEADSET">
+        <point>1,-3000</point>
+        <point>33,-2600</point>
+        <point>66,-2200</point>
+        <point>100,-1800</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_SYSTEM" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-4960</point>
+        <point>33,-3650</point>
+        <point>66,-2650</point>
+        <point>100,-1250</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_SYSTEM" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                         ref="DEFAULT_SYSTEM_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_SYSTEM" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                         ref="DEFAULT_DEVICE_CATEGORY_EXT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_SYSTEM" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                         ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_RING" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                       ref="DEFAULT_DEVICE_CATEGORY_HEADSET_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_RING" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-4735</point>
+        <point>14,-4170</point>
+        <point>28,-3600</point>
+        <point>71,-2030</point>
+        <point>100,-200</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_RING" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                       ref="DEFAULT_DEVICE_CATEGORY_EARPIECE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_RING" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                       ref="DEFAULT_DEVICE_CATEGORY_EXT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_RING" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                       ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_MUSIC" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                        ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_MUSIC" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-6400</point>
+        <point>12,-5360</point>
+        <point>20,-4700</point>
+        <point>28,-4020</point>
+        <point>36,-3570</point>
+        <point>52,-2765</point>
+        <point>60,-2300</point>
+        <point>68,-1950</point>
+        <point>80,-1170</point>
+        <point>88,-750</point>
+        <point>92,-490</point>
+        <point>96,-210</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_MUSIC" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                        ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_MUSIC" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                        ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_MUSIC" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                        ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ALARM" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                        ref="DEFAULT_NON_MUTABLE_HEADSET_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ALARM" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>0,-5900</point>
+        <point>17,-4650</point>
+        <point>34,-3210</point>
+        <point>83,-1430</point>
+        <point>100,-400</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_ALARM" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                        ref="DEFAULT_NON_MUTABLE_EARPIECE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ALARM" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                        ref="DEFAULT_NON_MUTABLE_EXT_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ALARM" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                        ref="DEFAULT_NON_MUTABLE_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_NOTIFICATION" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                               ref="DEFAULT_DEVICE_CATEGORY_HEADSET_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_NOTIFICATION" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-4920</point>
+        <point>14,-4390</point>
+        <point>57,-2740</point>
+        <point>85,-1570</point>
+        <point>100,-300</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_NOTIFICATION" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                               ref="DEFAULT_DEVICE_CATEGORY_EARPIECE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_NOTIFICATION" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                               ref="DEFAULT_DEVICE_CATEGORY_EXT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_NOTIFICATION" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                               ref="DEFAULT_DEVICE_CATEGORY_HEADSET_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_BLUETOOTH_SCO" deviceCategory="DEVICE_CATEGORY_HEADSET">
+        <point>0,-4200</point>
+        <point>33,-2800</point>
+        <point>66,-1400</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_BLUETOOTH_SCO" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>0,-2400</point>
+        <point>33,-1600</point>
+        <point>66,-800</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_BLUETOOTH_SCO" deviceCategory="DEVICE_CATEGORY_EARPIECE">
+        <point>0,-4200</point>
+        <point>33,-2800</point>
+        <point>66,-1400</point>
+        <point>100,0</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_BLUETOOTH_SCO" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                                ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_BLUETOOTH_SCO" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                                ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ENFORCED_AUDIBLE" deviceCategory="DEVICE_CATEGORY_HEADSET">
+        <point>1,-3000</point>
+        <point>33,-2600</point>
+        <point>66,-2200</point>
+        <point>100,-1800</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_ENFORCED_AUDIBLE" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-4960</point>
+        <point>33,-3920</point>
+        <point>66,-2850</point>
+        <point>100,-1750</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_ENFORCED_AUDIBLE" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                                   ref="DEFAULT_SYSTEM_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ENFORCED_AUDIBLE" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                                   ref="DEFAULT_DEVICE_CATEGORY_EXT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ENFORCED_AUDIBLE" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                                   ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_DTMF" deviceCategory="DEVICE_CATEGORY_HEADSET">
+        <point>1,-3000</point>
+        <point>33,-2600</point>
+        <point>66,-2200</point>
+        <point>100,-1800</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_DTMF" deviceCategory="DEVICE_CATEGORY_SPEAKER">
+        <point>1,-6460</point>
+        <point>33,-4490</point>
+        <point>66,-2460</point>
+        <point>100,-1280</point>
+    </volume>
+    <volume stream="AUDIO_STREAM_DTMF" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                       ref="DEFAULT_SYSTEM_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_DTMF" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                       ref="DEFAULT_DEVICE_CATEGORY_EXT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_DTMF" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                       ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_TTS" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                      ref="SILENT_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_TTS" deviceCategory="DEVICE_CATEGORY_SPEAKER"
+                                      ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_TTS" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                      ref="SILENT_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_TTS" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                      ref="SILENT_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_TTS" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                      ref="SILENT_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ACCESSIBILITY" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                                ref="DEFAULT_NON_MUTABLE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ACCESSIBILITY" deviceCategory="DEVICE_CATEGORY_SPEAKER"
+                                                ref="DEFAULT_NON_MUTABLE_SPEAKER_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ACCESSIBILITY" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                                ref="DEFAULT_NON_MUTABLE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ACCESSIBILITY" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                                ref="DEFAULT_NON_MUTABLE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ACCESSIBILITY" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                                ref="DEFAULT_NON_MUTABLE_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ASSISTANT" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                                ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ASSISTANT" deviceCategory="DEVICE_CATEGORY_SPEAKER"
+                                                ref="DEFAULT_DEVICE_CATEGORY_SPEAKER_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ASSISTANT" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                                ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ASSISTANT" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                                ref="DEFAULT_MEDIA_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_ASSISTANT" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                                ref="DEFAULT_HEARING_AID_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_REROUTING" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                            ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_REROUTING" deviceCategory="DEVICE_CATEGORY_SPEAKER"
+                                            ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_REROUTING" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                            ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_REROUTING" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                            ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_REROUTING" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                            ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_PATCH" deviceCategory="DEVICE_CATEGORY_HEADSET"
+                                        ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_PATCH" deviceCategory="DEVICE_CATEGORY_SPEAKER"
+                                        ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_PATCH" deviceCategory="DEVICE_CATEGORY_EARPIECE"
+                                        ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_PATCH" deviceCategory="DEVICE_CATEGORY_EXT_MEDIA"
+                                        ref="FULL_SCALE_VOLUME_CURVE"/>
+    <volume stream="AUDIO_STREAM_PATCH" deviceCategory="DEVICE_CATEGORY_HEARING_AID"
+                                        ref="FULL_SCALE_VOLUME_CURVE"/>
+</volumes>
+
diff --git a/audio/felix/config/bluetooth_with_le_audio_policy_configuration_7_0.xml b/audio/felix/config/bluetooth_with_le_audio_policy_configuration_7_0.xml
new file mode 100644
index 0000000..8b2af59
--- /dev/null
+++ b/audio/felix/config/bluetooth_with_le_audio_policy_configuration_7_0.xml
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Bluetooth Audio HAL Audio Policy Configuration file -->
+<module name="bluetooth" halVersion="2.0">
+    <mixPorts>
+        <!-- A2DP Audio Ports -->
+        <mixPort name="a2dp output" role="source" flags="AUDIO_OUTPUT_FLAG_SPATIALIZER"/>
+        <!-- Hearing AIDs Audio Ports -->
+        <mixPort name="hearing aid output" role="source">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="24000 16000"
+                     channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+        </mixPort>
+        <!-- Le Audio Audio Ports -->
+        <mixPort name="le audio output" role="source" flags="AUDIO_OUTPUT_FLAG_SPATIALIZER">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="44100 48000"
+                     channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+        </mixPort>
+        <mixPort name="le audio input" role="sink">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="8000 16000 24000 32000 44100 48000"
+                     channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+            <profile name="" format="AUDIO_FORMAT_PCM_24_BIT_PACKED"
+                     samplingRates="8000 16000 24000 32000 44100 48000"
+                     channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+            <profile name="" format="AUDIO_FORMAT_PCM_32_BIT"
+                     samplingRates="8000 16000 24000 32000 44100 48000"
+                     channelMasks="AUDIO_CHANNEL_IN_MONO AUDIO_CHANNEL_IN_STEREO"/>
+        </mixPort>
+    </mixPorts>
+    <devicePorts>
+        <!-- A2DP Audio Ports -->
+        <devicePort tagName="BT A2DP Out" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP" role="sink">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="44100 48000 88200 96000"
+                     channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+        </devicePort>
+        <devicePort tagName="BT A2DP Headphones" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_HEADPHONES" role="sink">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="44100 48000 88200 96000"
+                     channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+        </devicePort>
+        <devicePort tagName="BT A2DP Speaker" type="AUDIO_DEVICE_OUT_BLUETOOTH_A2DP_SPEAKER" role="sink">
+            <profile name="" format="AUDIO_FORMAT_PCM_16_BIT"
+                     samplingRates="44100 48000 88200 96000"
+                     channelMasks="AUDIO_CHANNEL_OUT_STEREO"/>
+        </devicePort>
+        <!-- Hearing AIDs Audio Ports -->
+        <devicePort tagName="BT Hearing Aid Out" type="AUDIO_DEVICE_OUT_HEARING_AID" role="sink"/>
+        <!-- BLE Audio Ports -->
+        <devicePort tagName="BLE Headset Out" type="AUDIO_DEVICE_OUT_BLE_HEADSET" role="sink"/>
+        <devicePort tagName="BLE Speaker Out" type="AUDIO_DEVICE_OUT_BLE_SPEAKER" role="sink"/>
+        <devicePort tagName="BLE Headset In" type="AUDIO_DEVICE_IN_BLE_HEADSET" role="source"/>
+    </devicePorts>
+    <routes>
+        <route type="mix" sink="BT A2DP Out"
+               sources="a2dp output"/>
+        <route type="mix" sink="BT A2DP Headphones"
+               sources="a2dp output"/>
+        <route type="mix" sink="BT A2DP Speaker"
+               sources="a2dp output"/>
+        <route type="mix" sink="BT Hearing Aid Out"
+               sources="hearing aid output"/>
+        <route type="mix" sink="BLE Headset Out"
+               sources="le audio output"/>
+        <route type="mix" sink="le audio input"
+               sources="BLE Headset In"/>
+        <route type="mix" sink="BLE Speaker Out"
+               sources="le audio output"/>
+    </routes>
+</module>
\ No newline at end of file
diff --git a/audio/felix/config/mixer_paths.xml b/audio/felix/config/mixer_paths.xml
index 38e180b..35f399f 100644
--- a/audio/felix/config/mixer_paths.xml
+++ b/audio/felix/config/mixer_paths.xml
@@ -30,6 +30,9 @@
     <ctl name="PCM Stream Wait Time in MSec" value="100"/>
     <ctl name="Voice PCM Stream Wait Time in MSec" value="500"/>
 
+    <!-- Enable it when AOC is ready to trim delay and padding -->
+    <ctl name="Gapless Offload Enable" value="1"/>
+
     <!-- TDM 0 setting -->
     <ctl name="TDM_0_RX Chan" value="Four"/>
     <ctl name="TDM_0_RX Format" value="S32_LE"/>
@@ -44,13 +47,9 @@
     <ctl name="HAPTIC_RX Chan" value="Four"/>
     <ctl name="HAPTIC_RX nSlot" value="Four"/>
     <ctl name="RX Slots" id="0" value="2"/>
-    <ctl name="RX Slots" id="1" value="3"/>
-    <ctl name="HR RX Slots" id="0" value="2"/>
-    <ctl name="HR RX Slots" id="1" value="3"/>
-
-    <!-- Cirrus default 96K -->
-    <ctl name="Default 96K" value="1"/>
-    <ctl name="R Default 96K" value="1"/>
+    <ctl name="RX Slots" id="1" value="0"/>
+    <ctl name="HR RX Slots" id="0" value="3"/>
+    <ctl name="HR RX Slots" id="1" value="0"/>
 
     <!-- Cirrus Booster Amp TDM slot assignment-->
     <!-- RX slot -->
@@ -123,6 +122,11 @@
     <ctl name="R ASP TX4 Source" value="Zero" />
     <ctl name="E ASP TX4 Source" value="Zero" />
 
+    <!-- Cirrus fast switch init -->
+    <ctl name="Fast Use Case Switch Enable" value="0" />
+    <ctl name="Fast Use Case Delta File" value="fast_switch9.txt" />
+    <ctl name="R Fast Use Case Switch Enable" value="0" />
+    <ctl name="R Fast Use Case Delta File" value="fast_switch9.txt" />
 
     <!-- audio RX route initial/default value -->
     <ctl name="TDM_0_RX Mixer EP1" value="0"/>
@@ -136,6 +140,7 @@
     <ctl name="TDM_0_RX Mixer NoHost1" value="0"/>
     <ctl name="TDM_0_RX Mixer VOIP" value="0"/>
     <ctl name="TDM_0_RX Mixer RAW" value="0"/>
+    <ctl name="TDM_0_RX Mixer IMSV" value="0"/>
 
     <ctl name="TDM_1_RX Mixer EP1" value="0"/>
     <ctl name="TDM_1_RX Mixer EP2" value="0"/>
@@ -158,6 +163,7 @@
     <ctl name="USB_RX Mixer VOIP" value="0"/>
     <ctl name="USB_RX Mixer HIFI" value="0"/>
     <ctl name="USB_RX Mixer RAW" value="0"/>
+    <ctl name="USB_RX Mixer IMSV" value="0"/>
 
     <ctl name="BT_RX Mixer EP1" value="0"/>
     <ctl name="BT_RX Mixer EP2" value="0"/>
@@ -168,6 +174,8 @@
     <ctl name="BT_RX Mixer EP7" value="0"/>
     <ctl name="BT_RX Mixer NoHost1" value="0"/>
     <ctl name="BT_RX Mixer VOIP" value="0"/>
+    <ctl name="BT_RX Mixer IMSV" value="0"/>
+    <ctl name="BT_RX Mixer RAW" value="0"/>
 
     <ctl name="INCALL_RX Mixer EP1" value="0"/>
     <ctl name="INCALL_RX Mixer EP2" value="0"/>
@@ -402,6 +410,10 @@
         <ctl name="USB_RX Mixer RAW" value="1"/>
     </path>
 
+    <path name="raw-playbackP bt">
+        <ctl name="BT_RX Mixer RAW" value="1"/>
+    </path>
+
     <path name="raw-playbackP hearing-aid">
     </path>
 
@@ -416,6 +428,10 @@
         <ctl name="USB_RX Mixer EP1" value="1"/>
     </path>
 
+    <path name="mmap-playbackP bt">
+        <ctl name="BT_RX Mixer EP1" value="1"/>
+    </path>
+
     <path name="mmap-playbackP hearing-aid">
     </path>
 
@@ -613,6 +629,10 @@
         <ctl name="EP3 TX Mixer USB_TX" value="1"/>
     </path>
 
+    <path name="low-latency-recordC bt-mic">
+        <ctl name="EP3 TX Mixer BT_TX" value="1"/>
+    </path>
+
     <path name="mmap-recordC">
         <ctl name="EP2 TX Mixer INTERNAL_MIC_TX" value="1"/>
     </path>
@@ -621,11 +641,15 @@
         <ctl name="EP2 TX Mixer USB_TX" value="1"/>
     </path>
 
+    <path name="mmap-recordC bt-mic">
+        <ctl name="EP2 TX Mixer BT_TX" value="1"/>
+    </path>
+
     <!-- codec setting -->>
     <!-- Rx device -->
     <path name="handset">
         <ctl name="E PCM Source" value="ASP"/>
-        <ctl name="E AMP PCM Gain" value="6"/>
+        <ctl name="E AMP PCM Gain" value="9"/>
         <ctl name="ASPTX1 Slot Position" value="4"/>
         <ctl name="E ASPTX1 Slot Position" value="0"/>
         <ctl name="ASPTX2 Slot Position" value="5"/>
@@ -635,7 +659,7 @@
 
     <path name="voice-handset">
         <ctl name="E PCM Source" value="ASP"/>
-        <ctl name="E AMP PCM Gain" value="6"/>
+        <ctl name="E AMP PCM Gain" value="9"/>
         <ctl name="ASPTX1 Slot Position" value="4"/>
         <ctl name="E ASPTX1 Slot Position" value="0"/>
         <ctl name="ASPTX2 Slot Position" value="5"/>
@@ -654,21 +678,29 @@
     <path name="speaker">
         <ctl name="Main AMP Enable Switch" value="1"/>
         <ctl name="R Main AMP Enable Switch" value="1"/>
+        <ctl name="Fast Use Case Delta File" value="fast_switch3.txt" />
+        <ctl name="Fast Use Case Switch Enable" value="1" />
+        <ctl name="R Fast Use Case Delta File" value="fast_switch4.txt" />
+        <ctl name="R Fast Use Case Switch Enable" value="1" />
     </path>
 
-    <path name="voice-speaker">
-        <ctl name="ASP TX1 Source" value="VMON" />
-        <ctl name="R ASP TX1 Source" value="Zero" />
-        <ctl name="ASPTX1 Slot Position" value="0"/>
-        <ctl name="R ASPTX1 Slot Position" value="1"/>
-        <ctl name="ASPRX1 Slot Position" value="0"/>
-        <ctl name="R ASPRX1 Slot Position" value="1"/>
+   <path name="voice-speaker">
+        <ctl name="ASPTX1 Slot Position" value="1"/>
+        <ctl name="R ASPTX1 Slot Position" value="0"/>
+        <ctl name="Digital PCM Volume" value="825"/>
+        <ctl name="R Digital PCM Volume" value="825"/>
         <ctl name="Main AMP Enable Switch" value="1"/>
         <ctl name="R Main AMP Enable Switch" value="1"/>
+        <ctl name="Fast Use Case Delta File" value="fast_switch1.txt" />
+        <ctl name="Fast Use Case Switch Enable" value="1" />
+        <ctl name="R Fast Use Case Delta File" value="fast_switch2.txt" />
+        <ctl name="R Fast Use Case Switch Enable" value="1" />
     </path>
 
     <path name="speaker-safe">
         <ctl name="R Main AMP Enable Switch" value="1"/>
+        <ctl name="R Fast Use Case Delta File" value="fast_switch4.txt" />
+        <ctl name="R Fast Use Case Switch Enable" value="1" />
     </path>
 
     <path name="builtin-3mics">
@@ -706,7 +738,7 @@
     </path>
 
     <path name="speaker-mic-post">
-        <ctl name="MIC Record Soft Gain (dB)" value="0"/>
+        <ctl name="MIC Record Soft Gain (dB)" value="22"/>
     </path>
 
     <path name="voice-speaker-mic">
@@ -731,6 +763,7 @@
 
     <path name="voice-recog-mic">
         <path name="builtin-3mics" />
+        <ctl name="Mic Spatial Module Enable" value="0"/>
         <ctl name="MIC DC Blocker" value="1"/>
     </path>
 
diff --git a/audio/felix/config/mixer_paths_factory.xml b/audio/felix/config/mixer_paths_factory.xml
index e1776f4..410cbc2 100644
--- a/audio/felix/config/mixer_paths_factory.xml
+++ b/audio/felix/config/mixer_paths_factory.xml
@@ -8,6 +8,7 @@
     <ctl name="E Main AMP Enable Switch" value="0" />
     <ctl name="MIC HW Gain At Lower Power Mode (cB)" value="-160" />
     <ctl name="MIC HW Gain At High Power Mode (cB)" value="0" />
+    <ctl name="MIC Record Soft Gain (dB)" value="0"/>
 
     <ctl name="EP1 TX Mixer TDM_0_TX" value="0" />
     <ctl name="DEFAULT_MIC_ID" value="0" />
@@ -33,6 +34,7 @@
 
     <path name="mfg-record usb-headset-mic">
         <ctl name="Audio Capture Mic Source" value="USB_MIC"/>
+        <ctl name="USB Playback EP ID v2" value="0" />
         <ctl name="USB Capture FORMAT v2" value="1" />
         <ctl name="USB Config To AoC v2" value="1"/>
         <ctl name="EP1 TX Mixer USB_TX" value="1"/>
@@ -88,7 +90,7 @@
     </path>
 
     <path name="usb-capture-gain">
-        <ctl name="Headset Capture Volume" />
+        <ctl name="MIC Record Soft Gain (dB)" />
     </path>
 
     <path name="mic1-only">
@@ -136,7 +138,7 @@
         <ctl name="ASPTX2 Slot Position" value="4" />
         <ctl name="ASPTX3 Slot Position" value="5" />
         <ctl name="ASPTX4 Slot Position" value="6" />
-        <ctl name="E ASP TX1 Source" value="ASPRX1" />
+        <ctl name="E ASP TX1 Source" value="VMON" />
         <ctl name="E ASP TX2 Source" value="Zero" />
         <ctl name="E ASP TX3 Source" value="Zero" />
         <ctl name="E ASP TX4 Source" value="Zero" />
@@ -144,7 +146,7 @@
         <ctl name="R ASP TX2 Source" value="ASPRX1" />
         <ctl name="R ASP TX3 Source" value="Zero" />
         <ctl name="R ASP TX4 Source" value="Zero" />
-        <ctl name="ASP TX1 Source" value="ASPRX1" />
+        <ctl name="ASP TX1 Source" value="VMON" />
         <ctl name="ASP TX2 Source" value="Zero" />
         <ctl name="ASP TX3 Source" value="Zero" />
         <ctl name="ASP TX4 Source" value="Zero" />
@@ -282,6 +284,7 @@
 
     <path name="mfg-playback usb-headphones">
         <ctl name="USB Dev ID v2" value="2" />
+        <ctl name="USB Capture EP ID v2" value="0" />
         <ctl name="USB Playback EP ID v2" value="1" />
         <ctl name="USB Playback FORMAT v2" value="6" />
         <ctl name="USB Playback SR v2" value="48000" />
diff --git a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin
index 1ac4066..4cfb355 100644
--- a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin
+++ b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin
index 5a3a4f5..4703b83 100644
--- a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin
+++ b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin
index e12bcd2..7a402b0 100644
--- a/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin
+++ b/audio/felix/cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-cali.bin b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-cali.bin
index 853f77a..3c22f13 100644
--- a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-cali.bin
+++ b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-cali.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-diag.bin b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-diag.bin
index d7b5842..5ac8bce 100644
--- a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-diag.bin
+++ b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-diag.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-prot.bin b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-prot.bin
index 89b2267..a0676e1 100644
--- a/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-prot.bin
+++ b/audio/felix/cs35l41/fw/cs35l41-dsp1-spk-prot.bin
Binary files differ
diff --git a/audio/felix/cs35l41/fw/fast_switch1.txt b/audio/felix/cs35l41/fw/fast_switch1.txt
new file mode 100644
index 0000000..d453678
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch1.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2162689,2294032,2,7,0,17,4134355,1395882,8388607,2,985354123
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch2.txt b/audio/felix/cs35l41/fw/fast_switch2.txt
new file mode 100644
index 0000000..bcd1b74
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch2.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2166785,2294032,2,7,0,17,4134355,1456572,8388607,2,-1905595085
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch3.txt b/audio/felix/cs35l41/fw/fast_switch3.txt
new file mode 100644
index 0000000..c8badf2
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch3.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2162690,2294032,2,7,4194304,17,4134355,1395882,8388607,2,-632693564
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch4.txt b/audio/felix/cs35l41/fw/fast_switch4.txt
new file mode 100644
index 0000000..67bae09
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch4.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2166786,2294032,2,7,4194304,17,4134355,1456572,8388607,2,1855487612
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch5.txt b/audio/felix/cs35l41/fw/fast_switch5.txt
new file mode 100644
index 0000000..1b3b942
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch5.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2162691,2294032,2,7,0,17,4409979,1395882,8388607,2,-1659281083
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch6.txt b/audio/felix/cs35l41/fw/fast_switch6.txt
new file mode 100644
index 0000000..f93014c
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch6.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2166787,2294032,2,7,0,17,4409979,1456572,8388607,2,701023229
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch7.txt b/audio/felix/cs35l41/fw/fast_switch7.txt
new file mode 100644
index 0000000..f1387ce
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch7.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2162692,2294032,2,7,4194304,17,4409979,1395882,8388607,2,-1385516587
\ No newline at end of file
diff --git a/audio/felix/cs35l41/fw/fast_switch8.txt b/audio/felix/cs35l41/fw/fast_switch8.txt
new file mode 100644
index 0000000..5177e56
--- /dev/null
+++ b/audio/felix/cs35l41/fw/fast_switch8.txt
@@ -0,0 +1 @@
+16,4,768,1236,419376,2166788,2294032,2,7,4194304,17,4409979,1456572,8388607,2,431690605
\ No newline at end of file
diff --git a/audio/felix/tuning/bluenote/recording.gatf b/audio/felix/tuning/bluenote/recording.gatf
index 320cddb..c2df2c1 100644
--- a/audio/felix/tuning/bluenote/recording.gatf
+++ b/audio/felix/tuning/bluenote/recording.gatf
Binary files differ
diff --git a/audio/felix/tuning/bluenote/smartfeature.gstf b/audio/felix/tuning/bluenote/smartfeature.gstf
new file mode 100644
index 0000000..d174ae3
--- /dev/null
+++ b/audio/felix/tuning/bluenote/smartfeature.gstf
Binary files differ
diff --git a/audio/felix/tuning/bluenote/template.xml b/audio/felix/tuning/bluenote/template.xml
index 52a75ba..b8d06e2 100644
--- a/audio/felix/tuning/bluenote/template.xml
+++ b/audio/felix/tuning/bluenote/template.xml
@@ -43,6 +43,24 @@
       <param default="0" id="27" name="ch0_assignFrom" type="int32"/>
       <param default="1" id="28" name="ch1_assignFrom" type="int32"/>
       <param default="2" id="29" name="ch2_assignFrom" type="int32"/>
+      <param default="0.33" id="30" name="alpha_enhancedRate" type="float"/>
+      <param default="0" id="31" name="swapOutputLR" type="int32"/>
+      <struct id="32">
+        <param default="1.0" name="CB_alpha_lowband" type="float"/>
+        <param default="1.0" name="CB_alpha_midband" type="float"/>
+        <param default="1.0" name="CB_alpha_highband" type="float"/>
+      </struct>
+      <struct id="33">
+        <param default="1.0" name="CB_epsilon_lowband" type="float"/>
+        <param default="1.0" name="CB_epsilon_midband" type="float"/>
+        <param default="1.0" name="CB_epsilon_highband" type="float"/>
+      </struct>
+      <struct id="34">
+        <param default="13" name="CB_fc_low_mid" type="int32"/>
+        <param default="22" name="CB_fc_mid_high" type="int32"/>
+        <param default="5" name="CB_smooth_span" type="int32"/>
+        <param default="1.0" name="CB_forget_factor" type="float"/>
+      </struct>
     </module>
     <module id="7" name="Multi Channel IIR 2">
       <param default="0" id="0" max="3" name="opMode_" type="uint32"/>
@@ -234,6 +252,8 @@
         <param name="attackTime_ms" size="4" type="float"/>
         <param name="releaseTime_ms" size="4" type="float"/>
         <param name="hysteresis" size="4" type="float"/>
+        <param default="0" max="1" min="0" name="rms_manual_enable" type="uint32"/>
+        <param default="0" max="2" min="0" name="rms_channel" type="uint32"/>
       </struct>
       <struct id="17">
         <param max="30" min="-30" name="limiter_gain_dB" type="float"/>
diff --git a/audio/felix/tuning/fortemedia/BLUETOOTH.dat b/audio/felix/tuning/fortemedia/BLUETOOTH.dat
index 722b835..8de425a 100644
--- a/audio/felix/tuning/fortemedia/BLUETOOTH.dat
+++ b/audio/felix/tuning/fortemedia/BLUETOOTH.dat
Binary files differ
diff --git a/audio/felix/tuning/fortemedia/BLUETOOTH.mods b/audio/felix/tuning/fortemedia/BLUETOOTH.mods
index 21cd874..404d204 100644
--- a/audio/felix/tuning/fortemedia/BLUETOOTH.mods
+++ b/audio/felix/tuning/fortemedia/BLUETOOTH.mods
@@ -1,11 +1,12 @@
 #PLATFORM_NAME  gChip
 #EXPORT_FLAG  BLUETOOTH
-#SINGLE_API_VER  1.1.6
-#SAVE_TIME  2021-08-20 16:32:53
+#SINGLE_API_VER  1.2.1
+#SAVE_TIME  2022-08-23 16:06:42
 
 #CASE_NAME  BLUETOOTH-RESERVE1-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -258,12 +259,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -289,12 +290,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -310,10 +311,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0028    //TX_G_LFNS
@@ -322,12 +323,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -387,10 +388,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
 379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x0000    //TX_MORENS_TFMASK_TH
+381    0x0000    //TX_DRC_QUIET_FLOOR
+382    0x0000    //TX_RATIODTL_CUT_TH
+383    0x0000    //TX_DT_CUT_K1
 384    0x0640    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0640    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0640    //TX_OUT_ENER_S_TH_NOISY
@@ -398,15 +399,15 @@
 388    0x07D0    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0000    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x0000    //TX_C_POST_FLT_MASK
+399    0x0000    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
@@ -521,16 +522,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -559,19 +560,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -904,6 +905,71 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x0000    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -1755,16 +1821,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0000    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0021    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0037    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BT_HAC-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0000    //TX_SAMPLINGFREQ_SIG
 7    0x0000    //TX_SAMPLINGFREQ_PROC
@@ -1781,8 +2699,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -1801,8 +2719,8 @@
 38    0x0002    //TX_MICS_OF_PAIR1
 39    0x0002    //TX_MICS_OF_PAIR2
 40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
 43    0x0001    //TX_MIC_DATA_SRC2
 44    0x0000    //TX_MIC_DATA_SRC3
 45    0x0000    //TX_MIC_PAIR_CH_04
@@ -1910,7 +2828,7 @@
 147    0x0100    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7500    //TX_EAD_THR
+150    0x7A00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
 153    0x0200    //TX_MIN_EQ_RE_EST_1
@@ -1925,13 +2843,13 @@
 162    0x4000    //TX_MIN_EQ_RE_EST_10
 163    0x6000    //TX_MIN_EQ_RE_EST_11
 164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x2000    //TX_LAMBDA_RE_EST
+165    0x4000    //TX_LAMBDA_RE_EST
 166    0x0000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x2000    //TX_GAIN_NP
 169    0x0180    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0200    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -1957,9 +2875,9 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
+197    0x7148    //TX_DTD_THR1_0
+198    0x7148    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
@@ -1988,7 +2906,7 @@
 225    0x1770    //TX_RATIO_DT_L_TH_HIGH
 226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
 227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
+228    0x2000    //TX_B_POST_FILT_ECHO_L
 229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
@@ -2011,12 +2929,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0050    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -2042,29 +2960,29 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0012    //TX_NS_LVL_CTRL_1
-283    0x0017    //TX_NS_LVL_CTRL_2
-284    0x0015    //TX_NS_LVL_CTRL_3
+282    0x0017    //TX_NS_LVL_CTRL_1
+283    0x0015    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
 285    0x0012    //TX_NS_LVL_CTRL_4
-286    0x0012    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0012    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
-290    0x000F    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000F    //TX_MIN_GAIN_S_2
 292    0x000F    //TX_MIN_GAIN_S_3
 293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000F    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x000F    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
 297    0x4000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x1000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x2400    //TX_SNRI_SUP_4
+301    0x1000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x2400    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
 306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
@@ -2075,19 +2993,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x2000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x1000    //TX_A_POST_FILT_S_4
-319    0x3000    //TX_A_POST_FILT_S_5
+315    0x2000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x1000    //TX_A_POST_FILT_S_3
+318    0x3000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
 320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
 324    0x1000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x3000    //TX_B_POST_FILT_5
+325    0x5000    //TX_B_POST_FILT_3
+326    0x3000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -2100,12 +3018,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7E00    //TX_LAMBDA_PFILT
 339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7900    //TX_LAMBDA_PFILT_S_1
-341    0x7400    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7000    //TX_LAMBDA_PFILT_S_4
+340    0x7400    //TX_LAMBDA_PFILT_S_1
+341    0x7900    //TX_LAMBDA_PFILT_S_2
+342    0x7000    //TX_LAMBDA_PFILT_S_3
+343    0x7D00    //TX_LAMBDA_PFILT_S_4
 344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
+345    0x7900    //TX_LAMBDA_PFILT_S_6
 346    0x7D00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0800    //TX_A_PEPPER
@@ -2118,7 +3036,7 @@
 355    0x0800    //TX_DT_BINVAD_TH_2
 356    0x0800    //TX_DT_BINVAD_TH_3
 357    0x0FA0    //TX_DT_BINVAD_ENDF
-358    0x0400    //TX_C_POST_FLT_DT
+358    0x0200    //TX_C_POST_FLT_DT
 359    0x4000    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0100    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
@@ -2140,10 +3058,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0FA0    //TX_NOISE_TH_6
 379    0x000A    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -2151,17 +3069,17 @@
 388    0x1000    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7000    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -2269,21 +3187,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -2312,31 +3230,31 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
-567    0x5858    //TX_FDEQ_GAIN_0
-568    0x5850    //TX_FDEQ_GAIN_1
-569    0x5050    //TX_FDEQ_GAIN_2
-570    0x5048    //TX_FDEQ_GAIN_3
-571    0x3C48    //TX_FDEQ_GAIN_4
-572    0x3C48    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4842    //TX_FDEQ_GAIN_7
-575    0x3030    //TX_FDEQ_GAIN_8
-576    0x3030    //TX_FDEQ_GAIN_9
+567    0x5250    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4A43    //TX_FDEQ_GAIN_3
+571    0x374B    //TX_FDEQ_GAIN_4
+572    0x3444    //TX_FDEQ_GAIN_5
+573    0x433C    //TX_FDEQ_GAIN_6
+574    0x3A37    //TX_FDEQ_GAIN_7
+575    0x2A2A    //TX_FDEQ_GAIN_8
+576    0x2C2C    //TX_FDEQ_GAIN_9
 577    0x4848    //TX_FDEQ_GAIN_10
 578    0x4848    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
@@ -2360,7 +3278,7 @@
 597    0x0708    //TX_FDEQ_BIN_6
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
-600    0x0D08    //TX_FDEQ_BIN_9
+600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x0000    //TX_FDEQ_BIN_10
 602    0x0000    //TX_FDEQ_BIN_11
 603    0x0000    //TX_FDEQ_BIN_12
@@ -2384,9 +3302,9 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4B4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
 627    0x4848    //TX_PREEQ_GAIN_MIC0_10
 628    0x4848    //TX_PREEQ_GAIN_MIC0_11
 629    0x4848    //TX_PREEQ_GAIN_MIC0_12
@@ -2410,7 +3328,7 @@
 647    0x0708    //TX_PREEQ_BIN_MIC0_6
 648    0x090A    //TX_PREEQ_BIN_MIC0_7
 649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D08    //TX_PREEQ_BIN_MIC0_9
+650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0000    //TX_PREEQ_BIN_MIC0_10
 652    0x0000    //TX_PREEQ_BIN_MIC0_11
 653    0x0000    //TX_PREEQ_BIN_MIC0_12
@@ -2433,9 +3351,9 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+673    0x4A4A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4B4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4D4E    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
 678    0x4848    //TX_PREEQ_GAIN_MIC1_12
@@ -2450,16 +3368,16 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C08    //TX_PREEQ_BIN_MIC1_2
-693    0x0700    //TX_PREEQ_BIN_MIC1_3
-694    0x0000    //TX_PREEQ_BIN_MIC1_4
-695    0x0000    //TX_PREEQ_BIN_MIC1_5
-696    0x0000    //TX_PREEQ_BIN_MIC1_6
-697    0x0000    //TX_PREEQ_BIN_MIC1_7
-698    0x0000    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
 700    0x0000    //TX_PREEQ_BIN_MIC1_10
 701    0x0000    //TX_PREEQ_BIN_MIC1_11
 702    0x0000    //TX_PREEQ_BIN_MIC1_12
@@ -2481,10 +3399,10 @@
 718    0x4848    //TX_PREEQ_GAIN_MIC2_3
 719    0x4848    //TX_PREEQ_GAIN_MIC2_4
 720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+721    0x484A    //TX_PREEQ_GAIN_MIC2_6
+722    0x4B4B    //TX_PREEQ_GAIN_MIC2_7
+723    0x4B4C    //TX_PREEQ_GAIN_MIC2_8
+724    0x4D50    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
 727    0x4848    //TX_PREEQ_GAIN_MIC2_12
@@ -2499,16 +3417,16 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x7800    //TX_PREEQ_BIN_MIC2_0
-740    0x0000    //TX_PREEQ_BIN_MIC2_1
-741    0x0000    //TX_PREEQ_BIN_MIC2_2
-742    0x0000    //TX_PREEQ_BIN_MIC2_3
-743    0x0000    //TX_PREEQ_BIN_MIC2_4
-744    0x0000    //TX_PREEQ_BIN_MIC2_5
-745    0x0000    //TX_PREEQ_BIN_MIC2_6
-746    0x0000    //TX_PREEQ_BIN_MIC2_7
-747    0x0000    //TX_PREEQ_BIN_MIC2_8
-748    0x0000    //TX_PREEQ_BIN_MIC2_9
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0708    //TX_PREEQ_BIN_MIC2_6
+746    0x090A    //TX_PREEQ_BIN_MIC2_7
+747    0x0B0C    //TX_PREEQ_BIN_MIC2_8
+748    0x0D0E    //TX_PREEQ_BIN_MIC2_9
 749    0x0000    //TX_PREEQ_BIN_MIC2_10
 750    0x0000    //TX_PREEQ_BIN_MIC2_11
 751    0x0000    //TX_PREEQ_BIN_MIC2_12
@@ -2533,7 +3451,7 @@
 770    0x0044    //TX_MIC_PWR_BIAS_1
 771    0x0044    //TX_MIC_PWR_BIAS_2
 772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
+773    0x0000    //TX_GAIN_LIMIT_0
 774    0x000F    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
 776    0x000F    //TX_GAIN_LIMIT_3
@@ -2626,7 +3544,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0DCE    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -2651,14 +3569,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x0050    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x000C    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7918    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xE0C0    //TX_AMS_RESRV_02
+945    0x1770    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -3508,16 +4491,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BT_HAC-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0001    //TX_SAMPLINGFREQ_SIG
 7    0x0001    //TX_SAMPLINGFREQ_PROC
@@ -3534,8 +5369,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -3554,8 +5389,8 @@
 38    0x0002    //TX_MICS_OF_PAIR1
 39    0x0002    //TX_MICS_OF_PAIR2
 40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
 43    0x0001    //TX_MIC_DATA_SRC2
 44    0x0000    //TX_MIC_DATA_SRC3
 45    0x0000    //TX_MIC_PAIR_CH_04
@@ -3663,7 +5498,7 @@
 147    0x0300    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6800    //TX_EAD_THR
+150    0x6C00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
 153    0x0100    //TX_MIN_EQ_RE_EST_1
@@ -3682,9 +5517,9 @@
 166    0x4000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x5000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
+169    0x02A0    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x01B0    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -3710,9 +5545,9 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
+197    0x7148    //TX_DTD_THR1_0
+198    0x7148    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
@@ -3727,7 +5562,7 @@
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
 213    0x07D0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
+214    0x0020    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -3736,18 +5571,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
 224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
+225    0x01CC    //TX_RATIO_DT_L_TH_HIGH
+226    0x4A38    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x7FFF    //TX_B_POST_FILT_ECHO_L
 229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+234    0x015E    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -3764,11 +5599,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -3796,11 +5631,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -3818,8 +5653,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -3828,19 +5663,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -3848,14 +5683,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -3869,9 +5704,9 @@
 353    0x0200    //TX_DT_BINVAD_TH_0
 354    0x0200    //TX_DT_BINVAD_TH_1
 355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x0200    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0800    //TX_C_POST_FLT_DT
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1388    //TX_DT_BINVAD_ENDF
+358    0x2000    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0140    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
@@ -3893,10 +5728,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0F0A    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -3904,17 +5739,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7FFF    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0005    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -4022,21 +5857,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -4065,33 +5900,33 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x001C    //TX_FDEQ_SUBNUM
-567    0x5050    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x5050    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x5048    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4A4F    //TX_FDEQ_GAIN_2
+570    0x4E48    //TX_FDEQ_GAIN_3
+571    0x4444    //TX_FDEQ_GAIN_4
+572    0x444B    //TX_FDEQ_GAIN_5
+573    0x4E50    //TX_FDEQ_GAIN_6
+574    0x544D    //TX_FDEQ_GAIN_7
+575    0x464C    //TX_FDEQ_GAIN_8
 576    0x4844    //TX_FDEQ_GAIN_9
-577    0x3C36    //TX_FDEQ_GAIN_10
-578    0x3A3A    //TX_FDEQ_GAIN_11
+577    0x393C    //TX_FDEQ_GAIN_10
+578    0x3C3C    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
 580    0x4848    //TX_FDEQ_GAIN_13
 581    0x4848    //TX_FDEQ_GAIN_14
@@ -4114,10 +5949,10 @@
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
 600    0x0D0E    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x1011    //TX_FDEQ_BIN_12
-604    0x1104    //TX_FDEQ_BIN_13
+601    0x0F10    //TX_FDEQ_BIN_10
+602    0x1011    //TX_FDEQ_BIN_11
+603    0x1112    //TX_FDEQ_BIN_12
+604    0x120B    //TX_FDEQ_BIN_13
 605    0x0000    //TX_FDEQ_BIN_14
 606    0x0000    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
@@ -4137,13 +5972,13 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x5E64    //TX_PREEQ_GAIN_MIC0_12
-630    0x6464    //TX_PREEQ_GAIN_MIC0_13
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
 631    0x4848    //TX_PREEQ_GAIN_MIC0_14
 632    0x4848    //TX_PREEQ_GAIN_MIC0_15
 633    0x4848    //TX_PREEQ_GAIN_MIC0_16
@@ -4166,8 +6001,8 @@
 650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0F10    //TX_PREEQ_BIN_MIC0_10
 652    0x1011    //TX_PREEQ_BIN_MIC0_11
-653    0x1104    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
+653    0x1112    //TX_PREEQ_BIN_MIC0_12
+654    0x120B    //TX_PREEQ_BIN_MIC0_13
 655    0x0000    //TX_PREEQ_BIN_MIC0_14
 656    0x0000    //TX_PREEQ_BIN_MIC0_15
 657    0x0000    //TX_PREEQ_BIN_MIC0_16
@@ -4186,13 +6021,13 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+673    0x484A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4C4E    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5454    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
 680    0x4848    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
@@ -4203,20 +6038,20 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x0700    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0F10    //TX_PREEQ_BIN_MIC1_10
+701    0x1011    //TX_PREEQ_BIN_MIC1_11
+702    0x1112    //TX_PREEQ_BIN_MIC1_12
+703    0x120B    //TX_PREEQ_BIN_MIC1_13
 704    0x0000    //TX_PREEQ_BIN_MIC1_14
 705    0x0000    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
@@ -4231,19 +6066,19 @@
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+718    0x484A    //TX_PREEQ_GAIN_MIC2_3
+719    0x4B4A    //TX_PREEQ_GAIN_MIC2_4
+720    0x4B4C    //TX_PREEQ_GAIN_MIC2_5
+721    0x4C4D    //TX_PREEQ_GAIN_MIC2_6
+722    0x4F50    //TX_PREEQ_GAIN_MIC2_7
+723    0x5050    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5252    //TX_PREEQ_GAIN_MIC2_10
+726    0x5253    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x5454    //TX_PREEQ_GAIN_MIC2_13
+729    0x5455    //TX_PREEQ_GAIN_MIC2_14
+730    0x5555    //TX_PREEQ_GAIN_MIC2_15
 731    0x4848    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
@@ -4267,7 +6102,7 @@
 751    0x0808    //TX_PREEQ_BIN_MIC2_12
 752    0x0808    //TX_PREEQ_BIN_MIC2_13
 753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
+754    0x0808    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
@@ -4286,8 +6121,8 @@
 770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0009    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
 776    0x000F    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
@@ -4379,7 +6214,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x10CA    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -4404,14 +6239,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x03C0    //TX_MICMUTE_RATIO_THR
+900    0x0122    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x6590    //TX_DTD_THR1_MICMUTE_0
+912    0x7FFF    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xE4A8    //TX_AMS_RESRV_02
+945    0x1770    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -5261,16 +7161,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BT_HAC-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
 7    0x0003    //TX_SAMPLINGFREQ_PROC
@@ -5287,8 +8039,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -5307,8 +8059,8 @@
 38    0x0002    //TX_MICS_OF_PAIR1
 39    0x0002    //TX_MICS_OF_PAIR2
 40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
 43    0x0001    //TX_MIC_DATA_SRC2
 44    0x0000    //TX_MIC_DATA_SRC3
 45    0x0000    //TX_MIC_PAIR_CH_04
@@ -5431,13 +8183,13 @@
 162    0x7800    //TX_MIN_EQ_RE_EST_10
 163    0x7800    //TX_MIN_EQ_RE_EST_11
 164    0x7800    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
+165    0x3000    //TX_LAMBDA_RE_EST
 166    0x3000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x4000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
+169    0x0260    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -5463,7 +8215,7 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
+197    0x7B0C    //TX_DTD_THR1_0
 198    0x7FF0    //TX_DTD_THR1_1
 199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
@@ -5489,18 +8241,18 @@
 220    0x7FFF    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
 224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1F40    //TX_RATIO_DT_L_TH_HIGH
-226    0x6590    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
-229    0x1000    //TX_B_POST_FILT_ECHO_H
+225    0x01F4    //TX_RATIO_DT_L_TH_HIGH
+226    0x59D8    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x7FFF    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x2328    //TX_RATIO_DT_L0_TH_HIGH
+234    0x00C8    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -5519,10 +8271,10 @@
 250    0x0100    //TX_DELTA_THR_SN_EST_0
 251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
-254    0x0000    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+253    0x0000    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -5548,52 +8300,52 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x003C    //TX_NS_LVL_CTRL_1
-283    0x003C    //TX_NS_LVL_CTRL_2
-284    0x0024    //TX_NS_LVL_CTRL_3
-285    0x003C    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+282    0x001A    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
 297    0x6000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x1400    //TX_SNRI_SUP_1
-302    0x1400    //TX_SNRI_SUP_2
-303    0x1400    //TX_SNRI_SUP_3
+301    0x4000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
 310    0x09C4    //TX_GAIN0_NTH
 311    0x000A    //TX_MUSIC_MORENS
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x7C00    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x6000    //TX_B_POST_FILT_1
 324    0x6000    //TX_B_POST_FILT_2
 325    0x6000    //TX_B_POST_FILT_3
-326    0x6000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -5601,19 +8353,19 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7D00    //TX_LAMBDA_PFILT_S_1
-341    0x7D00    //TX_LAMBDA_PFILT_S_2
-342    0x7D00    //TX_LAMBDA_PFILT_S_3
-343    0x7D00    //TX_LAMBDA_PFILT_S_4
-344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
-346    0x7D00    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x3E80    //TX_K_PEPPER
 348    0x0400    //TX_A_PEPPER
 349    0x1EAA    //TX_K_PEPPER_HF
 350    0x0600    //TX_A_PEPPER_HF
@@ -5622,7 +8374,7 @@
 353    0x0040    //TX_DT_BINVAD_TH_0
 354    0x0040    //TX_DT_BINVAD_TH_1
 355    0x0100    //TX_DT_BINVAD_TH_2
-356    0x0100    //TX_DT_BINVAD_TH_3
+356    0x2000    //TX_DT_BINVAD_TH_3
 357    0x36B0    //TX_DT_BINVAD_ENDF
 358    0x0200    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
@@ -5646,10 +8398,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0DAC    //TX_NOISE_TH_6
 379    0x0050    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -5657,17 +8409,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0005    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -5775,21 +8527,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -5818,37 +8570,37 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
 568    0x4848    //TX_FDEQ_GAIN_1
 569    0x4850    //TX_FDEQ_GAIN_2
 570    0x5050    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x484A    //TX_FDEQ_GAIN_5
-573    0x4E5E    //TX_FDEQ_GAIN_6
-574    0x5C4C    //TX_FDEQ_GAIN_7
+571    0x4B48    //TX_FDEQ_GAIN_4
+572    0x484E    //TX_FDEQ_GAIN_5
+573    0x4E5C    //TX_FDEQ_GAIN_6
+574    0x564E    //TX_FDEQ_GAIN_7
 575    0x4C4E    //TX_FDEQ_GAIN_8
-576    0x4844    //TX_FDEQ_GAIN_9
-577    0x4448    //TX_FDEQ_GAIN_10
-578    0x4850    //TX_FDEQ_GAIN_11
-579    0x5C6A    //TX_FDEQ_GAIN_12
-580    0x5A84    //TX_FDEQ_GAIN_13
-581    0x7880    //TX_FDEQ_GAIN_14
-582    0x7F7F    //TX_FDEQ_GAIN_15
+576    0x4E45    //TX_FDEQ_GAIN_9
+577    0x494A    //TX_FDEQ_GAIN_10
+578    0x534D    //TX_FDEQ_GAIN_11
+579    0x5C54    //TX_FDEQ_GAIN_12
+580    0x5466    //TX_FDEQ_GAIN_13
+581    0x5C70    //TX_FDEQ_GAIN_14
+582    0x7C84    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
 584    0x4848    //TX_FDEQ_GAIN_17
 585    0x4848    //TX_FDEQ_GAIN_18
@@ -5882,7 +8634,7 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
@@ -5890,15 +8642,15 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x6474    //TX_PREEQ_GAIN_MIC0_12
-630    0x7870    //TX_PREEQ_GAIN_MIC0_13
-631    0x5C48    //TX_PREEQ_GAIN_MIC0_14
-632    0x383C    //TX_PREEQ_GAIN_MIC0_15
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
 633    0x4848    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
@@ -5913,17 +8665,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x090A    //TX_PREEQ_BIN_MIC0_7
-649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1719    //TX_PREEQ_BIN_MIC0_11
-653    0x1B1E    //TX_PREEQ_BIN_MIC0_12
-654    0x1E1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x401E    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -5931,7 +8683,7 @@
 662    0x0000    //TX_PREEQ_BIN_MIC0_21
 663    0x0000    //TX_PREEQ_BIN_MIC0_22
 664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
 666    0x4848    //TX_PREEQ_GAIN_MIC1_0
 667    0x4848    //TX_PREEQ_GAIN_MIC1_1
 668    0x4848    //TX_PREEQ_GAIN_MIC1_2
@@ -5939,16 +8691,16 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+673    0x4849    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4A    //TX_PREEQ_GAIN_MIC1_8
+675    0x4B4D    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5354    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
+680    0x5653    //TX_PREEQ_GAIN_MIC1_14
+681    0x4C48    //TX_PREEQ_GAIN_MIC1_15
+682    0x4444    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
 684    0x4848    //TX_PREEQ_GAIN_MIC1_18
 685    0x4848    //TX_PREEQ_GAIN_MIC1_19
@@ -5956,23 +8708,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x070F    //TX_PREEQ_BIN_MIC1_8
-699    0x1F08    //TX_PREEQ_BIN_MIC1_9
-700    0x0808    //TX_PREEQ_BIN_MIC1_10
-701    0x0920    //TX_PREEQ_BIN_MIC1_11
-702    0x2020    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x401E    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -5987,16 +8739,16 @@
 718    0x4848    //TX_PREEQ_GAIN_MIC2_3
 719    0x4848    //TX_PREEQ_GAIN_MIC2_4
 720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+721    0x494B    //TX_PREEQ_GAIN_MIC2_6
+722    0x4C4D    //TX_PREEQ_GAIN_MIC2_7
+723    0x4E4F    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5255    //TX_PREEQ_GAIN_MIC2_10
+726    0x5754    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x544F    //TX_PREEQ_GAIN_MIC2_13
+729    0x463D    //TX_PREEQ_GAIN_MIC2_14
+730    0x4A48    //TX_PREEQ_GAIN_MIC2_15
 731    0x4848    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
@@ -6005,22 +8757,22 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
+739    0x0203    //TX_PREEQ_BIN_MIC2_0
+740    0x0303    //TX_PREEQ_BIN_MIC2_1
+741    0x0304    //TX_PREEQ_BIN_MIC2_2
+742    0x0405    //TX_PREEQ_BIN_MIC2_3
+743    0x0506    //TX_PREEQ_BIN_MIC2_4
 744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0xF200    //TX_PREEQ_BIN_MIC2_15
+745    0x0809    //TX_PREEQ_BIN_MIC2_6
+746    0x0A0A    //TX_PREEQ_BIN_MIC2_7
+747    0x0C10    //TX_PREEQ_BIN_MIC2_8
+748    0x1013    //TX_PREEQ_BIN_MIC2_9
+749    0x1414    //TX_PREEQ_BIN_MIC2_10
+750    0x261E    //TX_PREEQ_BIN_MIC2_11
+751    0x1E14    //TX_PREEQ_BIN_MIC2_12
+752    0x1414    //TX_PREEQ_BIN_MIC2_13
+753    0x2814    //TX_PREEQ_BIN_MIC2_14
+754    0x4022    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
@@ -6036,12 +8788,12 @@
 767    0x0050    //TX_MIC_CALIBRATION_2
 768    0x0050    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
+770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
 774    0x000F    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
+775    0x000F    //TX_GAIN_LIMIT_2
 776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
@@ -6120,8 +8872,8 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0002    //TX_TDDRC_THRD_1
+854    0x0003    //TX_TDDRC_THRD_0
+855    0x0004    //TX_TDDRC_THRD_1
 856    0x1000    //TX_TDDRC_THRD_2
 857    0x1000    //TX_TDDRC_THRD_3
 858    0x6000    //TX_TDDRC_SLANT_0
@@ -6132,7 +8884,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0E21    //TX_TDDRC_DRC_GAIN
+866    0x1380    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -6163,8 +8915,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x01C2    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7918    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x3A98    //TX_DTD_THR1_MICMUTE_2
+914    0x32C8    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xE4A8    //TX_AMS_RESRV_02
+945    0x1770    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0xA064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -7014,10 +9831,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BT_HAC-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -7270,11 +10939,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -7302,11 +10971,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -7324,8 +10993,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -7334,19 +11003,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -7354,14 +11023,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -7399,10 +11068,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x2710    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -7410,15 +11079,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -7533,16 +11202,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -7571,19 +11240,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -7916,6 +11585,71 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x0064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -8767,10 +12501,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -9023,20 +13609,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -9054,16 +13640,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -9087,12 +13673,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -9152,10 +13738,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -9163,15 +13749,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -9286,16 +13872,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -9324,19 +13910,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -9669,8 +14255,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -9692,7 +14343,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -9838,8 +14489,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -9937,8 +14588,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10036,8 +14687,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10135,8 +14786,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10234,8 +14885,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10333,8 +14984,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10432,8 +15083,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -10520,10 +15171,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -10776,20 +16279,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -10807,16 +16310,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -10840,12 +16343,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -10905,10 +16408,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -10916,15 +16419,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -11039,16 +16542,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -11077,19 +16580,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -11422,8 +16925,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -11445,7 +17013,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -11591,8 +17159,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -11690,8 +17258,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -11789,8 +17357,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -11888,8 +17456,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -11987,8 +17555,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -12086,8 +17654,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -12185,8 +17753,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -12273,10 +17841,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -12529,20 +18949,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -12560,16 +18980,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -12593,12 +19013,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -12658,10 +19078,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -12669,15 +19089,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -12792,16 +19212,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -12830,19 +19250,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -13175,8 +19595,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0xA064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -14026,10 +20511,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -14282,10 +21619,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -14313,31 +21650,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
+282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x7000    //TX_SNRI_SUP_1
 302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -14354,8 +21691,8 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
@@ -14411,10 +21748,10 @@
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x02BC    //TX_NOISE_TH_6
 379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -14422,15 +21759,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -14545,16 +21882,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -14583,19 +21920,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -14928,8 +22265,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0x2064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -15779,10 +23181,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB_NREC-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -16035,20 +24289,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -16066,16 +24320,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -16099,12 +24353,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -16164,10 +24418,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -16175,15 +24429,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -16298,16 +24552,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -16336,19 +24590,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -16681,8 +24935,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -16704,7 +25023,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -16850,8 +25169,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -16949,8 +25268,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17048,8 +25367,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17147,8 +25466,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17246,8 +25565,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17345,8 +25664,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17444,8 +25763,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -17532,10 +25851,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB_NREC-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -17788,20 +26959,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -17819,16 +26990,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -17852,12 +27023,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -17917,10 +27088,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -17928,15 +27099,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -18051,16 +27222,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -18089,19 +27260,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -18434,8 +27605,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -18457,7 +27693,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -18603,8 +27839,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -18702,8 +27938,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -18801,8 +28037,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -18900,8 +28136,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -18999,8 +28235,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -19098,8 +28334,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -19197,8 +28433,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -19285,10 +28521,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB_NREC-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -19541,20 +29629,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -19572,16 +29660,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -19605,12 +29693,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -19670,10 +29758,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -19681,15 +29769,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -19804,16 +29892,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -19842,19 +29930,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -20187,8 +30275,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0xA064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -21038,10 +31191,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTNB_NREC-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -21294,10 +32299,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -21325,31 +32330,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
+282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x7000    //TX_SNRI_SUP_1
 302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -21366,8 +32371,8 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
@@ -21423,10 +32428,10 @@
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x02BC    //TX_NOISE_TH_6
 379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -21434,15 +32439,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -21557,16 +32562,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -21595,19 +32600,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -21940,8 +32945,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0x2064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -22791,10 +33861,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -23047,20 +34969,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -23078,16 +35000,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -23111,12 +35033,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -23176,10 +35098,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -23187,15 +35109,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -23310,16 +35232,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -23348,19 +35270,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -23693,8 +35615,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -23716,7 +35703,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -23862,8 +35849,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -23961,8 +35948,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24060,8 +36047,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24159,8 +36146,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24258,8 +36245,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24357,8 +36344,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24456,8 +36443,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -24544,10 +36531,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -24800,20 +37639,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -24831,16 +37670,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -24864,12 +37703,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -24929,10 +37768,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -24940,15 +37779,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -25063,16 +37902,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -25101,19 +37940,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -25446,8 +38285,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -25469,7 +38373,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -25615,8 +38519,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -25714,8 +38618,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -25813,8 +38717,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -25912,8 +38816,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -26011,8 +38915,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -26110,8 +39014,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -26209,8 +39113,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -26297,10 +39201,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -26553,20 +40309,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -26584,16 +40340,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -26617,12 +40373,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -26682,10 +40438,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -26693,15 +40449,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -26816,16 +40572,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -26854,19 +40610,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -27199,8 +40955,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0xA064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -28050,10 +41871,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -28306,10 +42979,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -28337,31 +43010,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
+282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x7000    //TX_SNRI_SUP_1
 302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -28378,8 +43051,8 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
@@ -28435,10 +43108,10 @@
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x02BC    //TX_NOISE_TH_6
 379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -28446,15 +43119,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -28569,16 +43242,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -28607,19 +43280,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -28952,8 +43625,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0x2064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -29803,10 +44541,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB_NREC-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -30059,20 +45649,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -30090,16 +45680,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -30123,12 +45713,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -30188,10 +45778,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -30199,15 +45789,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -30322,16 +45912,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -30360,19 +45950,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -30705,8 +46295,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -30728,7 +46383,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -30874,8 +46529,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -30973,8 +46628,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31072,8 +46727,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31171,8 +46826,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31270,8 +46925,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31369,8 +47024,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31468,8 +47123,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7FFF    //RX_TDDRC_SLANT_0
@@ -31556,10 +47211,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x017F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4444    //RX_FDEQ_GAIN_6
+203    0x4040    //RX_FDEQ_GAIN_7
+204    0x4040    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB_NREC-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0008    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -31812,20 +48319,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -31843,16 +48350,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -31876,12 +48383,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -31941,10 +48448,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -31952,15 +48459,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -32075,16 +48582,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -32113,19 +48620,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -32458,8 +48965,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0xA06C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -32481,7 +49053,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -32627,8 +49199,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -32726,8 +49298,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -32825,8 +49397,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -32924,8 +49496,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -33023,8 +49595,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -33122,8 +49694,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -33221,8 +49793,8 @@
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0001    //RX_TDDRC_THRD_1
 114    0x7FFF    //RX_TDDRC_THRD_2
 115    0x7FFF    //RX_TDDRC_THRD_3
 116    0x7E70    //RX_TDDRC_SLANT_0
@@ -33309,10 +49881,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA06C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0001    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7E70    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x3C3C    //RX_FDEQ_GAIN_9
+206    0x3C3C    //RX_FDEQ_GAIN_10
+207    0x3838    //RX_FDEQ_GAIN_11
+208    0x3838    //RX_FDEQ_GAIN_12
+209    0x3030    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1112    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB_NREC-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -33565,20 +50989,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -33596,16 +51020,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -33629,12 +51053,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -33694,10 +51118,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -33705,15 +51129,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -33828,16 +51252,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -33866,19 +51290,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -34211,8 +51635,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0xA064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -35062,10 +52551,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  BLUETOOTH-BTWB_NREC-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -35318,10 +53659,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -35349,31 +53690,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
+282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x7000    //TX_SNRI_SUP_1
 302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -35390,8 +53731,8 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
@@ -35447,10 +53788,10 @@
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x02BC    //TX_NOISE_TH_6
 379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -35458,15 +53799,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -35581,16 +53922,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -35619,19 +53960,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -35964,8 +54305,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0064    //RX_RECVFUNC_MODE_0
+0    0x2064    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -36815,4 +55221,14205 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  BLUETOOTH-BT_HAC-RESERVE2-SWB
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7600    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x3000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7B0C    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7FF0    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x36B0    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x01F4    //TX_RATIO_DT_L_TH_HIGH
+226    0x59D8    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x7FFF    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x00C8    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0000    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x001A    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x3E80    //TX_K_PEPPER
+348    0x0400    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0040    //TX_DT_BINVAD_TH_1
+355    0x0100    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x2CEC    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0005    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4850    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4B48    //TX_FDEQ_GAIN_4
+572    0x484E    //TX_FDEQ_GAIN_5
+573    0x4E5C    //TX_FDEQ_GAIN_6
+574    0x564E    //TX_FDEQ_GAIN_7
+575    0x4C4E    //TX_FDEQ_GAIN_8
+576    0x4E45    //TX_FDEQ_GAIN_9
+577    0x494A    //TX_FDEQ_GAIN_10
+578    0x534D    //TX_FDEQ_GAIN_11
+579    0x5C54    //TX_FDEQ_GAIN_12
+580    0x5466    //TX_FDEQ_GAIN_13
+581    0x5C70    //TX_FDEQ_GAIN_14
+582    0x7C84    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x401E    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4849    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4A    //TX_PREEQ_GAIN_MIC1_8
+675    0x4B4D    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5354    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
+680    0x5653    //TX_PREEQ_GAIN_MIC1_14
+681    0x4C48    //TX_PREEQ_GAIN_MIC1_15
+682    0x4444    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x401E    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x494B    //TX_PREEQ_GAIN_MIC2_6
+722    0x4C4D    //TX_PREEQ_GAIN_MIC2_7
+723    0x4E4F    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5255    //TX_PREEQ_GAIN_MIC2_10
+726    0x5754    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x544F    //TX_PREEQ_GAIN_MIC2_13
+729    0x463D    //TX_PREEQ_GAIN_MIC2_14
+730    0x4A48    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0203    //TX_PREEQ_BIN_MIC2_0
+740    0x0303    //TX_PREEQ_BIN_MIC2_1
+741    0x0304    //TX_PREEQ_BIN_MIC2_2
+742    0x0405    //TX_PREEQ_BIN_MIC2_3
+743    0x0506    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0809    //TX_PREEQ_BIN_MIC2_6
+746    0x0A0A    //TX_PREEQ_BIN_MIC2_7
+747    0x0C10    //TX_PREEQ_BIN_MIC2_8
+748    0x1013    //TX_PREEQ_BIN_MIC2_9
+749    0x1414    //TX_PREEQ_BIN_MIC2_10
+750    0x261E    //TX_PREEQ_BIN_MIC2_11
+751    0x1E14    //TX_PREEQ_BIN_MIC2_12
+752    0x1414    //TX_PREEQ_BIN_MIC2_13
+753    0x2814    //TX_PREEQ_BIN_MIC2_14
+754    0x4022    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0050    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0050    //TX_MIC_CALIBRATION_2
+768    0x0050    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0800    //TX_TDDRC_ALPHA_UP_01
+784    0x0800    //TX_TDDRC_ALPHA_UP_02
+785    0x0800    //TX_TDDRC_ALPHA_UP_03
+786    0x0800    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0010    //TX_DEADMIC_SILENCE_TH
+817    0x0600    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0003    //TX_TDDRC_THRD_0
+855    0x0004    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1000    //TX_TDDRC_THRD_3
+858    0x6000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x0800    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x1380    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x01C2    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7918    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x3A98    //TX_DTD_THR1_MICMUTE_2
+914    0x32C8    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xE4A8    //TX_AMS_RESRV_02
+945    0x1770    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA064    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0000    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  BLUETOOTH-BTNB-RESERVE2-SWB
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x0200    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0915    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF400    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0000    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0970    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA064    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0000    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  BLUETOOTH-BTNB_NREC-RESERVE2-SWB
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2A28    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0915    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF400    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0970    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA064    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0000    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  BLUETOOTH-BTWB-RESERVE2-SWB
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x0200    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0915    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF400    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0000    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0970    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA064    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0000    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  BLUETOOTH-BTWB_NREC-RESERVE2-SWB
+#PARAM_MODE  Full
+#PARAM_TYPE  TX+2RX
+#TOTAL_CUSTOM_STEP  7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2A28    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0915    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF400    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0x4000    //TX_MORENS_TFMASK_TH
+381    0xFFEE    //TX_DRC_QUIET_FLOOR
+382    0x6000    //TX_RATIODTL_CUT_TH
+383    0xFFF3    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x0000    //TX_POST_MASK_SUP_HSNE
+392    0x0000    //TX_TAIL_DET_TH
+393    0x0000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0800    //TX_SUPHIGH_TH
+396    0x00C8    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x0800    //TX_C_POST_FLT_MASK
+399    0x0005    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x0000    //TX_DEREVERB_LF_MU
+515    0x0000    //TX_DEREVERB_HF_MU
+516    0x0000    //TX_DEREVERB_DELAY
+517    0x0000    //TX_DEREVERB_COEF_LEN
+518    0x0000    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x0000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0970    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x0000    //TX_SENDFUNC_REG_MICMUTE
+898    0x0000    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0000    //TX_MICMUTE_RATIO_THR
+900    0x0000    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x0000    //TX_MICMUTE_LOG_EYR_TH
+903    0x0000    //TX_MICMUTE_CVG_TIME
+904    0x0000    //TX_MICMUTE_RELEASE_TIME
+905    0x0000    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0000    //TX_MICMUTE_FRQ_AEC_L
+908    0x0000    //TX_MICMUTE_EAD_THR
+909    0x0000    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x0000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x0000    //TX_DTD_THR1_MICMUTE_0
+912    0x0000    //TX_DTD_THR1_MICMUTE_1
+913    0x0000    //TX_DTD_THR1_MICMUTE_2
+914    0x0000    //TX_DTD_THR1_MICMUTE_3
+915    0x0000    //TX_DTD_THR2_MICMUTE_0
+916    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x0000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x0000    //TX_MICMUTE_C_POST_FLT
+922    0x0000    //TX_MICMUTE_DT_CUT_K
+923    0x0000    //TX_MICMUTE_DT_CUT_THR
+924    0x0000    //TX_MICMUTE_DT_CUT_K2
+925    0x0000    //TX_MICMUTE_DT_CUT_THR2
+926    0x0000    //TX_MICMUTE_DT2_HOLD_N
+927    0x0000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x0000    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0000    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x0000    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0000    //TX_MICMUTE_DT_CUT_K1
+933    0x0000    //TX_MICMUTE_N2_SN_EST
+934    0x0000    //TX_MICMUTE_THR_SN_EST_0
+935    0x0000    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x0000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x0000    //TX_MICMUTE_B_POST_FILT_0
+938    0x0000    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x0000    //TX_MIC1MUTE_AMP_THR
+941    0x0000    //TX_MIC1MUTE_CVG_TIME
+942    0x0000    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA064    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0000    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x7FFF    //RX_TDDRC_THRD_2
+115    0x7FFF    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0155    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x8064    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0000    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x7FFF    //RX_TDDRC_THRD_2
+272    0x7FFF    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0155    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
diff --git a/audio/felix/tuning/fortemedia/HANDSET.dat b/audio/felix/tuning/fortemedia/HANDSET.dat
index 9f6bea4..0dae20b 100644
--- a/audio/felix/tuning/fortemedia/HANDSET.dat
+++ b/audio/felix/tuning/fortemedia/HANDSET.dat
Binary files differ
diff --git a/audio/felix/tuning/fortemedia/HANDSET.mods b/audio/felix/tuning/fortemedia/HANDSET.mods
index 308f409..0e7e722 100644
--- a/audio/felix/tuning/fortemedia/HANDSET.mods
+++ b/audio/felix/tuning/fortemedia/HANDSET.mods
@@ -1,16 +1,8027 @@
 #PLATFORM_NAME  gChip
 #EXPORT_FLAG  HANDSET
-#SINGLE_API_VER  1.1.6
-#SAVE_TIME  2021-10-21 12:03:00
+#SINGLE_API_VER  1.2.1
+#SAVE_TIME  2023-04-11 17:47:20
 
-#CASE_NAME  HANDSET-HANDSET-RESERVE1-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-NB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7646    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7C00    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7DC8    //TX_DTD_THR1_0
+198    0x7DC8    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7530    //TX_DTD_THR1_4
+202    0x7530    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x1000    //TX_DTD_THR2_0
+205    0x1000    //TX_DTD_THR2_1
+206    0x1000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FB0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFD00    //TX_THR_SN_EST_1
+244    0xFD00    //TX_THR_SN_EST_2
+245    0xFD00    //TX_THR_SN_EST_3
+246    0xF900    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x01A0    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0000    //TX_DELTA_THR_SN_EST_5
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x2000    //TX_LAMBDA_NN_EST_2
+261    0x3000    //TX_LAMBDA_NN_EST_3
+262    0x3000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x3000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x3000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x3000    //TX_MAINREFRTO_TH_H
+277    0x1000    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x4000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0017    //TX_NS_LVL_CTRL_2
+284    0x0017    //TX_NS_LVL_CTRL_3
+285    0x0019    //TX_NS_LVL_CTRL_4
+286    0x0014    //TX_NS_LVL_CTRL_5
+287    0x001B    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x0010    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x4000    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x3000    //TX_SNRI_SUP_7
+308    0x3000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x2000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x4000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x4000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7900    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7900    //TX_LAMBDA_PFILT_S_3
+343    0x7200    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x0C80    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0004    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x09C4    //TX_NOISE_TH_1
+371    0x022C    //TX_NOISE_TH_2
+372    0x4650    //TX_NOISE_TH_3
+373    0x7E2C    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x4650    //TX_NOISE_TH_6
+379    0x0004    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x1000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0003    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x000A    //TX_NS_ENOISE_MIC0_TH
+406    0x0004    //TX_MINENOISE_MIC0_TH
+407    0x0014    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1FFF    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x4000    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0100    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0666    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x6000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x001A    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0080    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0018    //TX_FDEQ_SUBNUM
+567    0x7064    //TX_FDEQ_GAIN_0
+568    0x5E54    //TX_FDEQ_GAIN_1
+569    0x5350    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4642    //TX_FDEQ_GAIN_4
+572    0x4034    //TX_FDEQ_GAIN_5
+573    0x3E4C    //TX_FDEQ_GAIN_6
+574    0x3636    //TX_FDEQ_GAIN_7
+575    0x3634    //TX_FDEQ_GAIN_8
+576    0x4448    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0502    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0404    //TX_FDEQ_BIN_4
+596    0x0409    //TX_FDEQ_BIN_5
+597    0x0507    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x0B0A    //TX_FDEQ_BIN_8
+600    0x1109    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C08    //TX_PREEQ_BIN_MIC0_2
+644    0x0700    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0065    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0065    //TX_MIC_CALIBRATION_2
+768    0x0065    //TX_MIC_CALIBRATION_3
+769    0x0044    //TX_MIC_PWR_BIAS_0
+770    0x0044    //TX_MIC_PWR_BIAS_1
+771    0x0044    //TX_MIC_PWR_BIAS_2
+772    0x0044    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0004    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x089C    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0208    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x000A    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x12E1    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7D00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x75F8    //TX_DTD_THR1_MICMUTE_0
+912    0x76C0    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x7FFF    //TX_MICMUTE_C_POST_FLT
+922    0x0FA0    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x0FA0    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0C00    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7148    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0000    //RX_SAMPLINGFREQ_SIG
+3    0x0000    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4840    //RX_FDEQ_GAIN_0
+40    0x3E40    //RX_FDEQ_GAIN_1
+41    0x515E    //RX_FDEQ_GAIN_2
+42    0x6470    //RX_FDEQ_GAIN_3
+43    0x7A84    //RX_FDEQ_GAIN_4
+44    0x7C7A    //RX_FDEQ_GAIN_5
+45    0x7C7C    //RX_FDEQ_GAIN_6
+46    0x7D7C    //RX_FDEQ_GAIN_7
+47    0x7E82    //RX_FDEQ_GAIN_8
+48    0x7C80    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0204    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x055F    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0F0A    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B49    //RX_MAX_G_FP
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01ED    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x655E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01F9    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01FF    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0023    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01FF    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01FF    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01FF    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0098    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x020B    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x566A    //RX_FDEQ_GAIN_1
+41    0x6A78    //RX_FDEQ_GAIN_2
+42    0x6E5E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0600    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0045    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-WB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0036    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0001    //TX_SAMPLINGFREQ_SIG
+7    0x0001    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x6000    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x0200    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7918    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFB00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x01A0    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x2000    //TX_MAINREFRTOH_TH_H
+275    0x1400    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0018    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x001A    //TX_NS_LVL_CTRL_4
+286    0x001E    //TX_NS_LVL_CTRL_5
+287    0x001C    //TX_NS_LVL_CTRL_6
+288    0x001C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x000A    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0012    //TX_MIN_GAIN_S_3
+293    0x0018    //TX_MIN_GAIN_S_4
+294    0x0018    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0018    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x3000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x2000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x4000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7000    //TX_A_POST_FILT_S_0
+315    0x3000    //TX_A_POST_FILT_S_1
+316    0x3000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x7000    //TX_A_POST_FILT_S_4
+319    0x7000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x4000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x5000    //TX_B_POST_FILT_6
+329    0x4000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x6000    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C29    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0600    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x0BB8    //TX_NOISE_TH_1
+371    0x0479    //TX_NOISE_TH_2
+372    0x4A38    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0032    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x21E8    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0500    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4900    //TX_MIN_G_CTRL_SSNS
+409    0x1000    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x05A8    //TX_SB_RHO_MEAN2_TH
+441    0x0384    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x0200    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x5E56    //TX_FDEQ_GAIN_0
+568    0x564E    //TX_FDEQ_GAIN_1
+569    0x4E4E    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4646    //TX_FDEQ_GAIN_4
+572    0x4440    //TX_FDEQ_GAIN_5
+573    0x4C56    //TX_FDEQ_GAIN_6
+574    0x4A48    //TX_FDEQ_GAIN_7
+575    0x4242    //TX_FDEQ_GAIN_8
+576    0x4C50    //TX_FDEQ_GAIN_9
+577    0x5252    //TX_FDEQ_GAIN_10
+578    0x6058    //TX_FDEQ_GAIN_11
+579    0x5656    //TX_FDEQ_GAIN_12
+580    0x5670    //TX_FDEQ_GAIN_13
+581    0x7070    //TX_FDEQ_GAIN_14
+582    0x7070    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0504    //TX_FDEQ_BIN_4
+596    0x0906    //TX_FDEQ_BIN_5
+597    0x0407    //TX_FDEQ_BIN_6
+598    0x0A12    //TX_FDEQ_BIN_7
+599    0x0707    //TX_FDEQ_BIN_8
+600    0x160D    //TX_FDEQ_BIN_9
+601    0x0F12    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0505    //TX_FDEQ_BIN_13
+605    0x0505    //TX_FDEQ_BIN_14
+606    0x0504    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x000E    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0700    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x5858    //TX_PREEQ_GAIN_MIC1_11
+678    0x5858    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x120F    //TX_PREEQ_BIN_MIC1_10
+701    0x0E11    //TX_PREEQ_BIN_MIC1_11
+702    0x1109    //TX_PREEQ_BIN_MIC1_12
+703    0x0B1B    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0063    //TX_MIC_CALIBRATION_0
+766    0x0063    //TX_MIC_CALIBRATION_1
+767    0x0063    //TX_MIC_CALIBRATION_2
+768    0x0063    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0003    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0876    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x199A    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x2000    //TX_B_LESSCUT_RTO_MASK
+877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x026C    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7000    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x6B6C    //TX_DTD_THR1_MICMUTE_0
+912    0x7FFF    //TX_DTD_THR1_MICMUTE_1
+913    0x6590    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0180    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7530    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0001    //RX_SAMPLINGFREQ_SIG
+3    0x0001    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x1000    //RX_LMT_THRD
+37    0x7FDF    //RX_LMT_ALPHA
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4840    //RX_FDEQ_GAIN_0
+40    0x4040    //RX_FDEQ_GAIN_1
+41    0x4659    //RX_FDEQ_GAIN_2
+42    0x6474    //RX_FDEQ_GAIN_3
+43    0x7A82    //RX_FDEQ_GAIN_4
+44    0x8180    //RX_FDEQ_GAIN_5
+45    0x8084    //RX_FDEQ_GAIN_6
+46    0x8A88    //RX_FDEQ_GAIN_7
+47    0x8C8C    //RX_FDEQ_GAIN_8
+48    0x8A95    //RX_FDEQ_GAIN_9
+49    0x978E    //RX_FDEQ_GAIN_10
+50    0x8C8C    //RX_FDEQ_GAIN_11
+51    0x7068    //RX_FDEQ_GAIN_12
+52    0x6050    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F0E    //RX_FDEQ_BIN_11
+75    0x100D    //RX_FDEQ_BIN_12
+76    0x110A    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04E6    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x07F2    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B49    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x038C    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x7062    //RX_FDEQ_GAIN_0
+40    0x707C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0397    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0017    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C2    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C2    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03CD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0062    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03CD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0413    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x7080    //RX_FDEQ_GAIN_1
+41    0x8290    //RX_FDEQ_GAIN_2
+42    0x8674    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6C58    //RX_FDEQ_GAIN_10
+50    0x4C48    //RX_FDEQ_GAIN_11
+51    0x4858    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0600    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x1000    //RX_LMT_THRD
+194    0x7FDF    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0031    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0050    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0086    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0551    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x042B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0438    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005F    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705C    //RX_FDEQ_GAIN_0
+40    0x6E7E    //RX_FDEQ_GAIN_1
+41    0x808E    //RX_FDEQ_GAIN_2
+42    0x8472    //RX_FDEQ_GAIN_3
+43    0x7476    //RX_FDEQ_GAIN_4
+44    0x7278    //RX_FDEQ_GAIN_5
+45    0x8092    //RX_FDEQ_GAIN_6
+46    0xA4A2    //RX_FDEQ_GAIN_7
+47    0xB49C    //RX_FDEQ_GAIN_8
+48    0x8E7C    //RX_FDEQ_GAIN_9
+49    0x8664    //RX_FDEQ_GAIN_10
+50    0x5A78    //RX_FDEQ_GAIN_11
+51    0x7C7C    //RX_FDEQ_GAIN_12
+52    0x7888    //RX_FDEQ_GAIN_13
+53    0x7852    //RX_FDEQ_GAIN_14
+54    0x4C70    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x1F06    //RX_FDEQ_BIN_10
+74    0x110B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x2228    //RX_FDEQ_BIN_14
+78    0x5160    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0000    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
 2    0x0026    //TX_PATCH_REG
-3    0x6B56    //TX_SENDFUNC_MODE_0
+3    0x6B7E    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0002    //TX_NUM_MIC
 6    0x0004    //TX_SAMPLINGFREQ_SIG
@@ -28,7 +8039,7 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
+21    0x009C    //TX_DIST2REF1
 22    0x0000    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
@@ -258,12 +8269,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF700    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -291,16 +8302,16 @@
 281    0x0014    //TX_NS_LVL_CTRL_0
 282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
 288    0x0017    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
 294    0x0012    //TX_MIN_GAIN_S_5
 295    0x0012    //TX_MIN_GAIN_S_6
 296    0x0012    //TX_MIN_GAIN_S_7
@@ -322,29 +8333,29 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
+315    0x4000    //TX_A_POST_FILT_S_1
 316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
+326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
+328    0x3000    //TX_B_POST_FILT_6
 329    0x3000    //TX_B_POST_FILT_7
 330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
 340    0x7C29    //TX_LAMBDA_PFILT_S_1
@@ -387,10 +8398,10 @@
 377    0x4E20    //TX_NOISE_TH_5_4
 378    0x39DF    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -398,15 +8409,15 @@
 388    0x0200    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -521,16 +8532,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -559,69 +8570,69 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
 584    0x9898    //TX_FDEQ_GAIN_17
 585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
+586    0x9848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
 603    0x0F0F    //TX_FDEQ_BIN_12
 604    0x0A0F    //TX_FDEQ_BIN_13
 605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
+606    0x0A0B    //TX_FDEQ_BIN_15
 607    0x0C0D    //TX_FDEQ_BIN_16
 608    0x0E0F    //TX_FDEQ_BIN_17
 609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
+610    0x0A00    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
 616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
@@ -679,15 +8690,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -706,13 +8717,13 @@
 696    0x0708    //TX_PREEQ_BIN_MIC1_6
 697    0x0909    //TX_PREEQ_BIN_MIC1_7
 698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
 704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
@@ -790,15 +8801,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -823,8 +8834,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -861,19 +8872,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
 860    0x1000    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
+866    0x0504    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -904,18 +8915,83 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
+10    0x0722    //RX_PGA
 11    0x7FFF    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x5800    //RX_THR_PITCH_DET_0
@@ -930,36 +9006,36 @@
 22    0x000F    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -968,22 +9044,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1016,25 +9092,25 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0001    //RX_FILTINDX
+111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0014    //RX_SPK_VOL
+126    0x1964    //RX_TPKA_FP
+127    0x0080    //RX_MIN_G_FP
+128    0x2000    //RX_MAX_G_FP
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -1063,46 +9139,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1111,22 +9187,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1159,49 +9235,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1210,22 +9286,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1258,49 +9334,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
+129    0x0016    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1309,22 +9385,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1357,49 +9433,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0037    //RX_SPK_VOL
+129    0x0024    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1408,22 +9484,2791 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0059    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0090    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0722    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1964    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0016    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0059    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-NB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7646    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7C00    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7DC8    //TX_DTD_THR1_0
+198    0x7DC8    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7530    //TX_DTD_THR1_4
+202    0x7530    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x1000    //TX_DTD_THR2_0
+205    0x1000    //TX_DTD_THR2_1
+206    0x1000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FB0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFD00    //TX_THR_SN_EST_1
+244    0xFD00    //TX_THR_SN_EST_2
+245    0xFD00    //TX_THR_SN_EST_3
+246    0xF900    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x01A0    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0000    //TX_DELTA_THR_SN_EST_5
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x2000    //TX_LAMBDA_NN_EST_2
+261    0x3000    //TX_LAMBDA_NN_EST_3
+262    0x3000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x3000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x3000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x3000    //TX_MAINREFRTO_TH_H
+277    0x1000    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x4000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0017    //TX_NS_LVL_CTRL_2
+284    0x0017    //TX_NS_LVL_CTRL_3
+285    0x0019    //TX_NS_LVL_CTRL_4
+286    0x0014    //TX_NS_LVL_CTRL_5
+287    0x001B    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x0010    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x4000    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x3000    //TX_SNRI_SUP_7
+308    0x3000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x2000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x4000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x4000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7900    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7900    //TX_LAMBDA_PFILT_S_3
+343    0x7200    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x0C80    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0004    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x09C4    //TX_NOISE_TH_1
+371    0x022C    //TX_NOISE_TH_2
+372    0x4650    //TX_NOISE_TH_3
+373    0x7E2C    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x4650    //TX_NOISE_TH_6
+379    0x0004    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x1000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0003    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x000A    //TX_NS_ENOISE_MIC0_TH
+406    0x0004    //TX_MINENOISE_MIC0_TH
+407    0x0014    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1FFF    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x4000    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0100    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0666    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x6000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x001A    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0080    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0018    //TX_FDEQ_SUBNUM
+567    0x7064    //TX_FDEQ_GAIN_0
+568    0x5E54    //TX_FDEQ_GAIN_1
+569    0x5350    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4642    //TX_FDEQ_GAIN_4
+572    0x4038    //TX_FDEQ_GAIN_5
+573    0x3E44    //TX_FDEQ_GAIN_6
+574    0x3636    //TX_FDEQ_GAIN_7
+575    0x3634    //TX_FDEQ_GAIN_8
+576    0x4448    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0502    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0404    //TX_FDEQ_BIN_4
+596    0x0409    //TX_FDEQ_BIN_5
+597    0x0507    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x0B0A    //TX_FDEQ_BIN_8
+600    0x1109    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C08    //TX_PREEQ_BIN_MIC0_2
+644    0x0700    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0065    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0065    //TX_MIC_CALIBRATION_2
+768    0x0065    //TX_MIC_CALIBRATION_3
+769    0x0044    //TX_MIC_PWR_BIAS_0
+770    0x0044    //TX_MIC_PWR_BIAS_1
+771    0x0044    //TX_MIC_PWR_BIAS_2
+772    0x0044    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0004    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x089C    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0208    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x000A    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x12E1    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7D00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x75F8    //TX_DTD_THR1_MICMUTE_0
+912    0x76C0    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x7FFF    //TX_MICMUTE_C_POST_FLT
+922    0x0FA0    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x0FA0    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0C00    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7148    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0000    //RX_SAMPLINGFREQ_SIG
+3    0x0000    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4840    //RX_FDEQ_GAIN_0
+40    0x3E40    //RX_FDEQ_GAIN_1
+41    0x515E    //RX_FDEQ_GAIN_2
+42    0x6470    //RX_FDEQ_GAIN_3
+43    0x7A84    //RX_FDEQ_GAIN_4
+44    0x7C7A    //RX_FDEQ_GAIN_5
+45    0x7C7C    //RX_FDEQ_GAIN_6
+46    0x7D7C    //RX_FDEQ_GAIN_7
+47    0x7E82    //RX_FDEQ_GAIN_8
+48    0x7C80    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0204    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x055F    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0F0A    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B49    //RX_MAX_G_FP
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01EB    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x655E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01D7    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01D8    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0023    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E2    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0039    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E3    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1458,146 +12303,47 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x005B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x695E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+124    0x01EA    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x5664    //RX_FDEQ_GAIN_1
+41    0x6270    //RX_FDEQ_GAIN_2
+42    0x665E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1606,22 +12352,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1654,49 +12400,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0091    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+124    0x01F3    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7048    //RX_FDEQ_GAIN_0
+40    0x566A    //RX_FDEQ_GAIN_1
+41    0x6A78    //RX_FDEQ_GAIN_2
+42    0x6E5E    //RX_FDEQ_GAIN_3
+43    0x625C    //RX_FDEQ_GAIN_4
+44    0x5852    //RX_FDEQ_GAIN_5
+45    0x5C60    //RX_FDEQ_GAIN_6
+46    0x7684    //RX_FDEQ_GAIN_7
+47    0x8C72    //RX_FDEQ_GAIN_8
+48    0x6048    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -1705,22 +12451,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0103    //RX_FDEQ_BIN_2
+66    0x0504    //RX_FDEQ_BIN_3
+67    0x0104    //RX_FDEQ_BIN_4
+68    0x0509    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x0A06    //RX_FDEQ_BIN_7
+71    0x1006    //RX_FDEQ_BIN_8
+72    0x0B15    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -1755,15 +12501,6207 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0600    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0045    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x055F    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x3E40    //RX_FDEQ_GAIN_1
+198    0x515E    //RX_FDEQ_GAIN_2
+199    0x6470    //RX_FDEQ_GAIN_3
+200    0x7A84    //RX_FDEQ_GAIN_4
+201    0x7C7A    //RX_FDEQ_GAIN_5
+202    0x7C7C    //RX_FDEQ_GAIN_6
+203    0x7D7C    //RX_FDEQ_GAIN_7
+204    0x7E82    //RX_FDEQ_GAIN_8
+205    0x7C80    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
-#CASE_NAME  HANDSET-HANDSET-CUSTOM2-FB
-#PARAM_TYPE TX+RX
-#TOTAL_CUSTOM_STEP 7
+#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-WB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0036    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0001    //TX_SAMPLINGFREQ_SIG
+7    0x0001    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x6000    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x0200    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7918    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFB00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x01A0    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x2000    //TX_MAINREFRTOH_TH_H
+275    0x1400    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0018    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x001A    //TX_NS_LVL_CTRL_4
+286    0x001E    //TX_NS_LVL_CTRL_5
+287    0x001C    //TX_NS_LVL_CTRL_6
+288    0x001C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x000A    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0012    //TX_MIN_GAIN_S_3
+293    0x0018    //TX_MIN_GAIN_S_4
+294    0x0018    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0018    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x3000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x2000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x4000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7000    //TX_A_POST_FILT_S_0
+315    0x3000    //TX_A_POST_FILT_S_1
+316    0x3000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x7000    //TX_A_POST_FILT_S_4
+319    0x7000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x4000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x5000    //TX_B_POST_FILT_6
+329    0x4000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x6000    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C29    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0600    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x0BB8    //TX_NOISE_TH_1
+371    0x0479    //TX_NOISE_TH_2
+372    0x4A38    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0032    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x21E8    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0500    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4900    //TX_MIN_G_CTRL_SSNS
+409    0x1000    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x05A8    //TX_SB_RHO_MEAN2_TH
+441    0x0384    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x0200    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x5E56    //TX_FDEQ_GAIN_0
+568    0x564E    //TX_FDEQ_GAIN_1
+569    0x4E4E    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4646    //TX_FDEQ_GAIN_4
+572    0x4440    //TX_FDEQ_GAIN_5
+573    0x4C56    //TX_FDEQ_GAIN_6
+574    0x4A48    //TX_FDEQ_GAIN_7
+575    0x4242    //TX_FDEQ_GAIN_8
+576    0x4C50    //TX_FDEQ_GAIN_9
+577    0x524E    //TX_FDEQ_GAIN_10
+578    0x5658    //TX_FDEQ_GAIN_11
+579    0x5656    //TX_FDEQ_GAIN_12
+580    0x5670    //TX_FDEQ_GAIN_13
+581    0x7070    //TX_FDEQ_GAIN_14
+582    0x7070    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0504    //TX_FDEQ_BIN_4
+596    0x0906    //TX_FDEQ_BIN_5
+597    0x0407    //TX_FDEQ_BIN_6
+598    0x0A12    //TX_FDEQ_BIN_7
+599    0x0707    //TX_FDEQ_BIN_8
+600    0x160D    //TX_FDEQ_BIN_9
+601    0x0F12    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0505    //TX_FDEQ_BIN_13
+605    0x0505    //TX_FDEQ_BIN_14
+606    0x0504    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x000E    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0700    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x5858    //TX_PREEQ_GAIN_MIC1_11
+678    0x5858    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x120F    //TX_PREEQ_BIN_MIC1_10
+701    0x0E11    //TX_PREEQ_BIN_MIC1_11
+702    0x1109    //TX_PREEQ_BIN_MIC1_12
+703    0x0B1B    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0063    //TX_MIC_CALIBRATION_0
+766    0x0063    //TX_MIC_CALIBRATION_1
+767    0x0063    //TX_MIC_CALIBRATION_2
+768    0x0063    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0003    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0876    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x199A    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x2000    //TX_B_LESSCUT_RTO_MASK
+877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x026C    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7000    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x6B6C    //TX_DTD_THR1_MICMUTE_0
+912    0x7FFF    //TX_DTD_THR1_MICMUTE_1
+913    0x6590    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0180    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7530    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0001    //RX_SAMPLINGFREQ_SIG
+3    0x0001    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x1000    //RX_LMT_THRD
+37    0x7FDF    //RX_LMT_ALPHA
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4840    //RX_FDEQ_GAIN_0
+40    0x4040    //RX_FDEQ_GAIN_1
+41    0x4659    //RX_FDEQ_GAIN_2
+42    0x6474    //RX_FDEQ_GAIN_3
+43    0x7A82    //RX_FDEQ_GAIN_4
+44    0x8180    //RX_FDEQ_GAIN_5
+45    0x8084    //RX_FDEQ_GAIN_6
+46    0x8A88    //RX_FDEQ_GAIN_7
+47    0x8C8C    //RX_FDEQ_GAIN_8
+48    0x8A95    //RX_FDEQ_GAIN_9
+49    0x978E    //RX_FDEQ_GAIN_10
+50    0x8C8C    //RX_FDEQ_GAIN_11
+51    0x7068    //RX_FDEQ_GAIN_12
+52    0x6050    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F0E    //RX_FDEQ_BIN_11
+75    0x100D    //RX_FDEQ_BIN_12
+76    0x110A    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04E6    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x07F2    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B49    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x034B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x7062    //RX_FDEQ_GAIN_0
+40    0x707C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0355    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0017    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0373    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0373    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x037D    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0062    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03DE    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E74    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x008E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03D3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x7080    //RX_FDEQ_GAIN_1
+41    0x8290    //RX_FDEQ_GAIN_2
+42    0x8674    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x9074    //RX_FDEQ_GAIN_9
+49    0x6456    //RX_FDEQ_GAIN_10
+50    0x504E    //RX_FDEQ_GAIN_11
+51    0x4E58    //RX_FDEQ_GAIN_12
+52    0x5858    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A1E    //RX_FDEQ_BIN_9
+73    0x0F05    //RX_FDEQ_BIN_10
+74    0x0C06    //RX_FDEQ_BIN_11
+75    0x0311    //RX_FDEQ_BIN_12
+76    0x2816    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0600    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x1000    //RX_LMT_THRD
+194    0x7FDF    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0031    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0050    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0086    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04E6    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4840    //RX_FDEQ_GAIN_0
+197    0x4040    //RX_FDEQ_GAIN_1
+198    0x4659    //RX_FDEQ_GAIN_2
+199    0x6474    //RX_FDEQ_GAIN_3
+200    0x7A82    //RX_FDEQ_GAIN_4
+201    0x8180    //RX_FDEQ_GAIN_5
+202    0x8084    //RX_FDEQ_GAIN_6
+203    0x8A88    //RX_FDEQ_GAIN_7
+204    0x8C8C    //RX_FDEQ_GAIN_8
+205    0x8A95    //RX_FDEQ_GAIN_9
+206    0x978E    //RX_FDEQ_GAIN_10
+207    0x8C8C    //RX_FDEQ_GAIN_11
+208    0x7068    //RX_FDEQ_GAIN_12
+209    0x6050    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F0E    //RX_FDEQ_BIN_11
+232    0x100D    //RX_FDEQ_BIN_12
+233    0x110A    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x565A    //TX_FDEQ_GAIN_9
+577    0x585A    //TX_FDEQ_GAIN_10
+578    0x5C5C    //TX_FDEQ_GAIN_11
+579    0x5460    //TX_FDEQ_GAIN_12
+580    0x644E    //TX_FDEQ_GAIN_13
+581    0x6448    //TX_FDEQ_GAIN_14
+582    0x6048    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x2015    //TX_FDEQ_BIN_13
+605    0x231C    //TX_FDEQ_BIN_14
+606    0x201C    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0551    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03D3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03F5    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03DE    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03F5    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03EA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005F    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03EA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x043E    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x7080    //RX_FDEQ_GAIN_1
+41    0x8290    //RX_FDEQ_GAIN_2
+42    0x8672    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x6264    //RX_FDEQ_GAIN_11
+51    0x6464    //RX_FDEQ_GAIN_12
+52    0x6A78    //RX_FDEQ_GAIN_13
+53    0x6C50    //RX_FDEQ_GAIN_14
+54    0x4E5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0000    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
 2    0x0026    //TX_PATCH_REG
-3    0x6B5E    //TX_SENDFUNC_MODE_0
+3    0x6B7E    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0002    //TX_NUM_MIC
 6    0x0004    //TX_SAMPLINGFREQ_SIG
@@ -1781,7 +18719,7 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
+21    0x009C    //TX_DIST2REF1
 22    0x0000    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
@@ -2011,12 +18949,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF700    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -2044,16 +18982,16 @@
 281    0x0014    //TX_NS_LVL_CTRL_0
 282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
 288    0x0017    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
 294    0x0012    //TX_MIN_GAIN_S_5
 295    0x0012    //TX_MIN_GAIN_S_6
 296    0x0012    //TX_MIN_GAIN_S_7
@@ -2075,29 +19013,29 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
+315    0x4000    //TX_A_POST_FILT_S_1
 316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
+326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
+328    0x3000    //TX_B_POST_FILT_6
 329    0x3000    //TX_B_POST_FILT_7
 330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
 340    0x7C29    //TX_LAMBDA_PFILT_S_1
@@ -2140,10 +19078,10 @@
 377    0x4E20    //TX_NOISE_TH_5_4
 378    0x39DF    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -2151,15 +19089,15 @@
 388    0x0200    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -2274,16 +19212,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -2312,69 +19250,69 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
 584    0x9898    //TX_FDEQ_GAIN_17
 585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
+586    0x9848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
 603    0x0F0F    //TX_FDEQ_BIN_12
 604    0x0A0F    //TX_FDEQ_BIN_13
 605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
+606    0x0A0B    //TX_FDEQ_BIN_15
 607    0x0C0D    //TX_FDEQ_BIN_16
 608    0x0E0F    //TX_FDEQ_BIN_17
 609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
+610    0x0A00    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
 616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
@@ -2432,15 +19370,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -2459,13 +19397,13 @@
 696    0x0708    //TX_PREEQ_BIN_MIC1_6
 697    0x0909    //TX_PREEQ_BIN_MIC1_7
 698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
 704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
@@ -2543,15 +19481,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -2576,8 +19514,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -2614,19 +19552,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
 860    0x1000    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
+866    0x0504    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -2657,18 +19595,83 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
+10    0x0722    //RX_PGA
 11    0x7FFF    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x5800    //RX_THR_PITCH_DET_0
@@ -2683,36 +19686,36 @@
 22    0x000F    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -2721,22 +19724,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -2769,25 +19772,25 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0001    //RX_FILTINDX
+111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0014    //RX_SPK_VOL
+126    0x1964    //RX_TPKA_FP
+127    0x0080    //RX_MIN_G_FP
+128    0x2000    //RX_MAX_G_FP
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -2816,46 +19819,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -2864,22 +19867,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -2912,49 +19915,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -2963,22 +19966,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3011,49 +20014,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
+129    0x0016    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -3062,22 +20065,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3110,49 +20113,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0037    //RX_SPK_VOL
+129    0x0024    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -3161,22 +20164,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3209,49 +20212,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
+129    0x003A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -3260,22 +20263,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3308,49 +20311,2224 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
+129    0x0059    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0090    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0722    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1964    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0016    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0059    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-CUSTOM1-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F77    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0551    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x042B    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x695E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -3359,22 +22537,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3407,49 +22585,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
+124    0x0451    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -3458,22 +22636,517 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0438    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005F    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705C    //RX_FDEQ_GAIN_0
+40    0x6E7E    //RX_FDEQ_GAIN_1
+41    0x808E    //RX_FDEQ_GAIN_2
+42    0x8472    //RX_FDEQ_GAIN_3
+43    0x7476    //RX_FDEQ_GAIN_4
+44    0x7278    //RX_FDEQ_GAIN_5
+45    0x8092    //RX_FDEQ_GAIN_6
+46    0xA4A2    //RX_FDEQ_GAIN_7
+47    0xB49C    //RX_FDEQ_GAIN_8
+48    0x8E7C    //RX_FDEQ_GAIN_9
+49    0x8664    //RX_FDEQ_GAIN_10
+50    0x5A78    //RX_FDEQ_GAIN_11
+51    0x7C7C    //RX_FDEQ_GAIN_12
+52    0x7888    //RX_FDEQ_GAIN_13
+53    0x7852    //RX_FDEQ_GAIN_14
+54    0x4C70    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x1F06    //RX_FDEQ_BIN_10
+74    0x110B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x2228    //RX_FDEQ_BIN_14
+78    0x5160    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -3508,10 +23181,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HANDSET-HANDSET-CUSTOM1-FB
-#PARAM_TYPE TX+RX
-#TOTAL_CUSTOM_STEP 7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0000    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -3534,7 +24059,7 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
+21    0x00A4    //TX_DIST2REF1
 22    0x0000    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
@@ -3764,12 +24289,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF700    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -3797,16 +24322,16 @@
 281    0x0014    //TX_NS_LVL_CTRL_0
 282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
 288    0x0017    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
 294    0x0012    //TX_MIN_GAIN_S_5
 295    0x0012    //TX_MIN_GAIN_S_6
 296    0x0012    //TX_MIN_GAIN_S_7
@@ -3828,29 +24353,29 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
+315    0x4000    //TX_A_POST_FILT_S_1
 316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
+326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
+328    0x3000    //TX_B_POST_FILT_6
 329    0x3000    //TX_B_POST_FILT_7
 330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
 340    0x7C29    //TX_LAMBDA_PFILT_S_1
@@ -3893,10 +24418,10 @@
 377    0x4E20    //TX_NOISE_TH_5_4
 378    0x39DF    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -3904,15 +24429,15 @@
 388    0x0200    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -4027,16 +24552,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -4065,1818 +24590,65 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
 584    0x9898    //TX_FDEQ_GAIN_17
 585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
-603    0x0F0F    //TX_FDEQ_BIN_12
-604    0x0A0F    //TX_FDEQ_BIN_13
-605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
-607    0x0C0D    //TX_FDEQ_BIN_16
-608    0x0E0F    //TX_FDEQ_BIN_17
-609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x1812    //TX_PREEQ_BIN_MIC0_0
-642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
-643    0x0808    //TX_PREEQ_BIN_MIC0_2
-644    0x080A    //TX_PREEQ_BIN_MIC0_3
-645    0x0B09    //TX_PREEQ_BIN_MIC0_4
-646    0x0A06    //TX_PREEQ_BIN_MIC0_5
-647    0x0606    //TX_PREEQ_BIN_MIC0_6
-648    0x0605    //TX_PREEQ_BIN_MIC0_7
-649    0x050A    //TX_PREEQ_BIN_MIC0_8
-650    0x1505    //TX_PREEQ_BIN_MIC0_9
-651    0x0506    //TX_PREEQ_BIN_MIC0_10
-652    0x0615    //TX_PREEQ_BIN_MIC0_11
-653    0x1516    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x2021    //TX_PREEQ_BIN_MIC0_14
-656    0x2021    //TX_PREEQ_BIN_MIC0_15
-657    0x0800    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x0909    //TX_PREEQ_BIN_MIC1_7
-698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
-704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0001    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0014    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0037    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x695E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0000    //TX_SAMPLINGFREQ_SIG
-7    0x0000    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7646    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6000    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x0040    //TX_MIN_EQ_RE_EST_0
-153    0x0040    //TX_MIN_EQ_RE_EST_1
-154    0x0040    //TX_MIN_EQ_RE_EST_2
-155    0x0040    //TX_MIN_EQ_RE_EST_3
-156    0x0040    //TX_MIN_EQ_RE_EST_4
-157    0x0040    //TX_MIN_EQ_RE_EST_5
-158    0x0040    //TX_MIN_EQ_RE_EST_6
-159    0x0040    //TX_MIN_EQ_RE_EST_7
-160    0x0040    //TX_MIN_EQ_RE_EST_8
-161    0x0040    //TX_MIN_EQ_RE_EST_9
-162    0x0040    //TX_MIN_EQ_RE_EST_10
-163    0x0040    //TX_MIN_EQ_RE_EST_11
-164    0x0040    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7B00    //TX_DTD_THR1_0
-198    0x7B00    //TX_DTD_THR1_1
-199    0x7B00    //TX_DTD_THR1_2
-200    0x7B00    //TX_DTD_THR1_3
-201    0x7B00    //TX_DTD_THR1_4
-202    0x7B00    //TX_DTD_THR1_5
-203    0x7B00    //TX_DTD_THR1_6
-204    0x1000    //TX_DTD_THR2_0
-205    0x1000    //TX_DTD_THR2_1
-206    0x1000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0FA0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xF800    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF900    //TX_THR_SN_EST_3
-246    0xF900    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x01A0    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x3000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x3000    //TX_LAMBDA_NN_EST_4
-263    0x3000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x3000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x3000    //TX_MAINREFRTOH_TH_H
-275    0x1000    //TX_MAINREFRTOH_TH_L
-276    0x3000    //TX_MAINREFRTO_TH_H
-277    0x1000    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x4000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x001B    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x0017    //TX_NS_LVL_CTRL_3
-285    0x0017    //TX_NS_LVL_CTRL_4
-286    0x0019    //TX_NS_LVL_CTRL_5
-287    0x0014    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x0010    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x0014    //TX_MIN_GAIN_S_6
-296    0x0014    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x4000    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x3000    //TX_SNRI_SUP_7
-308    0x3000    //TX_THR_LFNS
-309    0x001A    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x2000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x5000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x2000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x4000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x7FFF    //TX_B_POST_FILT_2
-325    0x5000    //TX_B_POST_FILT_3
-326    0x7FFF    //TX_B_POST_FILT_4
-327    0x7FFF    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7200    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7400    //TX_LAMBDA_PFILT_S_4
-344    0x7200    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x0C80    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0004    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0320    //TX_NOISE_TH_1
-371    0x022C    //TX_NOISE_TH_2
-372    0x2710    //TX_NOISE_TH_3
-373    0x1B58    //TX_NOISE_TH_4
-374    0x7FFF    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x0640    //TX_NOISE_TH_6
-379    0x0004    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x000A    //TX_NS_ENOISE_MIC0_TH
-406    0x0004    //TX_MINENOISE_MIC0_TH
-407    0x0014    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x0400    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x4000    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0640    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x001A    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0080    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0018    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4E    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x443A    //TX_FDEQ_GAIN_5
-573    0x3E42    //TX_FDEQ_GAIN_6
-574    0x423C    //TX_FDEQ_GAIN_7
-575    0x3434    //TX_FDEQ_GAIN_8
-576    0x3040    //TX_FDEQ_GAIN_9
-577    0x4040    //TX_FDEQ_GAIN_10
-578    0x4040    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
+586    0x9848    //TX_FDEQ_GAIN_19
 587    0x4848    //TX_FDEQ_GAIN_20
 588    0x4848    //TX_FDEQ_GAIN_21
 589    0x4848    //TX_FDEQ_GAIN_22
 590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0302    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F10    //TX_FDEQ_BIN_8
-600    0x100F    //TX_FDEQ_BIN_9
-601    0x0101    //TX_FDEQ_BIN_10
-602    0x0101    //TX_FDEQ_BIN_11
-603    0x0000    //TX_FDEQ_BIN_12
-604    0x0000    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0A0F    //TX_FDEQ_BIN_13
+605    0x0809    //TX_FDEQ_BIN_14
+606    0x0A0B    //TX_FDEQ_BIN_15
+607    0x0C0D    //TX_FDEQ_BIN_16
+608    0x0E0F    //TX_FDEQ_BIN_17
+609    0x1013    //TX_FDEQ_BIN_18
+610    0x0A00    //TX_FDEQ_BIN_19
 611    0x0000    //TX_FDEQ_BIN_20
 612    0x0000    //TX_FDEQ_BIN_21
 613    0x0000    //TX_FDEQ_BIN_22
@@ -5907,5265 +24679,6 @@
 638    0x4848    //TX_PREEQ_GAIN_MIC0_21
 639    0x4848    //TX_PREEQ_GAIN_MIC0_22
 640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C08    //TX_PREEQ_BIN_MIC0_2
-644    0x0700    //TX_PREEQ_BIN_MIC0_3
-645    0x0000    //TX_PREEQ_BIN_MIC0_4
-646    0x0000    //TX_PREEQ_BIN_MIC0_5
-647    0x0000    //TX_PREEQ_BIN_MIC0_6
-648    0x0000    //TX_PREEQ_BIN_MIC0_7
-649    0x0000    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x484A    //TX_PREEQ_GAIN_MIC1_8
-675    0x4C50    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D08    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
-769    0x0044    //TX_MIC_PWR_BIAS_0
-770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0003    //TX_GAIN_LIMIT_2
-776    0x0004    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0027    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0042    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0070    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00B2    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x011E    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0008    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01D8    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0001    //TX_SAMPLINGFREQ_SIG
-7    0x0001    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7B02    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0400    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFB00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x01A0    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x5000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x2000    //TX_MAINREFRTOH_TH_H
-275    0x1400    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0018    //TX_NS_LVL_CTRL_0
-282    0x001C    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x001C    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x001A    //TX_NS_LVL_CTRL_5
-287    0x001E    //TX_NS_LVL_CTRL_6
-288    0x001C    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0018    //TX_MIN_GAIN_S_1
-291    0x0012    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0012    //TX_MIN_GAIN_S_4
-294    0x0018    //TX_MIN_GAIN_S_5
-295    0x0018    //TX_MIN_GAIN_S_6
-296    0x0018    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
-307    0x4000    //TX_SNRI_SUP_7
-308    0x4000    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x7000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x7000    //TX_A_POST_FILT_S_5
-320    0x7000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x5000    //TX_B_POST_FILT_2
-325    0x4000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x4000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C29    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0600    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0139    //TX_NOISE_TH_1
-371    0x0479    //TX_NOISE_TH_2
-372    0x2E90    //TX_NOISE_TH_3
-373    0x4422    //TX_NOISE_TH_4
-374    0x5586    //TX_NOISE_TH_5
-375    0x4425    //TX_NOISE_TH_5_2
-376    0x0032    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x21E8    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x1000    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x05A8    //TX_SB_RHO_MEAN2_TH
-441    0x0384    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0280    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x0200    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4E50    //TX_FDEQ_GAIN_3
-571    0x4C48    //TX_FDEQ_GAIN_4
-572    0x4840    //TX_FDEQ_GAIN_5
-573    0x4850    //TX_FDEQ_GAIN_6
-574    0x5050    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4850    //TX_FDEQ_GAIN_10
-578    0x5860    //TX_FDEQ_GAIN_11
-579    0x5C60    //TX_FDEQ_GAIN_12
-580    0x6070    //TX_FDEQ_GAIN_13
-581    0x6A70    //TX_FDEQ_GAIN_14
-582    0x8490    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F0B    //TX_FDEQ_BIN_8
-600    0x190F    //TX_FDEQ_BIN_9
-601    0x1212    //TX_FDEQ_BIN_10
-602    0x0D2B    //TX_FDEQ_BIN_11
-603    0x0906    //TX_FDEQ_BIN_12
-604    0x0101    //TX_FDEQ_BIN_13
-605    0x0101    //TX_FDEQ_BIN_14
-606    0x0101    //TX_FDEQ_BIN_15
-607    0x0101    //TX_FDEQ_BIN_16
-608    0x0101    //TX_FDEQ_BIN_17
-609    0x0101    //TX_FDEQ_BIN_18
-610    0x0101    //TX_FDEQ_BIN_19
-611    0x0101    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0F09    //TX_PREEQ_BIN_MIC0_5
-647    0x0909    //TX_PREEQ_BIN_MIC0_6
-648    0x0908    //TX_PREEQ_BIN_MIC0_7
-649    0x0700    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x3448    //TX_PREEQ_GAIN_MIC1_13
-680    0x3848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0F10    //TX_PREEQ_BIN_MIC1_10
-701    0x1908    //TX_PREEQ_BIN_MIC1_11
-702    0x110C    //TX_PREEQ_BIN_MIC1_12
-703    0x0C02    //TX_PREEQ_BIN_MIC1_13
-704    0x0A00    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0004    //TX_GAIN_LIMIT_2
-776    0x0003    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05F5    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x199A    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x2000    //TX_B_LESSCUT_RTO_MASK
-877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0001    //RX_SAMPLINGFREQ_SIG
-3    0x0001    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x1000    //RX_LMT_THRD
-37    0x7FDF    //RX_LMT_ALPHA
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x001A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0049    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x007A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00C4    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x013B    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0008    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01F9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4E5C    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5A56    //RX_FDEQ_GAIN_4
-44    0x565C    //RX_FDEQ_GAIN_5
-45    0x626C    //RX_FDEQ_GAIN_6
-46    0x7A84    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0003    //TX_SAMPLINGFREQ_SIG
-7    0x0003    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0100    //TX_MIN_EQ_RE_EST_11
-164    0x0100    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x002C    //TX_NS_LVL_CTRL_2
-284    0x0020    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x2000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x0190    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5DC0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x5DC0    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x02F0    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x984E    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4C    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4240    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4840    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4E4C    //TX_FDEQ_GAIN_10
-578    0x5A60    //TX_FDEQ_GAIN_11
-579    0x6262    //TX_FDEQ_GAIN_12
-580    0x5A3C    //TX_FDEQ_GAIN_13
-581    0x5656    //TX_FDEQ_GAIN_14
-582    0x585E    //TX_FDEQ_GAIN_15
-583    0x6698    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0201    //TX_FDEQ_BIN_0
-592    0x0105    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0509    //TX_FDEQ_BIN_7
-599    0x0E09    //TX_FDEQ_BIN_8
-600    0x150A    //TX_FDEQ_BIN_9
-601    0x071E    //TX_FDEQ_BIN_10
-602    0x152B    //TX_FDEQ_BIN_11
-603    0x0617    //TX_FDEQ_BIN_12
-604    0x3226    //TX_FDEQ_BIN_13
-605    0x190A    //TX_FDEQ_BIN_14
-606    0x0A0A    //TX_FDEQ_BIN_15
-607    0x0A0A    //TX_FDEQ_BIN_16
-608    0x0A0A    //TX_FDEQ_BIN_17
-609    0x0A0A    //TX_FDEQ_BIN_18
-610    0x0A0A    //TX_FDEQ_BIN_19
-611    0x0A0A    //TX_FDEQ_BIN_20
-612    0x0A0B    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x110C    //TX_PREEQ_BIN_MIC0_6
-648    0x0A04    //TX_PREEQ_BIN_MIC0_7
-649    0x0A0C    //TX_PREEQ_BIN_MIC0_8
-650    0x1F08    //TX_PREEQ_BIN_MIC0_9
-651    0x0808    //TX_PREEQ_BIN_MIC0_10
-652    0x0920    //TX_PREEQ_BIN_MIC0_11
-653    0x2020    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4834    //TX_PREEQ_GAIN_MIC1_12
-679    0x4838    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x5848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x1013    //TX_PREEQ_BIN_MIC1_10
-701    0x1508    //TX_PREEQ_BIN_MIC1_11
-702    0x1D0A    //TX_PREEQ_BIN_MIC1_12
-703    0x040A    //TX_PREEQ_BIN_MIC1_13
-704    0x0A21    //TX_PREEQ_BIN_MIC1_14
-705    0x2890    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0056    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0042    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0005    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
-776    0x0000    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05D3    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0003    //RX_SAMPLINGFREQ_SIG
-3    0x0003    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0028    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0044    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x006F    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00B0    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x011C    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01D9    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484C    //RX_FDEQ_GAIN_1
-41    0x5458    //RX_FDEQ_GAIN_2
-42    0x5658    //RX_FDEQ_GAIN_3
-43    0x5452    //RX_FDEQ_GAIN_4
-44    0x525A    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4A4A    //RX_FDEQ_GAIN_17
-57    0x585A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0103    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6B7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0400    //TX_MIN_EQ_RE_EST_0
-153    0x0400    //TX_MIN_EQ_RE_EST_1
-154    0x0800    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x1000    //TX_MIN_EQ_RE_EST_4
-157    0x1000    //TX_MIN_EQ_RE_EST_5
-158    0x1000    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x1000    //TX_MIN_EQ_RE_EST_8
-161    0x1000    //TX_MIN_EQ_RE_EST_9
-162    0x1000    //TX_MIN_EQ_RE_EST_10
-163    0x1000    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x7000    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x2000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x6000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x00C6    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x47E0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x4BD6    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x051E    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
-603    0x0F0F    //TX_FDEQ_BIN_12
-604    0x0A0F    //TX_FDEQ_BIN_13
-605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
-607    0x0C0D    //TX_FDEQ_BIN_16
-608    0x0E0F    //TX_FDEQ_BIN_17
-609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
 641    0x1812    //TX_PREEQ_BIN_MIC0_0
 642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
 643    0x0808    //TX_PREEQ_BIN_MIC0_2
@@ -11197,15 +24710,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -11224,13 +24737,13 @@
 696    0x0708    //TX_PREEQ_BIN_MIC1_6
 697    0x0909    //TX_PREEQ_BIN_MIC1_7
 698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
 704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
@@ -11308,15 +24821,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -11341,8 +24854,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -11379,19 +24892,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
 860    0x1000    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
+866    0x0504    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -11422,14030 +24935,71 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0001    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0014    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0037    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x695E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0000    //TX_SAMPLINGFREQ_SIG
-7    0x0000    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7646    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6000    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x0040    //TX_MIN_EQ_RE_EST_0
-153    0x0040    //TX_MIN_EQ_RE_EST_1
-154    0x0040    //TX_MIN_EQ_RE_EST_2
-155    0x0040    //TX_MIN_EQ_RE_EST_3
-156    0x0040    //TX_MIN_EQ_RE_EST_4
-157    0x0040    //TX_MIN_EQ_RE_EST_5
-158    0x0040    //TX_MIN_EQ_RE_EST_6
-159    0x0040    //TX_MIN_EQ_RE_EST_7
-160    0x0040    //TX_MIN_EQ_RE_EST_8
-161    0x0040    //TX_MIN_EQ_RE_EST_9
-162    0x0040    //TX_MIN_EQ_RE_EST_10
-163    0x0040    //TX_MIN_EQ_RE_EST_11
-164    0x0040    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7B00    //TX_DTD_THR1_0
-198    0x7B00    //TX_DTD_THR1_1
-199    0x7B00    //TX_DTD_THR1_2
-200    0x7B00    //TX_DTD_THR1_3
-201    0x7B00    //TX_DTD_THR1_4
-202    0x7B00    //TX_DTD_THR1_5
-203    0x7B00    //TX_DTD_THR1_6
-204    0x1000    //TX_DTD_THR2_0
-205    0x1000    //TX_DTD_THR2_1
-206    0x1000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0FA0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xF800    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF900    //TX_THR_SN_EST_3
-246    0xF900    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x01A0    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x3000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x3000    //TX_LAMBDA_NN_EST_4
-263    0x3000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x3000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x3000    //TX_MAINREFRTOH_TH_H
-275    0x1000    //TX_MAINREFRTOH_TH_L
-276    0x3000    //TX_MAINREFRTO_TH_H
-277    0x1000    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x4000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x001B    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x0017    //TX_NS_LVL_CTRL_3
-285    0x0017    //TX_NS_LVL_CTRL_4
-286    0x0019    //TX_NS_LVL_CTRL_5
-287    0x0014    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x0010    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x0014    //TX_MIN_GAIN_S_6
-296    0x0014    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x4000    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x3000    //TX_SNRI_SUP_7
-308    0x3000    //TX_THR_LFNS
-309    0x001A    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x2000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x5000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x2000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x4000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x7FFF    //TX_B_POST_FILT_2
-325    0x5000    //TX_B_POST_FILT_3
-326    0x7FFF    //TX_B_POST_FILT_4
-327    0x7FFF    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7200    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7400    //TX_LAMBDA_PFILT_S_4
-344    0x7200    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x0C80    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0004    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0320    //TX_NOISE_TH_1
-371    0x022C    //TX_NOISE_TH_2
-372    0x2710    //TX_NOISE_TH_3
-373    0x1B58    //TX_NOISE_TH_4
-374    0x7FFF    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x0640    //TX_NOISE_TH_6
-379    0x0004    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x000A    //TX_NS_ENOISE_MIC0_TH
-406    0x0004    //TX_MINENOISE_MIC0_TH
-407    0x0014    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x0400    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x4000    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0640    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x001A    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0080    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0018    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4E    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x443A    //TX_FDEQ_GAIN_5
-573    0x3E42    //TX_FDEQ_GAIN_6
-574    0x423C    //TX_FDEQ_GAIN_7
-575    0x3434    //TX_FDEQ_GAIN_8
-576    0x3040    //TX_FDEQ_GAIN_9
-577    0x4040    //TX_FDEQ_GAIN_10
-578    0x4040    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0302    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F10    //TX_FDEQ_BIN_8
-600    0x100F    //TX_FDEQ_BIN_9
-601    0x0101    //TX_FDEQ_BIN_10
-602    0x0101    //TX_FDEQ_BIN_11
-603    0x0000    //TX_FDEQ_BIN_12
-604    0x0000    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C08    //TX_PREEQ_BIN_MIC0_2
-644    0x0700    //TX_PREEQ_BIN_MIC0_3
-645    0x0000    //TX_PREEQ_BIN_MIC0_4
-646    0x0000    //TX_PREEQ_BIN_MIC0_5
-647    0x0000    //TX_PREEQ_BIN_MIC0_6
-648    0x0000    //TX_PREEQ_BIN_MIC0_7
-649    0x0000    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x484A    //TX_PREEQ_GAIN_MIC1_8
-675    0x4C50    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D08    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
-769    0x0044    //TX_MIC_PWR_BIAS_0
-770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0003    //TX_GAIN_LIMIT_2
-776    0x0004    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0001    //TX_SAMPLINGFREQ_SIG
-7    0x0001    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7B02    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0400    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFB00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x01A0    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x5000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x2000    //TX_MAINREFRTOH_TH_H
-275    0x1400    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0018    //TX_NS_LVL_CTRL_0
-282    0x001C    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x001C    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x001A    //TX_NS_LVL_CTRL_5
-287    0x001E    //TX_NS_LVL_CTRL_6
-288    0x001C    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0018    //TX_MIN_GAIN_S_1
-291    0x0012    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0012    //TX_MIN_GAIN_S_4
-294    0x0018    //TX_MIN_GAIN_S_5
-295    0x0018    //TX_MIN_GAIN_S_6
-296    0x0018    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
-307    0x4000    //TX_SNRI_SUP_7
-308    0x4000    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x7000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x7000    //TX_A_POST_FILT_S_5
-320    0x7000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x5000    //TX_B_POST_FILT_2
-325    0x4000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x4000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C29    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0600    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0139    //TX_NOISE_TH_1
-371    0x0479    //TX_NOISE_TH_2
-372    0x2E90    //TX_NOISE_TH_3
-373    0x4422    //TX_NOISE_TH_4
-374    0x5586    //TX_NOISE_TH_5
-375    0x4425    //TX_NOISE_TH_5_2
-376    0x0032    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x21E8    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x1000    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x05A8    //TX_SB_RHO_MEAN2_TH
-441    0x0384    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0280    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x0200    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4E50    //TX_FDEQ_GAIN_3
-571    0x4C48    //TX_FDEQ_GAIN_4
-572    0x4840    //TX_FDEQ_GAIN_5
-573    0x4850    //TX_FDEQ_GAIN_6
-574    0x5050    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4850    //TX_FDEQ_GAIN_10
-578    0x5860    //TX_FDEQ_GAIN_11
-579    0x5C60    //TX_FDEQ_GAIN_12
-580    0x6070    //TX_FDEQ_GAIN_13
-581    0x6A70    //TX_FDEQ_GAIN_14
-582    0x8490    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F0B    //TX_FDEQ_BIN_8
-600    0x190F    //TX_FDEQ_BIN_9
-601    0x1212    //TX_FDEQ_BIN_10
-602    0x0D2B    //TX_FDEQ_BIN_11
-603    0x0906    //TX_FDEQ_BIN_12
-604    0x0101    //TX_FDEQ_BIN_13
-605    0x0101    //TX_FDEQ_BIN_14
-606    0x0101    //TX_FDEQ_BIN_15
-607    0x0101    //TX_FDEQ_BIN_16
-608    0x0101    //TX_FDEQ_BIN_17
-609    0x0101    //TX_FDEQ_BIN_18
-610    0x0101    //TX_FDEQ_BIN_19
-611    0x0101    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0F09    //TX_PREEQ_BIN_MIC0_5
-647    0x0909    //TX_PREEQ_BIN_MIC0_6
-648    0x0908    //TX_PREEQ_BIN_MIC0_7
-649    0x0700    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x3448    //TX_PREEQ_GAIN_MIC1_13
-680    0x3848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0F10    //TX_PREEQ_BIN_MIC1_10
-701    0x1908    //TX_PREEQ_BIN_MIC1_11
-702    0x110C    //TX_PREEQ_BIN_MIC1_12
-703    0x0C02    //TX_PREEQ_BIN_MIC1_13
-704    0x0A00    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0004    //TX_GAIN_LIMIT_2
-776    0x0003    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05F5    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x199A    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x2000    //TX_B_LESSCUT_RTO_MASK
-877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0003    //TX_SAMPLINGFREQ_SIG
-7    0x0003    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0100    //TX_MIN_EQ_RE_EST_11
-164    0x0100    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x002C    //TX_NS_LVL_CTRL_2
-284    0x0020    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x2000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x0190    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5DC0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x5DC0    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x02F0    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x984E    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4C    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4240    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4840    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4E4C    //TX_FDEQ_GAIN_10
-578    0x5A60    //TX_FDEQ_GAIN_11
-579    0x6262    //TX_FDEQ_GAIN_12
-580    0x5A3C    //TX_FDEQ_GAIN_13
-581    0x5656    //TX_FDEQ_GAIN_14
-582    0x585E    //TX_FDEQ_GAIN_15
-583    0x6698    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0201    //TX_FDEQ_BIN_0
-592    0x0105    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0509    //TX_FDEQ_BIN_7
-599    0x0E09    //TX_FDEQ_BIN_8
-600    0x150A    //TX_FDEQ_BIN_9
-601    0x071E    //TX_FDEQ_BIN_10
-602    0x152B    //TX_FDEQ_BIN_11
-603    0x0617    //TX_FDEQ_BIN_12
-604    0x3226    //TX_FDEQ_BIN_13
-605    0x190A    //TX_FDEQ_BIN_14
-606    0x0A0A    //TX_FDEQ_BIN_15
-607    0x0A0A    //TX_FDEQ_BIN_16
-608    0x0A0A    //TX_FDEQ_BIN_17
-609    0x0A0A    //TX_FDEQ_BIN_18
-610    0x0A0A    //TX_FDEQ_BIN_19
-611    0x0A0A    //TX_FDEQ_BIN_20
-612    0x0A0B    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x110C    //TX_PREEQ_BIN_MIC0_6
-648    0x0A04    //TX_PREEQ_BIN_MIC0_7
-649    0x0A0C    //TX_PREEQ_BIN_MIC0_8
-650    0x1F08    //TX_PREEQ_BIN_MIC0_9
-651    0x0808    //TX_PREEQ_BIN_MIC0_10
-652    0x0920    //TX_PREEQ_BIN_MIC0_11
-653    0x2020    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4834    //TX_PREEQ_GAIN_MIC1_12
-679    0x4838    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x5848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x1013    //TX_PREEQ_BIN_MIC1_10
-701    0x1508    //TX_PREEQ_BIN_MIC1_11
-702    0x1D0A    //TX_PREEQ_BIN_MIC1_12
-703    0x040A    //TX_PREEQ_BIN_MIC1_13
-704    0x0A21    //TX_PREEQ_BIN_MIC1_14
-705    0x2890    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0056    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0042    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0005    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
-776    0x0000    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05D3    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6B7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0400    //TX_MIN_EQ_RE_EST_0
-153    0x0400    //TX_MIN_EQ_RE_EST_1
-154    0x0800    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x1000    //TX_MIN_EQ_RE_EST_4
-157    0x1000    //TX_MIN_EQ_RE_EST_5
-158    0x1000    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x1000    //TX_MIN_EQ_RE_EST_8
-161    0x1000    //TX_MIN_EQ_RE_EST_9
-162    0x1000    //TX_MIN_EQ_RE_EST_10
-163    0x1000    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x7000    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x2000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x6000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x00C6    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x47E0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x4BD6    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x051E    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
-603    0x0F0F    //TX_FDEQ_BIN_12
-604    0x0A0F    //TX_FDEQ_BIN_13
-605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
-607    0x0C0D    //TX_FDEQ_BIN_16
-608    0x0E0F    //TX_FDEQ_BIN_17
-609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x1812    //TX_PREEQ_BIN_MIC0_0
-642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
-643    0x0808    //TX_PREEQ_BIN_MIC0_2
-644    0x080A    //TX_PREEQ_BIN_MIC0_3
-645    0x0B09    //TX_PREEQ_BIN_MIC0_4
-646    0x0A06    //TX_PREEQ_BIN_MIC0_5
-647    0x0606    //TX_PREEQ_BIN_MIC0_6
-648    0x0605    //TX_PREEQ_BIN_MIC0_7
-649    0x050A    //TX_PREEQ_BIN_MIC0_8
-650    0x1505    //TX_PREEQ_BIN_MIC0_9
-651    0x0506    //TX_PREEQ_BIN_MIC0_10
-652    0x0615    //TX_PREEQ_BIN_MIC0_11
-653    0x1516    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x2021    //TX_PREEQ_BIN_MIC0_14
-656    0x2021    //TX_PREEQ_BIN_MIC0_15
-657    0x0800    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x0909    //TX_PREEQ_BIN_MIC1_7
-698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
-704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0000    //TX_SAMPLINGFREQ_SIG
-7    0x0000    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7646    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6000    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x0040    //TX_MIN_EQ_RE_EST_0
-153    0x0040    //TX_MIN_EQ_RE_EST_1
-154    0x0040    //TX_MIN_EQ_RE_EST_2
-155    0x0040    //TX_MIN_EQ_RE_EST_3
-156    0x0040    //TX_MIN_EQ_RE_EST_4
-157    0x0040    //TX_MIN_EQ_RE_EST_5
-158    0x0040    //TX_MIN_EQ_RE_EST_6
-159    0x0040    //TX_MIN_EQ_RE_EST_7
-160    0x0040    //TX_MIN_EQ_RE_EST_8
-161    0x0040    //TX_MIN_EQ_RE_EST_9
-162    0x0040    //TX_MIN_EQ_RE_EST_10
-163    0x0040    //TX_MIN_EQ_RE_EST_11
-164    0x0040    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7B00    //TX_DTD_THR1_0
-198    0x7B00    //TX_DTD_THR1_1
-199    0x7B00    //TX_DTD_THR1_2
-200    0x7B00    //TX_DTD_THR1_3
-201    0x7B00    //TX_DTD_THR1_4
-202    0x7B00    //TX_DTD_THR1_5
-203    0x7B00    //TX_DTD_THR1_6
-204    0x1000    //TX_DTD_THR2_0
-205    0x1000    //TX_DTD_THR2_1
-206    0x1000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0FA0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xF800    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF900    //TX_THR_SN_EST_3
-246    0xF900    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x01A0    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x3000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x3000    //TX_LAMBDA_NN_EST_4
-263    0x3000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x3000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x3000    //TX_MAINREFRTOH_TH_H
-275    0x1000    //TX_MAINREFRTOH_TH_L
-276    0x3000    //TX_MAINREFRTO_TH_H
-277    0x1000    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x4000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x001B    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x0017    //TX_NS_LVL_CTRL_3
-285    0x0017    //TX_NS_LVL_CTRL_4
-286    0x0019    //TX_NS_LVL_CTRL_5
-287    0x0014    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x0010    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x0014    //TX_MIN_GAIN_S_6
-296    0x0014    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x4000    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x3000    //TX_SNRI_SUP_7
-308    0x3000    //TX_THR_LFNS
-309    0x001A    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x2000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x5000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x2000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x4000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x7FFF    //TX_B_POST_FILT_2
-325    0x5000    //TX_B_POST_FILT_3
-326    0x7FFF    //TX_B_POST_FILT_4
-327    0x7FFF    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7200    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7400    //TX_LAMBDA_PFILT_S_4
-344    0x7200    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x0C80    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0004    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0320    //TX_NOISE_TH_1
-371    0x022C    //TX_NOISE_TH_2
-372    0x2710    //TX_NOISE_TH_3
-373    0x1B58    //TX_NOISE_TH_4
-374    0x7FFF    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x0640    //TX_NOISE_TH_6
-379    0x0004    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x000A    //TX_NS_ENOISE_MIC0_TH
-406    0x0004    //TX_MINENOISE_MIC0_TH
-407    0x0014    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x0400    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x4000    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0640    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x001A    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0080    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0018    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4E    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x443A    //TX_FDEQ_GAIN_5
-573    0x3E42    //TX_FDEQ_GAIN_6
-574    0x423C    //TX_FDEQ_GAIN_7
-575    0x3434    //TX_FDEQ_GAIN_8
-576    0x3040    //TX_FDEQ_GAIN_9
-577    0x4040    //TX_FDEQ_GAIN_10
-578    0x4040    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0302    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F10    //TX_FDEQ_BIN_8
-600    0x100F    //TX_FDEQ_BIN_9
-601    0x0101    //TX_FDEQ_BIN_10
-602    0x0101    //TX_FDEQ_BIN_11
-603    0x0000    //TX_FDEQ_BIN_12
-604    0x0000    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C08    //TX_PREEQ_BIN_MIC0_2
-644    0x0700    //TX_PREEQ_BIN_MIC0_3
-645    0x0000    //TX_PREEQ_BIN_MIC0_4
-646    0x0000    //TX_PREEQ_BIN_MIC0_5
-647    0x0000    //TX_PREEQ_BIN_MIC0_6
-648    0x0000    //TX_PREEQ_BIN_MIC0_7
-649    0x0000    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x484A    //TX_PREEQ_GAIN_MIC1_8
-675    0x4C50    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D08    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
-769    0x0044    //TX_MIC_PWR_BIAS_0
-770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0003    //TX_GAIN_LIMIT_2
-776    0x0004    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0027    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0042    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0070    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x011E    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0008    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01D8    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4C50    //RX_FDEQ_GAIN_1
-41    0x5A64    //RX_FDEQ_GAIN_2
-42    0x605E    //RX_FDEQ_GAIN_3
-43    0x5C54    //RX_FDEQ_GAIN_4
-44    0x504A    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x606E    //RX_FDEQ_GAIN_7
-47    0x746C    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0204    //RX_FDEQ_BIN_0
-64    0x0101    //RX_FDEQ_BIN_1
-65    0x0205    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0105    //RX_FDEQ_BIN_4
-68    0x0A04    //RX_FDEQ_BIN_5
-69    0x070A    //RX_FDEQ_BIN_6
-70    0x070A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0B0A    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0001    //TX_SAMPLINGFREQ_SIG
-7    0x0001    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7B02    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0400    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFB00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x01A0    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x5000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x2000    //TX_MAINREFRTOH_TH_H
-275    0x1400    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0018    //TX_NS_LVL_CTRL_0
-282    0x001C    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x001C    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x001A    //TX_NS_LVL_CTRL_5
-287    0x001E    //TX_NS_LVL_CTRL_6
-288    0x001C    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0018    //TX_MIN_GAIN_S_1
-291    0x0012    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0012    //TX_MIN_GAIN_S_4
-294    0x0018    //TX_MIN_GAIN_S_5
-295    0x0018    //TX_MIN_GAIN_S_6
-296    0x0018    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
-307    0x4000    //TX_SNRI_SUP_7
-308    0x4000    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x7000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x7000    //TX_A_POST_FILT_S_5
-320    0x7000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x5000    //TX_B_POST_FILT_2
-325    0x4000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x4000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C29    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0600    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0139    //TX_NOISE_TH_1
-371    0x0479    //TX_NOISE_TH_2
-372    0x2E90    //TX_NOISE_TH_3
-373    0x4422    //TX_NOISE_TH_4
-374    0x5586    //TX_NOISE_TH_5
-375    0x4425    //TX_NOISE_TH_5_2
-376    0x0032    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x21E8    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x1000    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x05A8    //TX_SB_RHO_MEAN2_TH
-441    0x0384    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0280    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x0200    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4E50    //TX_FDEQ_GAIN_3
-571    0x4C48    //TX_FDEQ_GAIN_4
-572    0x4840    //TX_FDEQ_GAIN_5
-573    0x4850    //TX_FDEQ_GAIN_6
-574    0x5050    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4850    //TX_FDEQ_GAIN_10
-578    0x5860    //TX_FDEQ_GAIN_11
-579    0x5C60    //TX_FDEQ_GAIN_12
-580    0x6070    //TX_FDEQ_GAIN_13
-581    0x6A70    //TX_FDEQ_GAIN_14
-582    0x8490    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F0B    //TX_FDEQ_BIN_8
-600    0x190F    //TX_FDEQ_BIN_9
-601    0x1212    //TX_FDEQ_BIN_10
-602    0x0D2B    //TX_FDEQ_BIN_11
-603    0x0906    //TX_FDEQ_BIN_12
-604    0x0101    //TX_FDEQ_BIN_13
-605    0x0101    //TX_FDEQ_BIN_14
-606    0x0101    //TX_FDEQ_BIN_15
-607    0x0101    //TX_FDEQ_BIN_16
-608    0x0101    //TX_FDEQ_BIN_17
-609    0x0101    //TX_FDEQ_BIN_18
-610    0x0101    //TX_FDEQ_BIN_19
-611    0x0101    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0F09    //TX_PREEQ_BIN_MIC0_5
-647    0x0909    //TX_PREEQ_BIN_MIC0_6
-648    0x0908    //TX_PREEQ_BIN_MIC0_7
-649    0x0700    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x3448    //TX_PREEQ_GAIN_MIC1_13
-680    0x3848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0F10    //TX_PREEQ_BIN_MIC1_10
-701    0x1908    //TX_PREEQ_BIN_MIC1_11
-702    0x110C    //TX_PREEQ_BIN_MIC1_12
-703    0x0C02    //TX_PREEQ_BIN_MIC1_13
-704    0x0A00    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0004    //TX_GAIN_LIMIT_2
-776    0x0003    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05F5    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x199A    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x2000    //TX_B_LESSCUT_RTO_MASK
-877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0001    //RX_SAMPLINGFREQ_SIG
-3    0x0001    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x1000    //RX_LMT_THRD
-37    0x7FDF    //RX_LMT_ALPHA
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4C57    //RX_FDEQ_GAIN_2
-42    0x5959    //RX_FDEQ_GAIN_3
-43    0x5753    //RX_FDEQ_GAIN_4
-44    0x5359    //RX_FDEQ_GAIN_5
-45    0x616D    //RX_FDEQ_GAIN_6
-46    0x7983    //RX_FDEQ_GAIN_7
-47    0x897E    //RX_FDEQ_GAIN_8
-48    0x665D    //RX_FDEQ_GAIN_9
-49    0x564E    //RX_FDEQ_GAIN_10
-50    0x4855    //RX_FDEQ_GAIN_11
-51    0x555D    //RX_FDEQ_GAIN_12
-52    0x6598    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x001A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0049    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x007A    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00C4    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x013B    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x515F    //RX_FDEQ_GAIN_2
-42    0x5F5F    //RX_FDEQ_GAIN_3
-43    0x5D59    //RX_FDEQ_GAIN_4
-44    0x595F    //RX_FDEQ_GAIN_5
-45    0x656F    //RX_FDEQ_GAIN_6
-46    0x7D87    //RX_FDEQ_GAIN_7
-47    0x8C80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0008    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01F9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4E5C    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5A56    //RX_FDEQ_GAIN_4
-44    0x565C    //RX_FDEQ_GAIN_5
-45    0x626C    //RX_FDEQ_GAIN_6
-46    0x7A84    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x665E    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x404C    //RX_FDEQ_GAIN_11
-51    0x5658    //RX_FDEQ_GAIN_12
-52    0x5C98    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x080A    //RX_FDEQ_BIN_7
-71    0x0E0A    //RX_FDEQ_BIN_8
-72    0x0C14    //RX_FDEQ_BIN_9
-73    0x090A    //RX_FDEQ_BIN_10
-74    0x0E06    //RX_FDEQ_BIN_11
-75    0x0A21    //RX_FDEQ_BIN_12
-76    0x1118    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0003    //TX_SAMPLINGFREQ_SIG
-7    0x0003    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0100    //TX_MIN_EQ_RE_EST_11
-164    0x0100    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x002C    //TX_NS_LVL_CTRL_2
-284    0x0020    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x2000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x0190    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5DC0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x5DC0    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x02F0    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x984E    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4C    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4240    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4840    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4E4C    //TX_FDEQ_GAIN_10
-578    0x5A60    //TX_FDEQ_GAIN_11
-579    0x6262    //TX_FDEQ_GAIN_12
-580    0x5A3C    //TX_FDEQ_GAIN_13
-581    0x5656    //TX_FDEQ_GAIN_14
-582    0x585E    //TX_FDEQ_GAIN_15
-583    0x6698    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0201    //TX_FDEQ_BIN_0
-592    0x0105    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0509    //TX_FDEQ_BIN_7
-599    0x0E09    //TX_FDEQ_BIN_8
-600    0x150A    //TX_FDEQ_BIN_9
-601    0x071E    //TX_FDEQ_BIN_10
-602    0x152B    //TX_FDEQ_BIN_11
-603    0x0617    //TX_FDEQ_BIN_12
-604    0x3226    //TX_FDEQ_BIN_13
-605    0x190A    //TX_FDEQ_BIN_14
-606    0x0A0A    //TX_FDEQ_BIN_15
-607    0x0A0A    //TX_FDEQ_BIN_16
-608    0x0A0A    //TX_FDEQ_BIN_17
-609    0x0A0A    //TX_FDEQ_BIN_18
-610    0x0A0A    //TX_FDEQ_BIN_19
-611    0x0A0A    //TX_FDEQ_BIN_20
-612    0x0A0B    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x110C    //TX_PREEQ_BIN_MIC0_6
-648    0x0A04    //TX_PREEQ_BIN_MIC0_7
-649    0x0A0C    //TX_PREEQ_BIN_MIC0_8
-650    0x1F08    //TX_PREEQ_BIN_MIC0_9
-651    0x0808    //TX_PREEQ_BIN_MIC0_10
-652    0x0920    //TX_PREEQ_BIN_MIC0_11
-653    0x2020    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4834    //TX_PREEQ_GAIN_MIC1_12
-679    0x4838    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x5848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x1013    //TX_PREEQ_BIN_MIC1_10
-701    0x1508    //TX_PREEQ_BIN_MIC1_11
-702    0x1D0A    //TX_PREEQ_BIN_MIC1_12
-703    0x040A    //TX_PREEQ_BIN_MIC1_13
-704    0x0A21    //TX_PREEQ_BIN_MIC1_14
-705    0x2890    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0056    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0042    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0005    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
-776    0x0000    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05D3    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x047C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0003    //RX_SAMPLINGFREQ_SIG
-3    0x0003    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x5800    //RX_THR_PITCH_DET_0
-14    0x5000    //RX_THR_PITCH_DET_1
-15    0x4000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x1B00    //RX_TPKA_FP
-127    0x0300    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0017    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0028    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0044    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x006F    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00B0    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x011C    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484E    //RX_FDEQ_GAIN_1
-41    0x5658    //RX_FDEQ_GAIN_2
-42    0x565A    //RX_FDEQ_GAIN_3
-43    0x5C50    //RX_FDEQ_GAIN_4
-44    0x525E    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4644    //RX_FDEQ_GAIN_17
-57    0x445A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0504    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01D9    //RX_TDDRC_DRC_GAIN
-38    0x002A    //RX_FDEQ_SUBNUM
-39    0x9848    //RX_FDEQ_GAIN_0
-40    0x484C    //RX_FDEQ_GAIN_1
-41    0x5458    //RX_FDEQ_GAIN_2
-42    0x5658    //RX_FDEQ_GAIN_3
-43    0x5452    //RX_FDEQ_GAIN_4
-44    0x525A    //RX_FDEQ_GAIN_5
-45    0x6068    //RX_FDEQ_GAIN_6
-46    0x7480    //RX_FDEQ_GAIN_7
-47    0x8A80    //RX_FDEQ_GAIN_8
-48    0x6E62    //RX_FDEQ_GAIN_9
-49    0x6A4A    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x5656    //RX_FDEQ_GAIN_12
-52    0x5866    //RX_FDEQ_GAIN_13
-53    0x7878    //RX_FDEQ_GAIN_14
-54    0x584C    //RX_FDEQ_GAIN_15
-55    0x4C4C    //RX_FDEQ_GAIN_16
-56    0x4A4A    //RX_FDEQ_GAIN_17
-57    0x585A    //RX_FDEQ_GAIN_18
-58    0x5A98    //RX_FDEQ_GAIN_19
-59    0x9898    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0402    //RX_FDEQ_BIN_1
-65    0x0103    //RX_FDEQ_BIN_2
-66    0x0404    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x0806    //RX_FDEQ_BIN_7
-71    0x120A    //RX_FDEQ_BIN_8
-72    0x0C0C    //RX_FDEQ_BIN_9
-73    0x110C    //RX_FDEQ_BIN_10
-74    0x0E14    //RX_FDEQ_BIN_11
-75    0x0E0D    //RX_FDEQ_BIN_12
-76    0x110A    //RX_FDEQ_BIN_13
-77    0x1414    //RX_FDEQ_BIN_14
-78    0x1214    //RX_FDEQ_BIN_15
-79    0x1414    //RX_FDEQ_BIN_16
-80    0x141E    //RX_FDEQ_BIN_17
-81    0x0214    //RX_FDEQ_BIN_18
-82    0x1414    //RX_FDEQ_BIN_19
-83    0x1414    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET-TMOBILE_US-FB
-#PARAM_TYPE TX+RX
-#TOTAL_CUSTOM_STEP 7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6B7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7900    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0400    //TX_MIN_EQ_RE_EST_0
-153    0x0400    //TX_MIN_EQ_RE_EST_1
-154    0x0800    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x1000    //TX_MIN_EQ_RE_EST_4
-157    0x1000    //TX_MIN_EQ_RE_EST_5
-158    0x1000    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x1000    //TX_MIN_EQ_RE_EST_8
-161    0x1000    //TX_MIN_EQ_RE_EST_9
-162    0x1000    //TX_MIN_EQ_RE_EST_10
-163    0x1000    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x1800    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
-212    0x0177    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0C00    //TX_RATIO_DT_L_TH_LOW
-224    0x2000    //TX_RATIO_DT_H_TH_LOW
-225    0x1800    //TX_RATIO_DT_L_TH_HIGH
-226    0x3000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x7000    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xF800    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x1000    //TX_MAINREFRTOH_TH_H
-275    0x0600    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x2000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
-288    0x0017    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
-296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x6000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
-307    0x6000    //TX_SNRI_SUP_7
-308    0x6000    //TX_THR_LFNS
-309    0x0017    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
-329    0x3000    //TX_B_POST_FILT_7
-330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x07D0    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x00C6    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x47E0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x4BD6    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x0200    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x051E    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0300    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
-603    0x0F0F    //TX_FDEQ_BIN_12
-604    0x0A0F    //TX_FDEQ_BIN_13
-605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
-607    0x0C0D    //TX_FDEQ_BIN_16
-608    0x0E0F    //TX_FDEQ_BIN_17
-609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x1812    //TX_PREEQ_BIN_MIC0_0
-642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
-643    0x0808    //TX_PREEQ_BIN_MIC0_2
-644    0x080A    //TX_PREEQ_BIN_MIC0_3
-645    0x0B09    //TX_PREEQ_BIN_MIC0_4
-646    0x0A06    //TX_PREEQ_BIN_MIC0_5
-647    0x0606    //TX_PREEQ_BIN_MIC0_6
-648    0x0605    //TX_PREEQ_BIN_MIC0_7
-649    0x050A    //TX_PREEQ_BIN_MIC0_8
-650    0x1505    //TX_PREEQ_BIN_MIC0_9
-651    0x0506    //TX_PREEQ_BIN_MIC0_10
-652    0x0615    //TX_PREEQ_BIN_MIC0_11
-653    0x1516    //TX_PREEQ_BIN_MIC0_12
-654    0x2021    //TX_PREEQ_BIN_MIC0_13
-655    0x2021    //TX_PREEQ_BIN_MIC0_14
-656    0x2021    //TX_PREEQ_BIN_MIC0_15
-657    0x0800    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x0909    //TX_PREEQ_BIN_MIC1_7
-698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
-704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0xECCD    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x003C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -25453,11 +25007,11 @@
 3    0x0004    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
+10    0x0722    //RX_PGA
 11    0x7FFF    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x5800    //RX_THR_PITCH_DET_0
@@ -25472,36 +25026,36 @@
 22    0x000F    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -25510,22 +25064,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -25558,25 +25112,25 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0001    //RX_FILTINDX
+111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x02FD    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
 126    0x2000    //RX_TPKA_FP
 127    0x2000    //RX_MIN_G_FP
 128    0x0080    //RX_MAX_G_FP
-129    0x0099    //RX_SPK_VOL
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -25605,1656 +25159,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0037    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x1300    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x5A56    //RX_FDEQ_GAIN_2
-42    0x5454    //RX_FDEQ_GAIN_3
-43    0x4E4E    //RX_FDEQ_GAIN_4
-44    0x565E    //RX_FDEQ_GAIN_5
-45    0x6874    //RX_FDEQ_GAIN_6
-46    0x808A    //RX_FDEQ_GAIN_7
-47    0x806A    //RX_FDEQ_GAIN_8
-48    0x5E66    //RX_FDEQ_GAIN_9
-49    0x4E3E    //RX_FDEQ_GAIN_10
-50    0x4852    //RX_FDEQ_GAIN_11
-51    0x5460    //RX_FDEQ_GAIN_12
-52    0x6A5E    //RX_FDEQ_GAIN_13
-53    0x5460    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0103    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0102    //RX_FDEQ_BIN_2
-66    0x0203    //RX_FDEQ_BIN_3
-67    0x0207    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x040C    //RX_FDEQ_BIN_7
-71    0x0708    //RX_FDEQ_BIN_8
-72    0x080B    //RX_FDEQ_BIN_9
-73    0x0909    //RX_FDEQ_BIN_10
-74    0x0D12    //RX_FDEQ_BIN_11
-75    0x0C06    //RX_FDEQ_BIN_12
-76    0x1B0C    //RX_FDEQ_BIN_13
-77    0x491C    //RX_FDEQ_BIN_14
-78    0x06CC    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0000    //TX_SAMPLINGFREQ_SIG
-7    0x0000    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7646    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6000    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x0040    //TX_MIN_EQ_RE_EST_0
-153    0x0040    //TX_MIN_EQ_RE_EST_1
-154    0x0040    //TX_MIN_EQ_RE_EST_2
-155    0x0040    //TX_MIN_EQ_RE_EST_3
-156    0x0040    //TX_MIN_EQ_RE_EST_4
-157    0x0040    //TX_MIN_EQ_RE_EST_5
-158    0x0040    //TX_MIN_EQ_RE_EST_6
-159    0x0040    //TX_MIN_EQ_RE_EST_7
-160    0x0040    //TX_MIN_EQ_RE_EST_8
-161    0x0040    //TX_MIN_EQ_RE_EST_9
-162    0x0040    //TX_MIN_EQ_RE_EST_10
-163    0x0040    //TX_MIN_EQ_RE_EST_11
-164    0x0040    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7B00    //TX_DTD_THR1_0
-198    0x7B00    //TX_DTD_THR1_1
-199    0x7B00    //TX_DTD_THR1_2
-200    0x7B00    //TX_DTD_THR1_3
-201    0x7B00    //TX_DTD_THR1_4
-202    0x7B00    //TX_DTD_THR1_5
-203    0x7B00    //TX_DTD_THR1_6
-204    0x1000    //TX_DTD_THR2_0
-205    0x1000    //TX_DTD_THR2_1
-206    0x1000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0FA0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xF800    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF900    //TX_THR_SN_EST_3
-246    0xF900    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x01A0    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x3000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x3000    //TX_LAMBDA_NN_EST_4
-263    0x3000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x3000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x3000    //TX_MAINREFRTOH_TH_H
-275    0x1000    //TX_MAINREFRTOH_TH_L
-276    0x3000    //TX_MAINREFRTO_TH_H
-277    0x1000    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x4000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x001B    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x0017    //TX_NS_LVL_CTRL_3
-285    0x0017    //TX_NS_LVL_CTRL_4
-286    0x0019    //TX_NS_LVL_CTRL_5
-287    0x0014    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x0010    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x0014    //TX_MIN_GAIN_S_6
-296    0x0014    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x4000    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x3000    //TX_SNRI_SUP_7
-308    0x3000    //TX_THR_LFNS
-309    0x001A    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x2000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x5000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x2000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x4000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x7FFF    //TX_B_POST_FILT_2
-325    0x5000    //TX_B_POST_FILT_3
-326    0x7FFF    //TX_B_POST_FILT_4
-327    0x7FFF    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7200    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7400    //TX_LAMBDA_PFILT_S_4
-344    0x7200    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x0C80    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0004    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0320    //TX_NOISE_TH_1
-371    0x022C    //TX_NOISE_TH_2
-372    0x2710    //TX_NOISE_TH_3
-373    0x1B58    //TX_NOISE_TH_4
-374    0x7FFF    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x0640    //TX_NOISE_TH_6
-379    0x0004    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x000A    //TX_NS_ENOISE_MIC0_TH
-406    0x0004    //TX_MINENOISE_MIC0_TH
-407    0x0014    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x0400    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x4000    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0990    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0640    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x001A    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0080    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0018    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4E    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x443A    //TX_FDEQ_GAIN_5
-573    0x3E42    //TX_FDEQ_GAIN_6
-574    0x423C    //TX_FDEQ_GAIN_7
-575    0x3434    //TX_FDEQ_GAIN_8
-576    0x3040    //TX_FDEQ_GAIN_9
-577    0x4040    //TX_FDEQ_GAIN_10
-578    0x4040    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0302    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F10    //TX_FDEQ_BIN_8
-600    0x100F    //TX_FDEQ_BIN_9
-601    0x0101    //TX_FDEQ_BIN_10
-602    0x0101    //TX_FDEQ_BIN_11
-603    0x0000    //TX_FDEQ_BIN_12
-604    0x0000    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C08    //TX_PREEQ_BIN_MIC0_2
-644    0x0700    //TX_PREEQ_BIN_MIC0_3
-645    0x0000    //TX_PREEQ_BIN_MIC0_4
-646    0x0000    //TX_PREEQ_BIN_MIC0_5
-647    0x0000    //TX_PREEQ_BIN_MIC0_6
-648    0x0000    //TX_PREEQ_BIN_MIC0_7
-649    0x0000    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x484A    //TX_PREEQ_GAIN_MIC1_8
-675    0x4C50    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D08    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
-769    0x0044    //TX_MIC_PWR_BIAS_0
-770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0003    //TX_GAIN_LIMIT_2
-776    0x0004    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -27264,21 +25208,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -27311,2508 +25255,1464 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0016    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0059    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0090    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0722    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0016    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0059    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C48    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0303    //RX_FDEQ_BIN_3
-67    0x0303    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0303    //RX_FDEQ_BIN_6
-70    0x0303    //RX_FDEQ_BIN_7
-71    0x0A0A    //RX_FDEQ_BIN_8
-72    0x0A0E    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
-#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#CASE_NAME  HANDSET-HANDSET-CUSTOM2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0000    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
-2    0x0036    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0002    //TX_NUM_MIC
-6    0x0001    //TX_SAMPLINGFREQ_SIG
-7    0x0001    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x1000    //TX_PGA_0
-28    0x1000    //TX_PGA_1
-29    0x1000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0002    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3A66    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0AAC    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7B02    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0800    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0400    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x1000    //TX_LAMBDA_CB_NLE
-167    0x0400    //TX_C_POST_FLT
-168    0x4000    //TX_GAIN_NP
-169    0x003C    //TX_SE_HOLD_N
-170    0x0046    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
-200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
-202    0x7F00    //TX_DTD_THR1_5
-203    0x7F00    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x1000    //TX_DTD_THR2_3
-208    0x1000    //TX_DTD_THR2_4
-209    0x1000    //TX_DTD_THR2_5
-210    0x1000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x1B58    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0000    //TX_RATIO_DT_L_TH_LOW
-224    0x0000    //TX_RATIO_DT_H_TH_LOW
-225    0x0000    //TX_RATIO_DT_L_TH_HIGH
-226    0x0000    //TX_RATIO_DT_H_TH_HIGH
-227    0x0000    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
-233    0x0000    //TX_EPD_OFFST_01
-234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF600    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFB00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF800    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF700    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x01A0    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x5000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x0000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x1000    //TX_NE_RTO_TH_L
-274    0x2000    //TX_MAINREFRTOH_TH_H
-275    0x1400    //TX_MAINREFRTOH_TH_L
-276    0x2000    //TX_MAINREFRTO_TH_H
-277    0x1400    //TX_MAINREFRTO_TH_L
-278    0x0000    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x4000    //TX_B_POST_FLT_1
-281    0x0018    //TX_NS_LVL_CTRL_0
-282    0x001C    //TX_NS_LVL_CTRL_1
-283    0x0019    //TX_NS_LVL_CTRL_2
-284    0x001C    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x001A    //TX_NS_LVL_CTRL_5
-287    0x001E    //TX_NS_LVL_CTRL_6
-288    0x001C    //TX_NS_LVL_CTRL_7
-289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0018    //TX_MIN_GAIN_S_1
-291    0x0012    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0012    //TX_MIN_GAIN_S_4
-294    0x0018    //TX_MIN_GAIN_S_5
-295    0x0018    //TX_MIN_GAIN_S_6
-296    0x0018    //TX_MIN_GAIN_S_7
-297    0x5000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
-307    0x4000    //TX_SNRI_SUP_7
-308    0x4000    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x7000    //TX_A_POST_FILT_S_0
-315    0x7000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x2000    //TX_A_POST_FILT_S_4
-319    0x7000    //TX_A_POST_FILT_S_5
-320    0x7000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x4000    //TX_B_POST_FILT_1
-324    0x5000    //TX_B_POST_FILT_2
-325    0x4000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x4000    //TX_B_POST_FILT_6
-329    0x4000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C29    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0600    //TX_A_PEPPER
-349    0x1D4C    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0000    //TX_DT_BINVAD_ENDF
-358    0x1000    //TX_C_POST_FLT_DT
-359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x0139    //TX_NOISE_TH_1
-371    0x0479    //TX_NOISE_TH_2
-372    0x2E90    //TX_NOISE_TH_3
-373    0x4422    //TX_NOISE_TH_4
-374    0x5586    //TX_NOISE_TH_5
-375    0x4425    //TX_NOISE_TH_5_2
-376    0x0032    //TX_NOISE_TH_5_3
-377    0x4E20    //TX_NOISE_TH_5_4
-378    0x21E8    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x4900    //TX_MIN_G_CTRL_SSNS
-409    0x1000    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x2328    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x03E8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2800    //TX_BF_RESET_THR_HS
-424    0x0CCD    //TX_SB_RTO_MEAN_TH
-425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0100    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x05A8    //TX_SB_RHO_MEAN2_TH
-441    0x0384    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x0001    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0280    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x0200    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x7FFF    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0010    //TX_WIND_SUPRTO
-540    0x0014    //TX_WNS_MIN_G
-541    0x0600    //TX_WNS_B_POST_FLT
-542    0x3000    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0200    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x9854    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4E50    //TX_FDEQ_GAIN_3
-571    0x4C48    //TX_FDEQ_GAIN_4
-572    0x4840    //TX_FDEQ_GAIN_5
-573    0x4850    //TX_FDEQ_GAIN_6
-574    0x5050    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4850    //TX_FDEQ_GAIN_10
-578    0x5860    //TX_FDEQ_GAIN_11
-579    0x5C60    //TX_FDEQ_GAIN_12
-580    0x6070    //TX_FDEQ_GAIN_13
-581    0x6A70    //TX_FDEQ_GAIN_14
-582    0x8490    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0104    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0506    //TX_FDEQ_BIN_7
-599    0x0F0B    //TX_FDEQ_BIN_8
-600    0x190F    //TX_FDEQ_BIN_9
-601    0x1212    //TX_FDEQ_BIN_10
-602    0x0D2B    //TX_FDEQ_BIN_11
-603    0x0906    //TX_FDEQ_BIN_12
-604    0x0101    //TX_FDEQ_BIN_13
-605    0x0101    //TX_FDEQ_BIN_14
-606    0x0101    //TX_FDEQ_BIN_15
-607    0x0101    //TX_FDEQ_BIN_16
-608    0x0101    //TX_FDEQ_BIN_17
-609    0x0101    //TX_FDEQ_BIN_18
-610    0x0101    //TX_FDEQ_BIN_19
-611    0x0101    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0030    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
-643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
-644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
-645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0F09    //TX_PREEQ_BIN_MIC0_5
-647    0x0909    //TX_PREEQ_BIN_MIC0_6
-648    0x0908    //TX_PREEQ_BIN_MIC0_7
-649    0x0700    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x3448    //TX_PREEQ_GAIN_MIC1_13
-680    0x3848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
-693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
-695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
-697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0F10    //TX_PREEQ_BIN_MIC1_10
-701    0x1908    //TX_PREEQ_BIN_MIC1_11
-702    0x110C    //TX_PREEQ_BIN_MIC1_12
-703    0x0C02    //TX_PREEQ_BIN_MIC1_13
-704    0x0A00    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0030    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0000    //TX_GAIN_LIMIT_1
-775    0x0004    //TX_GAIN_LIMIT_2
-776    0x0003    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x0FA0    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05F5    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x199A    //TX_TFMASKLTH_BINVAD
-873    0xFCCD    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x2000    //TX_B_LESSCUT_RTO_MASK
-877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x6333    //TX_GAIN_WIND_MASK
-881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x014A    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4A4C    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5A5C    //RX_FDEQ_GAIN_7
-47    0x5C5C    //RX_FDEQ_GAIN_8
-48    0x5C5C    //RX_FDEQ_GAIN_9
-49    0x5C5C    //RX_FDEQ_GAIN_10
-50    0x5C5C    //RX_FDEQ_GAIN_11
-51    0x5C5C    //RX_FDEQ_GAIN_12
-52    0x5C5C    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0505    //RX_FDEQ_BIN_4
-68    0x0505    //RX_FDEQ_BIN_5
-69    0x0505    //RX_FDEQ_BIN_6
-70    0x0505    //RX_FDEQ_BIN_7
-71    0x160C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0000    //TX_OPERATION_MODE_0
-1    0x0000    //TX_OPERATION_MODE_1
-2    0x0026    //TX_PATCH_REG
-3    0x6F7E    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F5F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0002    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
 7    0x0003    //TX_SAMPLINGFREQ_PROC
@@ -29829,7 +26729,7 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
+21    0x009C    //TX_DIST2REF1
 22    0x0000    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
@@ -29960,19 +26860,19 @@
 149    0x0800    //TX_AEC_REF_GAIN_2
 150    0x7900    //TX_EAD_THR
 151    0x2000    //TX_THR_RE_EST
-152    0x0100    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0100    //TX_MIN_EQ_RE_EST_2
-155    0x0100    //TX_MIN_EQ_RE_EST_3
-156    0x0100    //TX_MIN_EQ_RE_EST_4
-157    0x0100    //TX_MIN_EQ_RE_EST_5
-158    0x0100    //TX_MIN_EQ_RE_EST_6
-159    0x0100    //TX_MIN_EQ_RE_EST_7
-160    0x0100    //TX_MIN_EQ_RE_EST_8
-161    0x0100    //TX_MIN_EQ_RE_EST_9
-162    0x0100    //TX_MIN_EQ_RE_EST_10
-163    0x0100    //TX_MIN_EQ_RE_EST_11
-164    0x0100    //TX_MIN_EQ_RE_EST_12
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
 165    0x3000    //TX_LAMBDA_RE_EST
 166    0x1000    //TX_LAMBDA_CB_NLE
 167    0x1800    //TX_C_POST_FLT
@@ -30005,11 +26905,11 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7000    //TX_DTD_THR1_2
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
 200    0x7F00    //TX_DTD_THR1_3
-201    0x7F00    //TX_DTD_THR1_4
+201    0x7000    //TX_DTD_THR1_4
 202    0x7F00    //TX_DTD_THR1_5
 203    0x7F00    //TX_DTD_THR1_6
 204    0x2000    //TX_DTD_THR2_0
@@ -30019,7 +26919,7 @@
 208    0x1000    //TX_DTD_THR2_4
 209    0x1000    //TX_DTD_THR2_5
 210    0x1000    //TX_DTD_THR2_6
-211    0x6000    //TX_DTD_THR3
+211    0x7FF0    //TX_DTD_THR3
 212    0x0177    //TX_SPK_CUT_K
 213    0x1B58    //TX_DT_CUT_K
 214    0x0100    //TX_DT_CUT_THR
@@ -30036,8 +26936,8 @@
 225    0x1800    //TX_RATIO_DT_L_TH_HIGH
 226    0x3000    //TX_RATIO_DT_H_TH_HIGH
 227    0x0A00    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x0800    //TX_B_POST_FILT_ECHO_H
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
@@ -30053,18 +26953,18 @@
 242    0xF600    //TX_THR_SN_EST_0
 243    0xFA00    //TX_THR_SN_EST_1
 244    0xFA00    //TX_THR_SN_EST_2
-245    0xF800    //TX_THR_SN_EST_3
+245    0xFC00    //TX_THR_SN_EST_3
 246    0xF800    //TX_THR_SN_EST_4
 247    0xF800    //TX_THR_SN_EST_5
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF700    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -30090,31 +26990,31 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0014    //TX_NS_LVL_CTRL_0
-282    0x0016    //TX_NS_LVL_CTRL_1
-283    0x002C    //TX_NS_LVL_CTRL_2
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
 284    0x0020    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
 288    0x0017    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
 294    0x0012    //TX_MIN_GAIN_S_5
-295    0x0012    //TX_MIN_GAIN_S_6
+295    0x0018    //TX_MIN_GAIN_S_6
 296    0x0012    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
+297    0x5000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x2000    //TX_SNRI_SUP_1
 302    0x2000    //TX_SNRI_SUP_2
-303    0x6000    //TX_SNRI_SUP_3
+303    0x1000    //TX_SNRI_SUP_3
 304    0x6000    //TX_SNRI_SUP_4
 305    0x6000    //TX_SNRI_SUP_5
-306    0x6000    //TX_SNRI_SUP_6
+306    0x1000    //TX_SNRI_SUP_6
 307    0x6000    //TX_SNRI_SUP_7
 308    0x6000    //TX_THR_LFNS
 309    0x0017    //TX_G_LFNS
@@ -30123,34 +27023,34 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x4000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
 329    0x3000    //TX_B_POST_FILT_7
 330    0x1000    //TX_B_LESSCUT_RTO_S_0
 331    0x6000    //TX_B_LESSCUT_RTO_S_1
 332    0x6000    //TX_B_LESSCUT_RTO_S_2
 333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
 343    0x7C29    //TX_LAMBDA_PFILT_S_4
 344    0x7C29    //TX_LAMBDA_PFILT_S_5
 345    0x7C29    //TX_LAMBDA_PFILT_S_6
@@ -30178,20 +27078,20 @@
 367    0x000A    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x0190    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5DC0    //TX_NOISE_TH_4
-374    0x57E4    //TX_NOISE_TH_5
-375    0x5DC0    //TX_NOISE_TH_5_2
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0001    //TX_NOISE_TH_5_3
 377    0x4E20    //TX_NOISE_TH_5_4
-378    0x39DF    //TX_NOISE_TH_6
+378    0x2EE0    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -30199,15 +27099,15 @@
 388    0x0200    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -30217,8 +27117,8 @@
 406    0x0014    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x0FA0    //TX_NS_FP_K_METAL
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
 411    0x3A98    //TX_NOISEDET_BOOST_TH
 412    0x0FA0    //TX_NSMOOTH_TH
 413    0x0000    //TX_NS_RESRV_8
@@ -30248,8 +27148,8 @@
 437    0x0032    //TX_SILENCE_T
 438    0x0000    //TX_A_POST_FLT_WTA
 439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x051E    //TX_SB_RHO_MEAN2_TH
-441    0x02F0    //TX_SB_RHO_MEAN3_TH
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
 442    0x0000    //TX_HS_RESRV_4
 443    0x0000    //TX_HS_RESRV_5
 444    0x0001    //TX_DOA_VAD_THR_1
@@ -30317,21 +27217,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -30360,69 +27260,69 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x0030    //TX_FDEQ_SUBNUM
-567    0x984E    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4A4C    //TX_FDEQ_GAIN_2
-570    0x4C4C    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4240    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4840    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4E4C    //TX_FDEQ_GAIN_10
-578    0x5A60    //TX_FDEQ_GAIN_11
-579    0x6262    //TX_FDEQ_GAIN_12
-580    0x5A3C    //TX_FDEQ_GAIN_13
-581    0x5656    //TX_FDEQ_GAIN_14
-582    0x585E    //TX_FDEQ_GAIN_15
-583    0x6698    //TX_FDEQ_GAIN_16
-584    0x9898    //TX_FDEQ_GAIN_17
-585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
 589    0x4848    //TX_FDEQ_GAIN_22
 590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0201    //TX_FDEQ_BIN_0
-592    0x0105    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
 594    0x0202    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0706    //TX_FDEQ_BIN_5
-597    0x0501    //TX_FDEQ_BIN_6
-598    0x0509    //TX_FDEQ_BIN_7
-599    0x0E09    //TX_FDEQ_BIN_8
-600    0x150A    //TX_FDEQ_BIN_9
-601    0x071E    //TX_FDEQ_BIN_10
-602    0x152B    //TX_FDEQ_BIN_11
-603    0x0617    //TX_FDEQ_BIN_12
-604    0x3226    //TX_FDEQ_BIN_13
-605    0x190A    //TX_FDEQ_BIN_14
-606    0x0A0A    //TX_FDEQ_BIN_15
-607    0x0A0A    //TX_FDEQ_BIN_16
-608    0x0A0A    //TX_FDEQ_BIN_17
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
 609    0x0A0A    //TX_FDEQ_BIN_18
 610    0x0A0A    //TX_FDEQ_BIN_19
 611    0x0A0A    //TX_FDEQ_BIN_20
-612    0x0A0B    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
 616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
@@ -30449,16 +27349,16 @@
 638    0x4848    //TX_PREEQ_GAIN_MIC0_21
 639    0x4848    //TX_PREEQ_GAIN_MIC0_22
 640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x251A    //TX_PREEQ_BIN_MIC0_0
-642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
 643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
 644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
 645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x110C    //TX_PREEQ_BIN_MIC0_6
-648    0x0A04    //TX_PREEQ_BIN_MIC0_7
-649    0x0A0C    //TX_PREEQ_BIN_MIC0_8
-650    0x1F08    //TX_PREEQ_BIN_MIC0_9
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
 651    0x0808    //TX_PREEQ_BIN_MIC0_10
 652    0x0920    //TX_PREEQ_BIN_MIC0_11
 653    0x2020    //TX_PREEQ_BIN_MIC0_12
@@ -30476,20 +27376,20 @@
 665    0x0030    //TX_PREEQ_SUBNUM_MIC1
 666    0x4848    //TX_PREEQ_GAIN_MIC1_0
 667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
 673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
 675    0x4848    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4834    //TX_PREEQ_GAIN_MIC1_11
-678    0x4834    //TX_PREEQ_GAIN_MIC1_12
-679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
 680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x5848    //TX_PREEQ_GAIN_MIC1_15
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
 684    0x4848    //TX_PREEQ_GAIN_MIC1_18
@@ -30499,21 +27399,21 @@
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
 690    0x0202    //TX_PREEQ_BIN_MIC1_0
-691    0x0203    //TX_PREEQ_BIN_MIC1_1
-692    0x0303    //TX_PREEQ_BIN_MIC1_2
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
 693    0x0304    //TX_PREEQ_BIN_MIC1_3
-694    0x0405    //TX_PREEQ_BIN_MIC1_4
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
 695    0x0506    //TX_PREEQ_BIN_MIC1_5
-696    0x0708    //TX_PREEQ_BIN_MIC1_6
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
 697    0x090A    //TX_PREEQ_BIN_MIC1_7
-698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
-699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
-700    0x1013    //TX_PREEQ_BIN_MIC1_10
-701    0x1508    //TX_PREEQ_BIN_MIC1_11
-702    0x1D0A    //TX_PREEQ_BIN_MIC1_12
-703    0x040A    //TX_PREEQ_BIN_MIC1_13
-704    0x0A21    //TX_PREEQ_BIN_MIC1_14
-705    0x2890    //TX_PREEQ_BIN_MIC1_15
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
@@ -30573,16 +27473,16 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0056    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0042    //TX_MIC_PWR_BIAS_1
+770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
-774    0x0005    //TX_GAIN_LIMIT_1
+774    0x0004    //TX_GAIN_LIMIT_1
 775    0x0000    //TX_GAIN_LIMIT_2
 776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
@@ -30591,14 +27491,14 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
 784    0x6000    //TX_TDDRC_ALPHA_UP_02
 785    0x6000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
 788    0x6000    //TX_TDDRC_ALPHA_DWN_02
 789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
 791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
@@ -30624,8 +27524,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -30662,19 +27562,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0730    //TX_TDDRC_THRD_2
-857    0x1C00    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05D3    //TX_TDDRC_DRC_GAIN
+866    0x098D    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -30699,22 +27599,87 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
 11    0x7FFF    //RX_A_HP
@@ -30728,39 +27693,39 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
+22    0x000A    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -30770,21 +27735,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
 72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -30817,24 +27782,24 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
+111    0x0002    //RX_FILTINDX
 112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
+124    0x0551    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
@@ -30864,46 +27829,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x042B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -30912,22 +27877,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -30960,49 +27925,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x000D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31011,22 +27976,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31059,49 +28024,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0015    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0438    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31110,22 +28075,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31158,49 +28123,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0024    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31209,22 +28174,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31257,49 +28222,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x003B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31308,22 +28273,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31356,49 +28321,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x005F    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31407,22 +28372,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31455,49 +28420,49 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x009A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7000    //RX_TDDRC_LIMITER_THRD
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0005    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x016B    //RX_TDDRC_DRC_GAIN
-38    0x0030    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4844    //RX_FDEQ_GAIN_2
-42    0x4B4D    //RX_FDEQ_GAIN_3
-43    0x4E50    //RX_FDEQ_GAIN_4
-44    0x5254    //RX_FDEQ_GAIN_5
-45    0x5658    //RX_FDEQ_GAIN_6
-46    0x5C60    //RX_FDEQ_GAIN_7
-47    0x6468    //RX_FDEQ_GAIN_8
-48    0x6C70    //RX_FDEQ_GAIN_9
-49    0x7474    //RX_FDEQ_GAIN_10
-50    0x7474    //RX_FDEQ_GAIN_11
-51    0x7474    //RX_FDEQ_GAIN_12
-52    0x7474    //RX_FDEQ_GAIN_13
-53    0x7474    //RX_FDEQ_GAIN_14
-54    0x7474    //RX_FDEQ_GAIN_15
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705C    //RX_FDEQ_GAIN_0
+40    0x6E7E    //RX_FDEQ_GAIN_1
+41    0x808E    //RX_FDEQ_GAIN_2
+42    0x8472    //RX_FDEQ_GAIN_3
+43    0x7476    //RX_FDEQ_GAIN_4
+44    0x7278    //RX_FDEQ_GAIN_5
+45    0x8092    //RX_FDEQ_GAIN_6
+46    0xA4A2    //RX_FDEQ_GAIN_7
+47    0xB49C    //RX_FDEQ_GAIN_8
+48    0x8E7C    //RX_FDEQ_GAIN_9
+49    0x8664    //RX_FDEQ_GAIN_10
+50    0x5A78    //RX_FDEQ_GAIN_11
+51    0x7C7C    //RX_FDEQ_GAIN_12
+52    0x7888    //RX_FDEQ_GAIN_13
+53    0x7852    //RX_FDEQ_GAIN_14
+54    0x4C70    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -31506,22 +28471,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0402    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1E1E    //RX_FDEQ_BIN_11
-75    0x1E1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E1E    //RX_FDEQ_BIN_14
-78    0x202C    //RX_FDEQ_BIN_15
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x1F06    //RX_FDEQ_BIN_10
+74    0x110B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x2228    //RX_FDEQ_BIN_14
+78    0x5160    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -31556,15 +28521,867 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
-#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#CASE_NAME  HANDSET-HANDSET-CUSTOM2-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0000    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
 2    0x0026    //TX_PATCH_REG
-3    0x6B7E    //TX_SENDFUNC_MODE_0
+3    0x6B5E    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0002    //TX_NUM_MIC
 6    0x0004    //TX_SAMPLINGFREQ_SIG
@@ -31582,7 +29399,7 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
+21    0x00A4    //TX_DIST2REF1
 22    0x0000    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
@@ -31812,12 +29629,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF700    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -31845,16 +29662,16 @@
 281    0x0014    //TX_NS_LVL_CTRL_0
 282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0018    //TX_NS_LVL_CTRL_4
-286    0x0016    //TX_NS_LVL_CTRL_5
-287    0x0012    //TX_NS_LVL_CTRL_6
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
 288    0x0017    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0007    //TX_MIN_GAIN_S_2
-292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
 294    0x0012    //TX_MIN_GAIN_S_5
 295    0x0012    //TX_MIN_GAIN_S_6
 296    0x0012    //TX_MIN_GAIN_S_7
@@ -31876,29 +29693,29 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
+315    0x4000    //TX_A_POST_FILT_S_1
 316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
+326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x6000    //TX_B_POST_FILT_6
+328    0x3000    //TX_B_POST_FILT_6
 329    0x3000    //TX_B_POST_FILT_7
 330    0x1000    //TX_B_LESSCUT_RTO_S_0
-331    0x6000    //TX_B_LESSCUT_RTO_S_1
-332    0x6000    //TX_B_LESSCUT_RTO_S_2
-333    0x6000    //TX_B_LESSCUT_RTO_S_3
-334    0x6000    //TX_B_LESSCUT_RTO_S_4
-335    0x6000    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
 340    0x7C29    //TX_LAMBDA_PFILT_S_1
@@ -31941,10 +29758,10 @@
 377    0x4E20    //TX_NOISE_TH_5_4
 378    0x39DF    //TX_NOISE_TH_6
 379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -31952,15 +29769,15 @@
 388    0x0200    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -32075,16 +29892,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -32113,69 +29930,69 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x9848    //TX_FDEQ_GAIN_0
-568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4840    //TX_FDEQ_GAIN_2
-570    0x3E4C    //TX_FDEQ_GAIN_3
-571    0x484C    //TX_FDEQ_GAIN_4
-572    0x7058    //TX_FDEQ_GAIN_5
-573    0x6068    //TX_FDEQ_GAIN_6
-574    0x645E    //TX_FDEQ_GAIN_7
-575    0x8054    //TX_FDEQ_GAIN_8
-576    0x5454    //TX_FDEQ_GAIN_9
-577    0x9898    //TX_FDEQ_GAIN_10
-578    0x9898    //TX_FDEQ_GAIN_11
-579    0x9898    //TX_FDEQ_GAIN_12
-580    0x9898    //TX_FDEQ_GAIN_13
-581    0x9898    //TX_FDEQ_GAIN_14
-582    0x9898    //TX_FDEQ_GAIN_15
-583    0x9898    //TX_FDEQ_GAIN_16
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
 584    0x9898    //TX_FDEQ_GAIN_17
 585    0x9898    //TX_FDEQ_GAIN_18
-586    0x9898    //TX_FDEQ_GAIN_19
-587    0x9898    //TX_FDEQ_GAIN_20
-588    0x9898    //TX_FDEQ_GAIN_21
-589    0x9898    //TX_FDEQ_GAIN_22
-590    0x9898    //TX_FDEQ_GAIN_23
-591    0x0103    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0605    //TX_FDEQ_BIN_2
-594    0x040A    //TX_FDEQ_BIN_3
-595    0x1417    //TX_FDEQ_BIN_4
-596    0x0C19    //TX_FDEQ_BIN_5
-597    0x1B04    //TX_FDEQ_BIN_6
-598    0x0F25    //TX_FDEQ_BIN_7
-599    0x1610    //TX_FDEQ_BIN_8
-600    0x0605    //TX_FDEQ_BIN_9
-601    0x0505    //TX_FDEQ_BIN_10
-602    0x0D0F    //TX_FDEQ_BIN_11
+586    0x9848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
 603    0x0F0F    //TX_FDEQ_BIN_12
 604    0x0A0F    //TX_FDEQ_BIN_13
 605    0x0809    //TX_FDEQ_BIN_14
-606    0x0A8C    //TX_FDEQ_BIN_15
+606    0x0A0B    //TX_FDEQ_BIN_15
 607    0x0C0D    //TX_FDEQ_BIN_16
 608    0x0E0F    //TX_FDEQ_BIN_17
 609    0x1013    //TX_FDEQ_BIN_18
-610    0x0A14    //TX_FDEQ_BIN_19
-611    0x0301    //TX_FDEQ_BIN_20
-612    0x0101    //TX_FDEQ_BIN_21
-613    0x0101    //TX_FDEQ_BIN_22
-614    0x0101    //TX_FDEQ_BIN_23
+610    0x0A00    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
 616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
@@ -32233,15 +30050,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x3448    //TX_PREEQ_GAIN_MIC1_10
-677    0x3448    //TX_PREEQ_GAIN_MIC1_11
-678    0x3848    //TX_PREEQ_GAIN_MIC1_12
-679    0x5848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -32260,13 +30077,13 @@
 696    0x0708    //TX_PREEQ_BIN_MIC1_6
 697    0x0909    //TX_PREEQ_BIN_MIC1_7
 698    0x090B    //TX_PREEQ_BIN_MIC1_8
-699    0x0C0E    //TX_PREEQ_BIN_MIC1_9
-700    0x0613    //TX_PREEQ_BIN_MIC1_10
-701    0x0603    //TX_PREEQ_BIN_MIC1_11
-702    0x071D    //TX_PREEQ_BIN_MIC1_12
-703    0x1A6D    //TX_PREEQ_BIN_MIC1_13
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
 704    0x1E28    //TX_PREEQ_BIN_MIC1_14
-705    0x282C    //TX_PREEQ_BIN_MIC1_15
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
@@ -32344,15 +30161,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x6000    //TX_TDDRC_ALPHA_UP_02
-785    0x6000    //TX_TDDRC_ALPHA_UP_03
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x6000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -32377,8 +30194,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -32415,19 +30232,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0003    //TX_TDDRC_THRD_0
-855    0x0005    //TX_TDDRC_THRD_1
-856    0x0640    //TX_TDDRC_THRD_2
-857    0x1BC0    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
 860    0x1000    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0523    //TX_TDDRC_DRC_GAIN
+866    0x0504    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -32458,17 +30275,16102 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x006C    //RX_RECVFUNC_MODE_0
+0    0x003C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0722    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0016    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0059    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0090    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0722    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0016    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0059    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-RESERVE1-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F57    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0551    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x042B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0438    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005F    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705C    //RX_FDEQ_GAIN_0
+40    0x6E7E    //RX_FDEQ_GAIN_1
+41    0x808E    //RX_FDEQ_GAIN_2
+42    0x8472    //RX_FDEQ_GAIN_3
+43    0x7476    //RX_FDEQ_GAIN_4
+44    0x7278    //RX_FDEQ_GAIN_5
+45    0x8092    //RX_FDEQ_GAIN_6
+46    0xA4A2    //RX_FDEQ_GAIN_7
+47    0xB49C    //RX_FDEQ_GAIN_8
+48    0x8E7C    //RX_FDEQ_GAIN_9
+49    0x8664    //RX_FDEQ_GAIN_10
+50    0x5A78    //RX_FDEQ_GAIN_11
+51    0x7C7C    //RX_FDEQ_GAIN_12
+52    0x7888    //RX_FDEQ_GAIN_13
+53    0x7852    //RX_FDEQ_GAIN_14
+54    0x4C70    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x1F06    //RX_FDEQ_BIN_10
+74    0x110B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x2228    //RX_FDEQ_BIN_14
+78    0x5160    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-RESERVE1-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0026    //TX_PATCH_REG
+3    0x6B56    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x00A4    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7000    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7000    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x6000    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x2000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0016    //TX_NS_LVL_CTRL_1
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0012    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x6000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x6000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x4000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x4000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x3000    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x00C6    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x2EE0    //TX_NOISE_TH_3
+373    0x47E0    //TX_NOISE_TH_4
+374    0x57E4    //TX_NOISE_TH_5
+375    0x4BD6    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x39DF    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x051E    //TX_SB_RHO_MEAN2_TH
+441    0x051E    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
+584    0x9898    //TX_FDEQ_GAIN_17
+585    0x9898    //TX_FDEQ_GAIN_18
+586    0x9848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0A0F    //TX_FDEQ_BIN_13
+605    0x0809    //TX_FDEQ_BIN_14
+606    0x0A0B    //TX_FDEQ_BIN_15
+607    0x0C0D    //TX_FDEQ_BIN_16
+608    0x0E0F    //TX_FDEQ_BIN_17
+609    0x1013    //TX_FDEQ_BIN_18
+610    0x0A00    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x1812    //TX_PREEQ_BIN_MIC0_0
+642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
+643    0x0808    //TX_PREEQ_BIN_MIC0_2
+644    0x080A    //TX_PREEQ_BIN_MIC0_3
+645    0x0B09    //TX_PREEQ_BIN_MIC0_4
+646    0x0A06    //TX_PREEQ_BIN_MIC0_5
+647    0x0606    //TX_PREEQ_BIN_MIC0_6
+648    0x0605    //TX_PREEQ_BIN_MIC0_7
+649    0x050A    //TX_PREEQ_BIN_MIC0_8
+650    0x1505    //TX_PREEQ_BIN_MIC0_9
+651    0x0506    //TX_PREEQ_BIN_MIC0_10
+652    0x0615    //TX_PREEQ_BIN_MIC0_11
+653    0x1516    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x2021    //TX_PREEQ_BIN_MIC0_14
+656    0x2021    //TX_PREEQ_BIN_MIC0_15
+657    0x0800    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x0909    //TX_PREEQ_BIN_MIC1_7
+698    0x090B    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
+704    0x1E28    //TX_PREEQ_BIN_MIC1_14
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
+860    0x1000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0504    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x003C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0722    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0016    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0059    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0090    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x02FD    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E4E    //RX_FDEQ_GAIN_0
+40    0x4E56    //RX_FDEQ_GAIN_1
+41    0x6878    //RX_FDEQ_GAIN_2
+42    0x8088    //RX_FDEQ_GAIN_3
+43    0x848B    //RX_FDEQ_GAIN_4
+44    0x8F8E    //RX_FDEQ_GAIN_5
+45    0x9494    //RX_FDEQ_GAIN_6
+46    0x96A0    //RX_FDEQ_GAIN_7
+47    0xB8A0    //RX_FDEQ_GAIN_8
+48    0xA99D    //RX_FDEQ_GAIN_9
+49    0x9D6A    //RX_FDEQ_GAIN_10
+50    0x626B    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x7884    //RX_FDEQ_GAIN_13
+53    0x9098    //RX_FDEQ_GAIN_14
+54    0x9CAC    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0302    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0722    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0016    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0059    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x02FD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E4E    //RX_FDEQ_GAIN_0
+197    0x4E56    //RX_FDEQ_GAIN_1
+198    0x6878    //RX_FDEQ_GAIN_2
+199    0x8088    //RX_FDEQ_GAIN_3
+200    0x848B    //RX_FDEQ_GAIN_4
+201    0x8F8E    //RX_FDEQ_GAIN_5
+202    0x9494    //RX_FDEQ_GAIN_6
+203    0x96A0    //RX_FDEQ_GAIN_7
+204    0xB8A0    //RX_FDEQ_GAIN_8
+205    0xA99D    //RX_FDEQ_GAIN_9
+206    0x9D6A    //RX_FDEQ_GAIN_10
+207    0x626B    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x7884    //RX_FDEQ_GAIN_13
+210    0x9098    //RX_FDEQ_GAIN_14
+211    0x9CAC    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0302    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x483E    //RX_FDEQ_GAIN_0
+40    0x3E3E    //RX_FDEQ_GAIN_1
+41    0x3E4C    //RX_FDEQ_GAIN_2
+42    0x5064    //RX_FDEQ_GAIN_3
+43    0x7076    //RX_FDEQ_GAIN_4
+44    0x897A    //RX_FDEQ_GAIN_5
+45    0x7C80    //RX_FDEQ_GAIN_6
+46    0x8888    //RX_FDEQ_GAIN_7
+47    0x949C    //RX_FDEQ_GAIN_8
+48    0x96A4    //RX_FDEQ_GAIN_9
+49    0xA9A0    //RX_FDEQ_GAIN_10
+50    0x9487    //RX_FDEQ_GAIN_11
+51    0x6F64    //RX_FDEQ_GAIN_12
+52    0x625A    //RX_FDEQ_GAIN_13
+53    0x5D80    //RX_FDEQ_GAIN_14
+54    0x8890    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0301    //RX_FDEQ_BIN_2
+66    0x0404    //RX_FDEQ_BIN_3
+67    0x0406    //RX_FDEQ_BIN_4
+68    0x0109    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B0F    //RX_FDEQ_BIN_12
+76    0x141E    //RX_FDEQ_BIN_13
+77    0x3728    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0551    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0780    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0B4A    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x042B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0015    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0438    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0024    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x003B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005F    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0444    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705E    //RX_FDEQ_GAIN_0
+40    0x6C7C    //RX_FDEQ_GAIN_1
+41    0x7E88    //RX_FDEQ_GAIN_2
+42    0x7E72    //RX_FDEQ_GAIN_3
+43    0x7678    //RX_FDEQ_GAIN_4
+44    0x747A    //RX_FDEQ_GAIN_5
+45    0x8294    //RX_FDEQ_GAIN_6
+46    0xA6A4    //RX_FDEQ_GAIN_7
+47    0xB69E    //RX_FDEQ_GAIN_8
+48    0x907C    //RX_FDEQ_GAIN_9
+49    0x7C68    //RX_FDEQ_GAIN_10
+50    0x5658    //RX_FDEQ_GAIN_11
+51    0x6068    //RX_FDEQ_GAIN_12
+52    0x6E7C    //RX_FDEQ_GAIN_13
+53    0x7048    //RX_FDEQ_GAIN_14
+54    0x445C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A13    //RX_FDEQ_BIN_9
+73    0x1A05    //RX_FDEQ_BIN_10
+74    0x120B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x223F    //RX_FDEQ_BIN_14
+78    0x3C5E    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x009A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0006    //RX_TDDRC_THRD_1
+114    0x0700    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x1000    //RX_TDDRC_SLANT_0
+117    0x4000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0451    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x705C    //RX_FDEQ_GAIN_0
+40    0x6E7E    //RX_FDEQ_GAIN_1
+41    0x808E    //RX_FDEQ_GAIN_2
+42    0x8472    //RX_FDEQ_GAIN_3
+43    0x7476    //RX_FDEQ_GAIN_4
+44    0x7278    //RX_FDEQ_GAIN_5
+45    0x8092    //RX_FDEQ_GAIN_6
+46    0xA4A2    //RX_FDEQ_GAIN_7
+47    0xB49C    //RX_FDEQ_GAIN_8
+48    0x8E7C    //RX_FDEQ_GAIN_9
+49    0x8664    //RX_FDEQ_GAIN_10
+50    0x5A78    //RX_FDEQ_GAIN_11
+51    0x7C7C    //RX_FDEQ_GAIN_12
+52    0x7888    //RX_FDEQ_GAIN_13
+53    0x7852    //RX_FDEQ_GAIN_14
+54    0x4C70    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0203    //RX_FDEQ_BIN_0
+64    0x0202    //RX_FDEQ_BIN_1
+65    0x0104    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0A06    //RX_FDEQ_BIN_5
+69    0x0B09    //RX_FDEQ_BIN_6
+70    0x0506    //RX_FDEQ_BIN_7
+71    0x0C09    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x1F06    //RX_FDEQ_BIN_10
+74    0x110B    //RX_FDEQ_BIN_11
+75    0x0816    //RX_FDEQ_BIN_12
+76    0x141A    //RX_FDEQ_BIN_13
+77    0x2228    //RX_FDEQ_BIN_14
+78    0x5160    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x05AA    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x13E0    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0010    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0032    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0047    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0076    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0551    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x483E    //RX_FDEQ_GAIN_0
+197    0x3E3E    //RX_FDEQ_GAIN_1
+198    0x3E4C    //RX_FDEQ_GAIN_2
+199    0x5064    //RX_FDEQ_GAIN_3
+200    0x7076    //RX_FDEQ_GAIN_4
+201    0x897A    //RX_FDEQ_GAIN_5
+202    0x7C80    //RX_FDEQ_GAIN_6
+203    0x8888    //RX_FDEQ_GAIN_7
+204    0x949C    //RX_FDEQ_GAIN_8
+205    0x96A4    //RX_FDEQ_GAIN_9
+206    0xA9A0    //RX_FDEQ_GAIN_10
+207    0x9487    //RX_FDEQ_GAIN_11
+208    0x6F64    //RX_FDEQ_GAIN_12
+209    0x625A    //RX_FDEQ_GAIN_13
+210    0x5D80    //RX_FDEQ_GAIN_14
+211    0x8890    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0202    //RX_FDEQ_BIN_1
+222    0x0301    //RX_FDEQ_BIN_2
+223    0x0404    //RX_FDEQ_BIN_3
+224    0x0406    //RX_FDEQ_BIN_4
+225    0x0109    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B0F    //RX_FDEQ_BIN_12
+233    0x141E    //RX_FDEQ_BIN_13
+234    0x3728    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-NB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7646    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7C00    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7DC8    //TX_DTD_THR1_0
+198    0x7DC8    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7530    //TX_DTD_THR1_4
+202    0x7530    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x1000    //TX_DTD_THR2_0
+205    0x1000    //TX_DTD_THR2_1
+206    0x1000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FB0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFD00    //TX_THR_SN_EST_1
+244    0xFD00    //TX_THR_SN_EST_2
+245    0xFD00    //TX_THR_SN_EST_3
+246    0xF900    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x01A0    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0000    //TX_DELTA_THR_SN_EST_5
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x2000    //TX_LAMBDA_NN_EST_2
+261    0x3000    //TX_LAMBDA_NN_EST_3
+262    0x3000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x3000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x3000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x3000    //TX_MAINREFRTO_TH_H
+277    0x1000    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x4000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0017    //TX_NS_LVL_CTRL_2
+284    0x0017    //TX_NS_LVL_CTRL_3
+285    0x0019    //TX_NS_LVL_CTRL_4
+286    0x0014    //TX_NS_LVL_CTRL_5
+287    0x001B    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x0010    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x4000    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x3000    //TX_SNRI_SUP_7
+308    0x3000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x2000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x4000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x4000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7900    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7900    //TX_LAMBDA_PFILT_S_3
+343    0x7200    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x0C80    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0004    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x09C4    //TX_NOISE_TH_1
+371    0x022C    //TX_NOISE_TH_2
+372    0x4650    //TX_NOISE_TH_3
+373    0x7E2C    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x4650    //TX_NOISE_TH_6
+379    0x0004    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x1000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0003    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x000A    //TX_NS_ENOISE_MIC0_TH
+406    0x0004    //TX_MINENOISE_MIC0_TH
+407    0x0014    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1FFF    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x4000    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0100    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0666    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x6000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x001A    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0080    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0018    //TX_FDEQ_SUBNUM
+567    0x7064    //TX_FDEQ_GAIN_0
+568    0x5E54    //TX_FDEQ_GAIN_1
+569    0x5350    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4642    //TX_FDEQ_GAIN_4
+572    0x4034    //TX_FDEQ_GAIN_5
+573    0x3E4C    //TX_FDEQ_GAIN_6
+574    0x3636    //TX_FDEQ_GAIN_7
+575    0x3634    //TX_FDEQ_GAIN_8
+576    0x4448    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0502    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0404    //TX_FDEQ_BIN_4
+596    0x0409    //TX_FDEQ_BIN_5
+597    0x0507    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x0B0A    //TX_FDEQ_BIN_8
+600    0x1109    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C08    //TX_PREEQ_BIN_MIC0_2
+644    0x0700    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0065    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0065    //TX_MIC_CALIBRATION_2
+768    0x0065    //TX_MIC_CALIBRATION_3
+769    0x0044    //TX_MIC_PWR_BIAS_0
+770    0x0044    //TX_MIC_PWR_BIAS_1
+771    0x0044    //TX_MIC_PWR_BIAS_2
+772    0x0044    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0004    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x089C    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0208    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x000A    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x12E1    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7D00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x75F8    //TX_DTD_THR1_MICMUTE_0
+912    0x76C0    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x7FFF    //TX_MICMUTE_C_POST_FLT
+922    0x0FA0    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x0FA0    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0C00    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7148    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0360    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
 8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-WB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0036    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0001    //TX_SAMPLINGFREQ_SIG
+7    0x0001    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x6000    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x0200    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7918    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFB00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x01A0    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x2000    //TX_MAINREFRTOH_TH_H
+275    0x1400    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0018    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x001A    //TX_NS_LVL_CTRL_4
+286    0x001E    //TX_NS_LVL_CTRL_5
+287    0x001C    //TX_NS_LVL_CTRL_6
+288    0x001C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x000A    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0012    //TX_MIN_GAIN_S_3
+293    0x0018    //TX_MIN_GAIN_S_4
+294    0x0018    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0018    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x3000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x2000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x4000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7000    //TX_A_POST_FILT_S_0
+315    0x3000    //TX_A_POST_FILT_S_1
+316    0x3000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x7000    //TX_A_POST_FILT_S_4
+319    0x7000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x4000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x5000    //TX_B_POST_FILT_6
+329    0x4000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x6000    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C29    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0600    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x0BB8    //TX_NOISE_TH_1
+371    0x0479    //TX_NOISE_TH_2
+372    0x4A38    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0032    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x21E8    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0500    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4900    //TX_MIN_G_CTRL_SSNS
+409    0x1000    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x05A8    //TX_SB_RHO_MEAN2_TH
+441    0x0384    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x0200    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x5E56    //TX_FDEQ_GAIN_0
+568    0x564E    //TX_FDEQ_GAIN_1
+569    0x4E4E    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4646    //TX_FDEQ_GAIN_4
+572    0x4440    //TX_FDEQ_GAIN_5
+573    0x4C56    //TX_FDEQ_GAIN_6
+574    0x4A48    //TX_FDEQ_GAIN_7
+575    0x4242    //TX_FDEQ_GAIN_8
+576    0x4C50    //TX_FDEQ_GAIN_9
+577    0x5252    //TX_FDEQ_GAIN_10
+578    0x6058    //TX_FDEQ_GAIN_11
+579    0x5656    //TX_FDEQ_GAIN_12
+580    0x5670    //TX_FDEQ_GAIN_13
+581    0x7070    //TX_FDEQ_GAIN_14
+582    0x7070    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0504    //TX_FDEQ_BIN_4
+596    0x0906    //TX_FDEQ_BIN_5
+597    0x0407    //TX_FDEQ_BIN_6
+598    0x0A12    //TX_FDEQ_BIN_7
+599    0x0707    //TX_FDEQ_BIN_8
+600    0x160D    //TX_FDEQ_BIN_9
+601    0x0F12    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0505    //TX_FDEQ_BIN_13
+605    0x0505    //TX_FDEQ_BIN_14
+606    0x0504    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x000E    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0700    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x5858    //TX_PREEQ_GAIN_MIC1_11
+678    0x5858    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x120F    //TX_PREEQ_BIN_MIC1_10
+701    0x0E11    //TX_PREEQ_BIN_MIC1_11
+702    0x1109    //TX_PREEQ_BIN_MIC1_12
+703    0x0B1B    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0063    //TX_MIC_CALIBRATION_0
+766    0x0063    //TX_MIC_CALIBRATION_1
+767    0x0063    //TX_MIC_CALIBRATION_2
+768    0x0063    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0003    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0876    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x199A    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x2000    //TX_B_LESSCUT_RTO_MASK
+877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x026C    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7000    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x6B6C    //TX_DTD_THR1_MICMUTE_0
+912    0x7FFF    //TX_DTD_THR1_MICMUTE_1
+913    0x6590    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0180    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7530    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0001    //RX_SAMPLINGFREQ_SIG
+3    0x0001    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0505    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0505    //RX_FDEQ_BIN_6
+70    0x0505    //RX_FDEQ_BIN_7
+71    0x160C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0400    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4748    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
 11    0x7FFF    //RX_A_HP
 12    0x4000    //RX_B_PE
@@ -32484,14 +46386,14 @@
 22    0x000F    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
@@ -32570,20 +46472,20 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
 126    0x2000    //RX_TPKA_FP
 127    0x2000    //RX_MIN_G_FP
@@ -32617,23 +46519,23 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
 8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 32    0x6000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
 114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
+115    0x1000    //RX_TDDRC_THRD_3
 116    0x0000    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
@@ -32641,6 +46543,2676 @@
 123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x0100    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-VOICE_GENERIC-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0026    //TX_PATCH_REG
+3    0x6B7E    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7000    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7000    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x6000    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x2000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0016    //TX_NS_LVL_CTRL_1
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0018    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0007    //TX_MIN_GAIN_S_1
+291    0x0012    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0012    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x6000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x6000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x4000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x4000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x3000    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x00C6    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x2EE0    //TX_NOISE_TH_3
+373    0x47E0    //TX_NOISE_TH_4
+374    0x57E4    //TX_NOISE_TH_5
+375    0x4BD6    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x39DF    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x051E    //TX_SB_RHO_MEAN2_TH
+441    0x051E    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x7FFF    //TX_GSC_RTOL_TH
+522    0x7FFF    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x4C4A    //TX_FDEQ_GAIN_0
+568    0x4B4F    //TX_FDEQ_GAIN_1
+569    0x504B    //TX_FDEQ_GAIN_2
+570    0x4A4C    //TX_FDEQ_GAIN_3
+571    0x4A49    //TX_FDEQ_GAIN_4
+572    0x4F48    //TX_FDEQ_GAIN_5
+573    0x4A4E    //TX_FDEQ_GAIN_6
+574    0x534E    //TX_FDEQ_GAIN_7
+575    0x494F    //TX_FDEQ_GAIN_8
+576    0x5E6E    //TX_FDEQ_GAIN_9
+577    0x787A    //TX_FDEQ_GAIN_10
+578    0x6A58    //TX_FDEQ_GAIN_11
+579    0x5051    //TX_FDEQ_GAIN_12
+580    0x5156    //TX_FDEQ_GAIN_13
+581    0x6168    //TX_FDEQ_GAIN_14
+582    0x7678    //TX_FDEQ_GAIN_15
+583    0x7A87    //TX_FDEQ_GAIN_16
+584    0x9898    //TX_FDEQ_GAIN_17
+585    0x9898    //TX_FDEQ_GAIN_18
+586    0x9848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0F03    //TX_FDEQ_BIN_0
+592    0x0909    //TX_FDEQ_BIN_1
+593    0x080F    //TX_FDEQ_BIN_2
+594    0x0609    //TX_FDEQ_BIN_3
+595    0x0F03    //TX_FDEQ_BIN_4
+596    0x1402    //TX_FDEQ_BIN_5
+597    0x0E13    //TX_FDEQ_BIN_6
+598    0x110F    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x0E0F    //TX_FDEQ_BIN_9
+601    0x080D    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0A0F    //TX_FDEQ_BIN_13
+605    0x0809    //TX_FDEQ_BIN_14
+606    0x0A0B    //TX_FDEQ_BIN_15
+607    0x0C0D    //TX_FDEQ_BIN_16
+608    0x0E0F    //TX_FDEQ_BIN_17
+609    0x1013    //TX_FDEQ_BIN_18
+610    0x0A00    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x1812    //TX_PREEQ_BIN_MIC0_0
+642    0x0A0A    //TX_PREEQ_BIN_MIC0_1
+643    0x0808    //TX_PREEQ_BIN_MIC0_2
+644    0x080A    //TX_PREEQ_BIN_MIC0_3
+645    0x0B09    //TX_PREEQ_BIN_MIC0_4
+646    0x0A06    //TX_PREEQ_BIN_MIC0_5
+647    0x0606    //TX_PREEQ_BIN_MIC0_6
+648    0x0605    //TX_PREEQ_BIN_MIC0_7
+649    0x050A    //TX_PREEQ_BIN_MIC0_8
+650    0x1505    //TX_PREEQ_BIN_MIC0_9
+651    0x0506    //TX_PREEQ_BIN_MIC0_10
+652    0x0615    //TX_PREEQ_BIN_MIC0_11
+653    0x1516    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x2021    //TX_PREEQ_BIN_MIC0_14
+656    0x2021    //TX_PREEQ_BIN_MIC0_15
+657    0x0800    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4A4C    //TX_PREEQ_GAIN_MIC1_6
+673    0x4E50    //TX_PREEQ_GAIN_MIC1_7
+674    0x5456    //TX_PREEQ_GAIN_MIC1_8
+675    0x585C    //TX_PREEQ_GAIN_MIC1_9
+676    0x5C64    //TX_PREEQ_GAIN_MIC1_10
+677    0x7478    //TX_PREEQ_GAIN_MIC1_11
+678    0x705C    //TX_PREEQ_GAIN_MIC1_12
+679    0x4838    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C70    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x0909    //TX_PREEQ_BIN_MIC1_7
+698    0x090B    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x1414    //TX_PREEQ_BIN_MIC1_12
+703    0x1C1E    //TX_PREEQ_BIN_MIC1_13
+704    0x1E28    //TX_PREEQ_BIN_MIC1_14
+705    0x462C    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x1800    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7E00    //TX_TDDRC_SLANT_1
+860    0x1000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0504    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x000C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4844    //RX_FDEQ_GAIN_2
@@ -32716,29 +49288,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -32815,29 +49387,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -32914,29 +49486,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -33013,29 +49585,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -33112,29 +49684,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -33211,29 +49783,29 @@
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x4000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
 33    0x7000    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0730    //RX_TDDRC_THRD_2
-115    0x17C0    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x01E0    //RX_TDDRC_DRC_GAIN
 38    0x0030    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -33309,4 +49881,14205 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-NB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7646    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7C00    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7DC8    //TX_DTD_THR1_0
+198    0x7DC8    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7530    //TX_DTD_THR1_4
+202    0x7530    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x1000    //TX_DTD_THR2_0
+205    0x1000    //TX_DTD_THR2_1
+206    0x1000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FB0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFD00    //TX_THR_SN_EST_1
+244    0xFD00    //TX_THR_SN_EST_2
+245    0xFD00    //TX_THR_SN_EST_3
+246    0xF900    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x01A0    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0000    //TX_DELTA_THR_SN_EST_5
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x2000    //TX_LAMBDA_NN_EST_2
+261    0x3000    //TX_LAMBDA_NN_EST_3
+262    0x3000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x3000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x3000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x3000    //TX_MAINREFRTO_TH_H
+277    0x1000    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x4000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0017    //TX_NS_LVL_CTRL_2
+284    0x0017    //TX_NS_LVL_CTRL_3
+285    0x0019    //TX_NS_LVL_CTRL_4
+286    0x0014    //TX_NS_LVL_CTRL_5
+287    0x001B    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x0010    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x4000    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x3000    //TX_SNRI_SUP_7
+308    0x3000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x2000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x4000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x4000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7900    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7900    //TX_LAMBDA_PFILT_S_3
+343    0x7200    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x0C80    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0004    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x09C4    //TX_NOISE_TH_1
+371    0x022C    //TX_NOISE_TH_2
+372    0x4650    //TX_NOISE_TH_3
+373    0x7E2C    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x4650    //TX_NOISE_TH_6
+379    0x0004    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x1000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0003    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x000A    //TX_NS_ENOISE_MIC0_TH
+406    0x0004    //TX_MINENOISE_MIC0_TH
+407    0x0014    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1FFF    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x4000    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0280    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0100    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0666    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x6000    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x001A    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0080    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0018    //TX_FDEQ_SUBNUM
+567    0x7064    //TX_FDEQ_GAIN_0
+568    0x5E54    //TX_FDEQ_GAIN_1
+569    0x5350    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4642    //TX_FDEQ_GAIN_4
+572    0x4038    //TX_FDEQ_GAIN_5
+573    0x3E44    //TX_FDEQ_GAIN_6
+574    0x3636    //TX_FDEQ_GAIN_7
+575    0x3634    //TX_FDEQ_GAIN_8
+576    0x4448    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0502    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0404    //TX_FDEQ_BIN_4
+596    0x0409    //TX_FDEQ_BIN_5
+597    0x0507    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x0B0A    //TX_FDEQ_BIN_8
+600    0x1109    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C08    //TX_PREEQ_BIN_MIC0_2
+644    0x0700    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0065    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0065    //TX_MIC_CALIBRATION_2
+768    0x0065    //TX_MIC_CALIBRATION_3
+769    0x0044    //TX_MIC_PWR_BIAS_0
+770    0x0044    //TX_MIC_PWR_BIAS_1
+771    0x0044    //TX_MIC_PWR_BIAS_2
+772    0x0044    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0004    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x089C    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0208    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x000A    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x12E1    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7D00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x75F8    //TX_DTD_THR1_MICMUTE_0
+912    0x76C0    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x7FFF    //TX_MICMUTE_C_POST_FLT
+922    0x0FA0    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x0FA0    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0C00    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7148    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0000    //RX_SAMPLINGFREQ_SIG
+3    0x0000    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0360    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x5050    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C48    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0E    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0360    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C48    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0303    //RX_FDEQ_BIN_3
+224    0x0303    //RX_FDEQ_BIN_4
+225    0x0303    //RX_FDEQ_BIN_5
+226    0x0303    //RX_FDEQ_BIN_6
+227    0x0303    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-WB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0036    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0001    //TX_SAMPLINGFREQ_SIG
+7    0x0001    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0800    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x6000    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x0200    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x0400    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x0400    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x0200    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7918    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7F00    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0000    //TX_RATIO_DT_L_TH_LOW
+224    0x0000    //TX_RATIO_DT_H_TH_LOW
+225    0x0000    //TX_RATIO_DT_L_TH_HIGH
+226    0x0000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0000    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0000    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFB00    //TX_THR_SN_EST_2
+245    0xF800    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x01A0    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x3000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x0000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x2000    //TX_MAINREFRTOH_TH_H
+275    0x1400    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x4000    //TX_B_POST_FLT_1
+281    0x0018    //TX_NS_LVL_CTRL_0
+282    0x0019    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x001A    //TX_NS_LVL_CTRL_4
+286    0x001E    //TX_NS_LVL_CTRL_5
+287    0x001C    //TX_NS_LVL_CTRL_6
+288    0x001C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x000A    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0012    //TX_MIN_GAIN_S_3
+293    0x0018    //TX_MIN_GAIN_S_4
+294    0x0018    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0018    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x3000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x2000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x4000    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7000    //TX_A_POST_FILT_S_0
+315    0x3000    //TX_A_POST_FILT_S_1
+316    0x3000    //TX_A_POST_FILT_S_2
+317    0x2000    //TX_A_POST_FILT_S_3
+318    0x7000    //TX_A_POST_FILT_S_4
+319    0x7000    //TX_A_POST_FILT_S_5
+320    0x7000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x4000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x4000    //TX_B_POST_FILT_5
+328    0x5000    //TX_B_POST_FILT_6
+329    0x4000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x6000    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C29    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0600    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x0BB8    //TX_NOISE_TH_1
+371    0x0479    //TX_NOISE_TH_2
+372    0x4A38    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0032    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x21E8    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0500    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4900    //TX_MIN_G_CTRL_SSNS
+409    0x1000    //TX_METAL_RTO_THR
+410    0x0FA0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x1C00    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x05A8    //TX_SB_RHO_MEAN2_TH
+441    0x0384    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0280    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x0200    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x0000    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x5E56    //TX_FDEQ_GAIN_0
+568    0x564E    //TX_FDEQ_GAIN_1
+569    0x4E4E    //TX_FDEQ_GAIN_2
+570    0x4C4A    //TX_FDEQ_GAIN_3
+571    0x4646    //TX_FDEQ_GAIN_4
+572    0x4440    //TX_FDEQ_GAIN_5
+573    0x4C56    //TX_FDEQ_GAIN_6
+574    0x4A48    //TX_FDEQ_GAIN_7
+575    0x4242    //TX_FDEQ_GAIN_8
+576    0x4C50    //TX_FDEQ_GAIN_9
+577    0x524E    //TX_FDEQ_GAIN_10
+578    0x5658    //TX_FDEQ_GAIN_11
+579    0x5656    //TX_FDEQ_GAIN_12
+580    0x5670    //TX_FDEQ_GAIN_13
+581    0x7070    //TX_FDEQ_GAIN_14
+582    0x7070    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0302    //TX_FDEQ_BIN_3
+595    0x0504    //TX_FDEQ_BIN_4
+596    0x0906    //TX_FDEQ_BIN_5
+597    0x0407    //TX_FDEQ_BIN_6
+598    0x0A12    //TX_FDEQ_BIN_7
+599    0x0707    //TX_FDEQ_BIN_8
+600    0x160D    //TX_FDEQ_BIN_9
+601    0x0F12    //TX_FDEQ_BIN_10
+602    0x0F0F    //TX_FDEQ_BIN_11
+603    0x0F0F    //TX_FDEQ_BIN_12
+604    0x0505    //TX_FDEQ_BIN_13
+605    0x0505    //TX_FDEQ_BIN_14
+606    0x0504    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x000E    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x251A    //TX_PREEQ_BIN_MIC0_0
+642    0x0F0F    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0700    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x5858    //TX_PREEQ_GAIN_MIC1_11
+678    0x5858    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x120F    //TX_PREEQ_BIN_MIC1_10
+701    0x0E11    //TX_PREEQ_BIN_MIC1_11
+702    0x1109    //TX_PREEQ_BIN_MIC1_12
+703    0x0B1B    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0063    //TX_MIC_CALIBRATION_0
+766    0x0063    //TX_MIC_CALIBRATION_1
+767    0x0063    //TX_MIC_CALIBRATION_2
+768    0x0063    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
+775    0x0004    //TX_GAIN_LIMIT_2
+776    0x0003    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0876    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x199A    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x2000    //TX_B_LESSCUT_RTO_MASK
+877    0x1C00    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x026C    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7000    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x6000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x6B6C    //TX_DTD_THR1_MICMUTE_0
+912    0x7FFF    //TX_DTD_THR1_MICMUTE_1
+913    0x6590    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x2000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0180    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7530    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0001    //RX_SAMPLINGFREQ_SIG
+3    0x0001    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0505    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0505    //RX_FDEQ_BIN_6
+70    0x0505    //RX_FDEQ_BIN_7
+71    0x160C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0400    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4748    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x6000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0730    //RX_TDDRC_THRD_2
+115    0x1000    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0400    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4A4C    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5A5C    //RX_FDEQ_GAIN_7
+204    0x5C5C    //RX_FDEQ_GAIN_8
+205    0x5C5C    //RX_FDEQ_GAIN_9
+206    0x5C5C    //RX_FDEQ_GAIN_10
+207    0x5C5C    //RX_FDEQ_GAIN_11
+208    0x5C5C    //RX_FDEQ_GAIN_12
+209    0x5C5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0505    //RX_FDEQ_BIN_4
+225    0x0505    //RX_FDEQ_BIN_5
+226    0x0505    //RX_FDEQ_BIN_6
+227    0x0505    //RX_FDEQ_BIN_7
+228    0x160C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x565A    //TX_FDEQ_GAIN_9
+577    0x585A    //TX_FDEQ_GAIN_10
+578    0x5C5C    //TX_FDEQ_GAIN_11
+579    0x5460    //TX_FDEQ_GAIN_12
+580    0x644E    //TX_FDEQ_GAIN_13
+581    0x6448    //TX_FDEQ_GAIN_14
+582    0x6048    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x2015    //TX_FDEQ_BIN_13
+605    0x231C    //TX_FDEQ_BIN_14
+606    0x201C    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-TMOBILE_US-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7E    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x1000    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0020    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0016    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x001C    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x4000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x4000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x1000    //TX_B_LESSCUT_RTO_S_1
+332    0x1000    //TX_B_LESSCUT_RTO_S_2
+333    0x1000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x7FFC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0030    //TX_FDEQ_SUBNUM
+567    0x5652    //TX_FDEQ_GAIN_0
+568    0x504C    //TX_FDEQ_GAIN_1
+569    0x4C4E    //TX_FDEQ_GAIN_2
+570    0x4E4E    //TX_FDEQ_GAIN_3
+571    0x4A46    //TX_FDEQ_GAIN_4
+572    0x4644    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4C4A    //TX_FDEQ_GAIN_7
+575    0x4646    //TX_FDEQ_GAIN_8
+576    0x565A    //TX_FDEQ_GAIN_9
+577    0x5862    //TX_FDEQ_GAIN_10
+578    0x6662    //TX_FDEQ_GAIN_11
+579    0x5C6A    //TX_FDEQ_GAIN_12
+580    0x6E56    //TX_FDEQ_GAIN_13
+581    0x6236    //TX_FDEQ_GAIN_14
+582    0x543A    //TX_FDEQ_GAIN_15
+583    0x5270    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0301    //TX_FDEQ_BIN_0
+592    0x0104    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x2015    //TX_FDEQ_BIN_13
+605    0x231B    //TX_FDEQ_BIN_14
+606    0x221B    //TX_FDEQ_BIN_15
+607    0x100A    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0050    //TX_MIC_CALIBRATION_0
+766    0x0056    //TX_MIC_CALIBRATION_1
+767    0x0050    //TX_MIC_CALIBRATION_2
+768    0x0050    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0042    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0006    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x6000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x08EA    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0CD0    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F00    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x7FFF    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0000    //TX_MIC1MUTE_RATIO_THR
+940    0x02A8    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x05A0    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x000C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSET-HANDSET_HAC-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0000    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0076    //TX_PATCH_REG
+3    0x6F7F    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0002    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0002    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3A66    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0AAC    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7900    //TX_EAD_THR
+151    0x2000    //TX_THR_RE_EST
+152    0x0400    //TX_MIN_EQ_RE_EST_0
+153    0x0400    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x1000    //TX_MIN_EQ_RE_EST_4
+157    0x1000    //TX_MIN_EQ_RE_EST_5
+158    0x1000    //TX_MIN_EQ_RE_EST_6
+159    0x1000    //TX_MIN_EQ_RE_EST_7
+160    0x1000    //TX_MIN_EQ_RE_EST_8
+161    0x1000    //TX_MIN_EQ_RE_EST_9
+162    0x1000    //TX_MIN_EQ_RE_EST_10
+163    0x1000    //TX_MIN_EQ_RE_EST_11
+164    0x1000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x1000    //TX_LAMBDA_CB_NLE
+167    0x1800    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x003C    //TX_SE_HOLD_N
+170    0x0046    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7FD0    //TX_DTD_THR1_0
+198    0x7F20    //TX_DTD_THR1_1
+199    0x7918    //TX_DTD_THR1_2
+200    0x7F00    //TX_DTD_THR1_3
+201    0x7000    //TX_DTD_THR1_4
+202    0x7F00    //TX_DTD_THR1_5
+203    0x7F00    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x1000    //TX_DTD_THR2_3
+208    0x1000    //TX_DTD_THR2_4
+209    0x1000    //TX_DTD_THR2_5
+210    0x1000    //TX_DTD_THR2_6
+211    0x7FF0    //TX_DTD_THR3
+212    0x0177    //TX_SPK_CUT_K
+213    0x1B58    //TX_DT_CUT_K
+214    0x0100    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0C00    //TX_RATIO_DT_L_TH_LOW
+224    0x2000    //TX_RATIO_DT_H_TH_LOW
+225    0x1800    //TX_RATIO_DT_L_TH_HIGH
+226    0x3000    //TX_RATIO_DT_H_TH_HIGH
+227    0x0A00    //TX_RATIO_DT_L0_TH
+228    0x7000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF600    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFC00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF700    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x0600    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0000    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0014    //TX_NS_LVL_CTRL_0
+282    0x002C    //TX_NS_LVL_CTRL_1
+283    0x0028    //TX_NS_LVL_CTRL_2
+284    0x0020    //TX_NS_LVL_CTRL_3
+285    0x0016    //TX_NS_LVL_CTRL_4
+286    0x0012    //TX_NS_LVL_CTRL_5
+287    0x0020    //TX_NS_LVL_CTRL_6
+288    0x0017    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0018    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0012    //TX_MIN_GAIN_S_4
+294    0x0012    //TX_MIN_GAIN_S_5
+295    0x0018    //TX_MIN_GAIN_S_6
+296    0x0012    //TX_MIN_GAIN_S_7
+297    0x5000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x2000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x1000    //TX_SNRI_SUP_3
+304    0x6000    //TX_SNRI_SUP_4
+305    0x6000    //TX_SNRI_SUP_5
+306    0x1000    //TX_SNRI_SUP_6
+307    0x6000    //TX_SNRI_SUP_7
+308    0x6000    //TX_THR_LFNS
+309    0x0017    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x5000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x7FFF    //TX_B_POST_FILT_1
+324    0x7FFF    //TX_B_POST_FILT_2
+325    0x7FFF    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x7FFF    //TX_B_POST_FILT_6
+329    0x3000    //TX_B_POST_FILT_7
+330    0x1000    //TX_B_LESSCUT_RTO_S_0
+331    0x6000    //TX_B_LESSCUT_RTO_S_1
+332    0x6000    //TX_B_LESSCUT_RTO_S_2
+333    0x6000    //TX_B_LESSCUT_RTO_S_3
+334    0x1000    //TX_B_LESSCUT_RTO_S_4
+335    0x1000    //TX_B_LESSCUT_RTO_S_5
+336    0x1000    //TX_B_LESSCUT_RTO_S_6
+337    0x1000    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x07D0    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1D4C    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x1000    //TX_C_POST_FLT_DT
+359    0x7FFF    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x000A    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x03E8    //TX_NOISE_TH_1
+371    0x0BB8    //TX_NOISE_TH_2
+372    0x2580    //TX_NOISE_TH_3
+373    0x77EC    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x4E20    //TX_NOISE_TH_5_4
+378    0x2EE0    //TX_NOISE_TH_6
+379    0x0014    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x6D60    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x0200    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x3000    //TX_POST_MASK_SUP_HSNE
+392    0x07D0    //TX_TAIL_DET_TH
+393    0x7FFF    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0014    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x2000    //TX_METAL_RTO_THR
+410    0x07D0    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x2328    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x03E8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2800    //TX_BF_RESET_THR_HS
+424    0x0CCD    //TX_SB_RTO_MEAN_TH
+425    0x0300    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x2000    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0990    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0100    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x03E8    //TX_SB_RHO_MEAN2_TH
+441    0x03E8    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x0001    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x001E    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0300    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x2CCC    //TX_DEREVERB_LF_MU
+515    0x3200    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x7FFF    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0010    //TX_WIND_SUPRTO
+540    0x0014    //TX_WNS_MIN_G
+541    0x0600    //TX_WNS_B_POST_FLT
+542    0x3000    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0200    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0022    //TX_FDEQ_SUBNUM
+567    0x605E    //TX_FDEQ_GAIN_0
+568    0x5C54    //TX_FDEQ_GAIN_1
+569    0x5450    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4E48    //TX_FDEQ_GAIN_4
+572    0x4A46    //TX_FDEQ_GAIN_5
+573    0x4E5A    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x464A    //TX_FDEQ_GAIN_8
+576    0x5E5E    //TX_FDEQ_GAIN_9
+577    0x5C66    //TX_FDEQ_GAIN_10
+578    0x6C6C    //TX_FDEQ_GAIN_11
+579    0x666C    //TX_FDEQ_GAIN_12
+580    0x7054    //TX_FDEQ_GAIN_13
+581    0x5A5E    //TX_FDEQ_GAIN_14
+582    0x4044    //TX_FDEQ_GAIN_15
+583    0x4870    //TX_FDEQ_GAIN_16
+584    0x7070    //TX_FDEQ_GAIN_17
+585    0x7070    //TX_FDEQ_GAIN_18
+586    0x7070    //TX_FDEQ_GAIN_19
+587    0x7070    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0404    //TX_FDEQ_BIN_2
+594    0x0202    //TX_FDEQ_BIN_3
+595    0x0503    //TX_FDEQ_BIN_4
+596    0x0808    //TX_FDEQ_BIN_5
+597    0x0406    //TX_FDEQ_BIN_6
+598    0x0B0E    //TX_FDEQ_BIN_7
+599    0x070F    //TX_FDEQ_BIN_8
+600    0x100F    //TX_FDEQ_BIN_9
+601    0x0A10    //TX_FDEQ_BIN_10
+602    0x110C    //TX_FDEQ_BIN_11
+603    0x1512    //TX_FDEQ_BIN_12
+604    0x1614    //TX_FDEQ_BIN_13
+605    0x1423    //TX_FDEQ_BIN_14
+606    0x1936    //TX_FDEQ_BIN_15
+607    0x105C    //TX_FDEQ_BIN_16
+608    0x0C0A    //TX_FDEQ_BIN_17
+609    0x0A0A    //TX_FDEQ_BIN_18
+610    0x0A0A    //TX_FDEQ_BIN_19
+611    0x0A0A    //TX_FDEQ_BIN_20
+612    0x0505    //TX_FDEQ_BIN_21
+613    0x0505    //TX_FDEQ_BIN_22
+614    0x0519    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0A12    //TX_PREEQ_BIN_MIC0_0
+642    0x142D    //TX_PREEQ_BIN_MIC0_1
+643    0x0C0C    //TX_PREEQ_BIN_MIC0_2
+644    0x0C0F    //TX_PREEQ_BIN_MIC0_3
+645    0x0F0F    //TX_PREEQ_BIN_MIC0_4
+646    0x0F09    //TX_PREEQ_BIN_MIC0_5
+647    0x0909    //TX_PREEQ_BIN_MIC0_6
+648    0x0908    //TX_PREEQ_BIN_MIC0_7
+649    0x0714    //TX_PREEQ_BIN_MIC0_8
+650    0x1A08    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0920    //TX_PREEQ_BIN_MIC0_11
+653    0x2020    //TX_PREEQ_BIN_MIC0_12
+654    0x2021    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x5858    //TX_PREEQ_GAIN_MIC1_2
+669    0x5858    //TX_PREEQ_GAIN_MIC1_3
+670    0x5860    //TX_PREEQ_GAIN_MIC1_4
+671    0x6060    //TX_PREEQ_GAIN_MIC1_5
+672    0x6048    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4858    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0204    //TX_PREEQ_BIN_MIC1_1
+692    0x0203    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0603    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0609    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x5339    //TX_PREEQ_BIN_MIC1_8
+699    0x4608    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0920    //TX_PREEQ_BIN_MIC1_11
+702    0x2020    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0030    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005C    //TX_MIC_CALIBRATION_0
+766    0x005C    //TX_MIC_CALIBRATION_1
+767    0x005C    //TX_MIC_CALIBRATION_2
+768    0x005C    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0004    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x7EB8    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x6000    //TX_TDDRC_ALPHA_UP_03
+786    0x2000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0FA0    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x000A    //TX_TDDRC_THRD_1
+856    0x0500    //TX_TDDRC_THRD_2
+857    0x1B00    //TX_TDDRC_THRD_3
+858    0x1000    //TX_TDDRC_SLANT_0
+859    0x4A90    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x098D    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0xECCD    //TX_TFMASKLTH_BINVAD
+873    0xFCCD    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x2000    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x6333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x0810    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6329    //TX_SENDFUNC_REG_MICMUTE
+898    0x0010    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0005    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x1081    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x0028    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x3000    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7EF4    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x6D60    //TX_DTD_THR1_MICMUTE_3
+915    0x5000    //TX_DTD_THR2_MICMUTE_0
+916    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x2000    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x1000    //TX_MICMUTE_C_POST_FLT
+922    0x1F40    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x1F40    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0100    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x3E80    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFFFF    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0x3FFF    //TX_AMS_RESRV_02
+945    0x7918    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x206C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x5800    //RX_THR_PITCH_DET_0
+14    0x5000    //RX_THR_PITCH_DET_1
+15    0x4000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4844    //RX_FDEQ_GAIN_2
+42    0x4B4D    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5254    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5C60    //RX_FDEQ_GAIN_7
+47    0x6468    //RX_FDEQ_GAIN_8
+48    0x6C70    //RX_FDEQ_GAIN_9
+49    0x7474    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7474    //RX_FDEQ_GAIN_12
+52    0x7474    //RX_FDEQ_GAIN_13
+53    0x7474    //RX_FDEQ_GAIN_14
+54    0x7474    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0402    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1E1E    //RX_FDEQ_BIN_11
+75    0x1E1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7000    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01E0    //RX_TDDRC_DRC_GAIN
+38    0x0030    //RX_FDEQ_SUBNUM
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x504A    //RX_FDEQ_GAIN_2
+42    0x4E4E    //RX_FDEQ_GAIN_3
+43    0x4E50    //RX_FDEQ_GAIN_4
+44    0x5054    //RX_FDEQ_GAIN_5
+45    0x5658    //RX_FDEQ_GAIN_6
+46    0x5A5C    //RX_FDEQ_GAIN_7
+47    0x5C5C    //RX_FDEQ_GAIN_8
+48    0x5C5C    //RX_FDEQ_GAIN_9
+49    0x5C5C    //RX_FDEQ_GAIN_10
+50    0x5C5C    //RX_FDEQ_GAIN_11
+51    0x5C5C    //RX_FDEQ_GAIN_12
+52    0x5C5C    //RX_FDEQ_GAIN_13
+53    0x5C5C    //RX_FDEQ_GAIN_14
+54    0x5C5C    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0303    //RX_FDEQ_BIN_3
+67    0x0303    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0303    //RX_FDEQ_BIN_6
+70    0x0303    //RX_FDEQ_BIN_7
+71    0x2A0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x1010    //RX_FDEQ_BIN_11
+75    0x1111    //RX_FDEQ_BIN_12
+76    0x0477    //RX_FDEQ_BIN_13
+77    0x1E1E    //RX_FDEQ_BIN_14
+78    0x202C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x000C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x5800    //RX_THR_PITCH_DET_0
+171    0x5000    //RX_THR_PITCH_DET_1
+172    0x4000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7000    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01E0    //RX_TDDRC_DRC_GAIN
+195    0x0030    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4844    //RX_FDEQ_GAIN_2
+199    0x4B4D    //RX_FDEQ_GAIN_3
+200    0x4E50    //RX_FDEQ_GAIN_4
+201    0x5254    //RX_FDEQ_GAIN_5
+202    0x5658    //RX_FDEQ_GAIN_6
+203    0x5C60    //RX_FDEQ_GAIN_7
+204    0x6468    //RX_FDEQ_GAIN_8
+205    0x6C70    //RX_FDEQ_GAIN_9
+206    0x7474    //RX_FDEQ_GAIN_10
+207    0x7474    //RX_FDEQ_GAIN_11
+208    0x7474    //RX_FDEQ_GAIN_12
+209    0x7474    //RX_FDEQ_GAIN_13
+210    0x7474    //RX_FDEQ_GAIN_14
+211    0x7474    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0402    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1E1E    //RX_FDEQ_BIN_11
+232    0x1E1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E1E    //RX_FDEQ_BIN_14
+235    0x202C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
diff --git a/audio/felix/tuning/fortemedia/HANDSFREE.dat b/audio/felix/tuning/fortemedia/HANDSFREE.dat
index da1a6b0..a3ccc96 100644
--- a/audio/felix/tuning/fortemedia/HANDSFREE.dat
+++ b/audio/felix/tuning/fortemedia/HANDSFREE.dat
Binary files differ
diff --git a/audio/felix/tuning/fortemedia/HANDSFREE.mods b/audio/felix/tuning/fortemedia/HANDSFREE.mods
index ebeb970..56f2787 100644
--- a/audio/felix/tuning/fortemedia/HANDSFREE.mods
+++ b/audio/felix/tuning/fortemedia/HANDSFREE.mods
@@ -1,5276 +1,18 @@
 #PLATFORM_NAME  gChip
 #EXPORT_FLAG  HANDSFREE
-#SINGLE_API_VER  1.1.6
-#SAVE_TIME  2021-10-19 18:57:10
-
-#CASE_NAME  HANDSFREE-HANDSFREE-RESERVE1-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0001    //TX_OPERATION_MODE_0
-1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6B50    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0003    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0E3A    //TX_PGA_0
-28    0x0E3A    //TX_PGA_1
-29    0x0E3A    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0001    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3B33    //TX_DIST2REF_11
-73    0x0A70    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0800    //TX_MIC_REFBLK_VOLUME
-108    0x0CAE    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0015    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7A00    //TX_EAD_THR
-151    0x1000    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x7FFF    //TX_MIN_EQ_RE_EST_1
-154    0x7FFF    //TX_MIN_EQ_RE_EST_2
-155    0x7FFF    //TX_MIN_EQ_RE_EST_3
-156    0x7FFF    //TX_MIN_EQ_RE_EST_4
-157    0x7FFF    //TX_MIN_EQ_RE_EST_5
-158    0x7FFF    //TX_MIN_EQ_RE_EST_6
-159    0x7FFF    //TX_MIN_EQ_RE_EST_7
-160    0x7FFF    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
-164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
-166    0x0CCD    //TX_LAMBDA_CB_NLE
-167    0x7FFF    //TX_C_POST_FLT
-168    0x7FFF    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x0080    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
-198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
-201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
-203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
-205    0x7E00    //TX_DTD_THR2_1
-206    0x5000    //TX_DTD_THR2_2
-207    0x5000    //TX_DTD_THR2_3
-208    0x5000    //TX_DTD_THR2_4
-209    0x5000    //TX_DTD_THR2_5
-210    0x5000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
-214    0x0020    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x7FFF    //TX_DTD_MIC_BLK
-221    0x023E    //TX_ADPT_STRICT_L
-222    0x023E    //TX_ADPT_STRICT_H
-223    0x04B0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x0960    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x7FFF    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0048    //TX_EPD_OFFSET_00
-233    0x0048    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
-235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xFB00    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF800    //TX_THR_SN_EST_7
-250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x2000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
-288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x1400    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x1000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7F80    //TX_LAMBDA_PFILT_S_0
-340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
-343    0x7C00    //TX_LAMBDA_PFILT_S_4
-344    0x7C00    //TX_LAMBDA_PFILT_S_5
-345    0x7C00    //TX_LAMBDA_PFILT_S_6
-346    0x7C00    //TX_LAMBDA_PFILT_S_7
-347    0x01F4    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1EAA    //TX_K_PEPPER_HF
-350    0x0600    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0100    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x4000    //TX_DT_BINVAD_TH_3
-357    0x0BB8    //TX_DT_BINVAD_ENDF
-358    0x0200    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01FF    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x4E20    //TX_NOISE_TH_3
-373    0x4E20    //TX_NOISE_TH_4
-374    0x59D8    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x2710    //TX_NOISE_TH_6
-379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0002    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0033    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x7FFF    //TX_MIN_G_CTRL_SSNS
-409    0x0000    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0230    //TX_NOR_OFF_THR
-498    0x0CCD    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x2000    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x7FFF    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x484D    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4854    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x4A50    //TX_FDEQ_GAIN_6
-574    0x484C    //TX_FDEQ_GAIN_7
-575    0x5256    //TX_FDEQ_GAIN_8
-576    0x5A5A    //TX_FDEQ_GAIN_9
-577    0x6468    //TX_FDEQ_GAIN_10
-578    0x807C    //TX_FDEQ_GAIN_11
-579    0x84AC    //TX_FDEQ_GAIN_12
-580    0xCACA    //TX_FDEQ_GAIN_13
-581    0xCACA    //TX_FDEQ_GAIN_14
-582    0xCACA    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0302    //TX_FDEQ_BIN_2
-594    0x0204    //TX_FDEQ_BIN_3
-595    0x0509    //TX_FDEQ_BIN_4
-596    0x030A    //TX_FDEQ_BIN_5
-597    0x0709    //TX_FDEQ_BIN_6
-598    0x0809    //TX_FDEQ_BIN_7
-599    0x1D0B    //TX_FDEQ_BIN_8
-600    0x0B0B    //TX_FDEQ_BIN_9
-601    0x0B1B    //TX_FDEQ_BIN_10
-602    0x351B    //TX_FDEQ_BIN_11
-603    0x1A0D    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x202F    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484C    //TX_PREEQ_GAIN_MIC0_7
-625    0x5050    //TX_PREEQ_GAIN_MIC0_8
-626    0x5050    //TX_PREEQ_GAIN_MIC0_9
-627    0x545C    //TX_PREEQ_GAIN_MIC0_10
-628    0x6A7A    //TX_PREEQ_GAIN_MIC0_11
-629    0x625C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0202    //TX_PREEQ_BIN_MIC0_0
-642    0x0203    //TX_PREEQ_BIN_MIC0_1
-643    0x0303    //TX_PREEQ_BIN_MIC0_2
-644    0x0304    //TX_PREEQ_BIN_MIC0_3
-645    0x0405    //TX_PREEQ_BIN_MIC0_4
-646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
-650    0x0C10    //TX_PREEQ_BIN_MIC0_9
-651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x3A1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x1812    //TX_PREEQ_BIN_MIC1_0
-691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x080A    //TX_PREEQ_BIN_MIC1_3
-694    0x0B09    //TX_PREEQ_BIN_MIC1_4
-695    0x0A06    //TX_PREEQ_BIN_MIC1_5
-696    0x0606    //TX_PREEQ_BIN_MIC1_6
-697    0x0605    //TX_PREEQ_BIN_MIC1_7
-698    0x050A    //TX_PREEQ_BIN_MIC1_8
-699    0x1505    //TX_PREEQ_BIN_MIC1_9
-700    0x0506    //TX_PREEQ_BIN_MIC1_10
-701    0x0615    //TX_PREEQ_BIN_MIC1_11
-702    0x1516    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x2021    //TX_PREEQ_BIN_MIC1_14
-705    0x2021    //TX_PREEQ_BIN_MIC1_15
-706    0x0800    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x6000    //TX_TDDRC_ALPHA_UP_01
-784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
-785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x4000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0004    //TX_TDDRC_THRD_0
-855    0x0010    //TX_TDDRC_THRD_1
-856    0x0140    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x6C40    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
-861    0x6000    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0D56    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7E56    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF400    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0051    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0081    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00CC    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0143    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0217    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0504    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM2-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0001    //TX_OPERATION_MODE_0
-1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6B58    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0003    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0E3A    //TX_PGA_0
-28    0x0E3A    //TX_PGA_1
-29    0x0E3A    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0001    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3B33    //TX_DIST2REF_11
-73    0x0A70    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0800    //TX_MIC_REFBLK_VOLUME
-108    0x0CAE    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0015    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7A00    //TX_EAD_THR
-151    0x1000    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x7FFF    //TX_MIN_EQ_RE_EST_1
-154    0x7FFF    //TX_MIN_EQ_RE_EST_2
-155    0x7FFF    //TX_MIN_EQ_RE_EST_3
-156    0x7FFF    //TX_MIN_EQ_RE_EST_4
-157    0x7FFF    //TX_MIN_EQ_RE_EST_5
-158    0x7FFF    //TX_MIN_EQ_RE_EST_6
-159    0x7FFF    //TX_MIN_EQ_RE_EST_7
-160    0x7FFF    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
-164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
-166    0x0CCD    //TX_LAMBDA_CB_NLE
-167    0x7FFF    //TX_C_POST_FLT
-168    0x7FFF    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x0080    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
-198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
-201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
-203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
-205    0x7E00    //TX_DTD_THR2_1
-206    0x5000    //TX_DTD_THR2_2
-207    0x5000    //TX_DTD_THR2_3
-208    0x5000    //TX_DTD_THR2_4
-209    0x5000    //TX_DTD_THR2_5
-210    0x5000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
-214    0x0020    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x7FFF    //TX_DTD_MIC_BLK
-221    0x023E    //TX_ADPT_STRICT_L
-222    0x023E    //TX_ADPT_STRICT_H
-223    0x04B0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x0960    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x7FFF    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0048    //TX_EPD_OFFSET_00
-233    0x0048    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
-235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xFB00    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF800    //TX_THR_SN_EST_7
-250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x2000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
-288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x1400    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x1000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7F80    //TX_LAMBDA_PFILT_S_0
-340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
-343    0x7C00    //TX_LAMBDA_PFILT_S_4
-344    0x7C00    //TX_LAMBDA_PFILT_S_5
-345    0x7C00    //TX_LAMBDA_PFILT_S_6
-346    0x7C00    //TX_LAMBDA_PFILT_S_7
-347    0x01F4    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1EAA    //TX_K_PEPPER_HF
-350    0x0600    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0100    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x4000    //TX_DT_BINVAD_TH_3
-357    0x0BB8    //TX_DT_BINVAD_ENDF
-358    0x0200    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01FF    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x4E20    //TX_NOISE_TH_3
-373    0x4E20    //TX_NOISE_TH_4
-374    0x59D8    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x2710    //TX_NOISE_TH_6
-379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0002    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0033    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x7FFF    //TX_MIN_G_CTRL_SSNS
-409    0x0000    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0230    //TX_NOR_OFF_THR
-498    0x0CCD    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x2000    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x7FFF    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x484D    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4854    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x4A50    //TX_FDEQ_GAIN_6
-574    0x484C    //TX_FDEQ_GAIN_7
-575    0x5256    //TX_FDEQ_GAIN_8
-576    0x5A5A    //TX_FDEQ_GAIN_9
-577    0x6468    //TX_FDEQ_GAIN_10
-578    0x807C    //TX_FDEQ_GAIN_11
-579    0x84AC    //TX_FDEQ_GAIN_12
-580    0xCACA    //TX_FDEQ_GAIN_13
-581    0xCACA    //TX_FDEQ_GAIN_14
-582    0xCACA    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0302    //TX_FDEQ_BIN_2
-594    0x0204    //TX_FDEQ_BIN_3
-595    0x0509    //TX_FDEQ_BIN_4
-596    0x030A    //TX_FDEQ_BIN_5
-597    0x0709    //TX_FDEQ_BIN_6
-598    0x0809    //TX_FDEQ_BIN_7
-599    0x1D0B    //TX_FDEQ_BIN_8
-600    0x0B0B    //TX_FDEQ_BIN_9
-601    0x0B1B    //TX_FDEQ_BIN_10
-602    0x351B    //TX_FDEQ_BIN_11
-603    0x1A0D    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x202F    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484C    //TX_PREEQ_GAIN_MIC0_7
-625    0x5050    //TX_PREEQ_GAIN_MIC0_8
-626    0x5050    //TX_PREEQ_GAIN_MIC0_9
-627    0x545C    //TX_PREEQ_GAIN_MIC0_10
-628    0x6A7A    //TX_PREEQ_GAIN_MIC0_11
-629    0x625C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0202    //TX_PREEQ_BIN_MIC0_0
-642    0x0203    //TX_PREEQ_BIN_MIC0_1
-643    0x0303    //TX_PREEQ_BIN_MIC0_2
-644    0x0304    //TX_PREEQ_BIN_MIC0_3
-645    0x0405    //TX_PREEQ_BIN_MIC0_4
-646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
-650    0x0C10    //TX_PREEQ_BIN_MIC0_9
-651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x3A1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x1812    //TX_PREEQ_BIN_MIC1_0
-691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x080A    //TX_PREEQ_BIN_MIC1_3
-694    0x0B09    //TX_PREEQ_BIN_MIC1_4
-695    0x0A06    //TX_PREEQ_BIN_MIC1_5
-696    0x0606    //TX_PREEQ_BIN_MIC1_6
-697    0x0605    //TX_PREEQ_BIN_MIC1_7
-698    0x050A    //TX_PREEQ_BIN_MIC1_8
-699    0x1505    //TX_PREEQ_BIN_MIC1_9
-700    0x0506    //TX_PREEQ_BIN_MIC1_10
-701    0x0615    //TX_PREEQ_BIN_MIC1_11
-702    0x1516    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x2021    //TX_PREEQ_BIN_MIC1_14
-705    0x2021    //TX_PREEQ_BIN_MIC1_15
-706    0x0800    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x6000    //TX_TDDRC_ALPHA_UP_01
-784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
-785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x4000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0004    //TX_TDDRC_THRD_0
-855    0x0010    //TX_TDDRC_THRD_1
-856    0x0140    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x6C40    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
-861    0x6000    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0D56    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7E56    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF400    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x4854    //RX_FDEQ_GAIN_1
-41    0x5C58    //RX_FDEQ_GAIN_2
-42    0x5050    //RX_FDEQ_GAIN_3
-43    0x4852    //RX_FDEQ_GAIN_4
-44    0x4E48    //RX_FDEQ_GAIN_5
-45    0x4E72    //RX_FDEQ_GAIN_6
-46    0x868E    //RX_FDEQ_GAIN_7
-47    0x8E72    //RX_FDEQ_GAIN_8
-48    0x7078    //RX_FDEQ_GAIN_9
-49    0x787A    //RX_FDEQ_GAIN_10
-50    0x9478    //RX_FDEQ_GAIN_11
-51    0x5C6C    //RX_FDEQ_GAIN_12
-52    0x7A78    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0051    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0081    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00CC    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0143    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0217    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0504    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM1-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0001    //TX_OPERATION_MODE_0
-1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6B70    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0003    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0E3A    //TX_PGA_0
-28    0x0E3A    //TX_PGA_1
-29    0x0E3A    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0001    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0002    //TX_MIC_DATA_SRC0
-42    0x0000    //TX_MIC_DATA_SRC1
-43    0x0001    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3B33    //TX_DIST2REF_11
-73    0x0A70    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0800    //TX_MIC_REFBLK_VOLUME
-108    0x0CAE    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0015    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x1800    //TX_THR_PITCH_DET_0
-131    0x1000    //TX_THR_PITCH_DET_1
-132    0x0800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7A00    //TX_EAD_THR
-151    0x1000    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x7FFF    //TX_MIN_EQ_RE_EST_1
-154    0x7FFF    //TX_MIN_EQ_RE_EST_2
-155    0x7FFF    //TX_MIN_EQ_RE_EST_3
-156    0x7FFF    //TX_MIN_EQ_RE_EST_4
-157    0x7FFF    //TX_MIN_EQ_RE_EST_5
-158    0x7FFF    //TX_MIN_EQ_RE_EST_6
-159    0x7FFF    //TX_MIN_EQ_RE_EST_7
-160    0x7FFF    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
-164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
-166    0x0CCD    //TX_LAMBDA_CB_NLE
-167    0x7FFF    //TX_C_POST_FLT
-168    0x7FFF    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x0080    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
-198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
-201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
-203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
-205    0x7E00    //TX_DTD_THR2_1
-206    0x5000    //TX_DTD_THR2_2
-207    0x5000    //TX_DTD_THR2_3
-208    0x5000    //TX_DTD_THR2_4
-209    0x5000    //TX_DTD_THR2_5
-210    0x5000    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
-214    0x0020    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x7FFF    //TX_DTD_MIC_BLK
-221    0x023E    //TX_ADPT_STRICT_L
-222    0x023E    //TX_ADPT_STRICT_H
-223    0x04B0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x0960    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x7FFF    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0048    //TX_EPD_OFFSET_00
-233    0x0048    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
-235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x0000    //TX_DTD_THR1_7
-238    0x0000    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xFB00    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xF800    //TX_THR_SN_EST_6
-249    0xF800    //TX_THR_SN_EST_7
-250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x2000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
-288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x1400    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
-303    0x4000    //TX_SNRI_SUP_3
-304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0018    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
-322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
-328    0x1000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x4000    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7F80    //TX_LAMBDA_PFILT_S_0
-340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
-343    0x7C00    //TX_LAMBDA_PFILT_S_4
-344    0x7C00    //TX_LAMBDA_PFILT_S_5
-345    0x7C00    //TX_LAMBDA_PFILT_S_6
-346    0x7C00    //TX_LAMBDA_PFILT_S_7
-347    0x01F4    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1EAA    //TX_K_PEPPER_HF
-350    0x0600    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0100    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x4000    //TX_DT_BINVAD_TH_3
-357    0x0BB8    //TX_DT_BINVAD_ENDF
-358    0x0200    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01FF    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
-371    0x0DAC    //TX_NOISE_TH_2
-372    0x4E20    //TX_NOISE_TH_3
-373    0x4E20    //TX_NOISE_TH_4
-374    0x59D8    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x2710    //TX_NOISE_TH_6
-379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0002    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0033    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x7FFF    //TX_MIN_G_CTRL_SSNS
-409    0x0000    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0230    //TX_NOR_OFF_THR
-498    0x0CCD    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x2000    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x7FFF    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x484D    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4854    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x4A50    //TX_FDEQ_GAIN_6
-574    0x484C    //TX_FDEQ_GAIN_7
-575    0x5256    //TX_FDEQ_GAIN_8
-576    0x5A5A    //TX_FDEQ_GAIN_9
-577    0x6468    //TX_FDEQ_GAIN_10
-578    0x807C    //TX_FDEQ_GAIN_11
-579    0x84AC    //TX_FDEQ_GAIN_12
-580    0xCACA    //TX_FDEQ_GAIN_13
-581    0xCACA    //TX_FDEQ_GAIN_14
-582    0xCACA    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0302    //TX_FDEQ_BIN_2
-594    0x0204    //TX_FDEQ_BIN_3
-595    0x0509    //TX_FDEQ_BIN_4
-596    0x030A    //TX_FDEQ_BIN_5
-597    0x0709    //TX_FDEQ_BIN_6
-598    0x0809    //TX_FDEQ_BIN_7
-599    0x1D0B    //TX_FDEQ_BIN_8
-600    0x0B0B    //TX_FDEQ_BIN_9
-601    0x0B1B    //TX_FDEQ_BIN_10
-602    0x351B    //TX_FDEQ_BIN_11
-603    0x1A0D    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x202F    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484C    //TX_PREEQ_GAIN_MIC0_7
-625    0x5050    //TX_PREEQ_GAIN_MIC0_8
-626    0x5050    //TX_PREEQ_GAIN_MIC0_9
-627    0x545C    //TX_PREEQ_GAIN_MIC0_10
-628    0x6A7A    //TX_PREEQ_GAIN_MIC0_11
-629    0x625C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0202    //TX_PREEQ_BIN_MIC0_0
-642    0x0203    //TX_PREEQ_BIN_MIC0_1
-643    0x0303    //TX_PREEQ_BIN_MIC0_2
-644    0x0304    //TX_PREEQ_BIN_MIC0_3
-645    0x0405    //TX_PREEQ_BIN_MIC0_4
-646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
-650    0x0C10    //TX_PREEQ_BIN_MIC0_9
-651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x3A1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0030    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x1812    //TX_PREEQ_BIN_MIC1_0
-691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x080A    //TX_PREEQ_BIN_MIC1_3
-694    0x0B09    //TX_PREEQ_BIN_MIC1_4
-695    0x0A06    //TX_PREEQ_BIN_MIC1_5
-696    0x0606    //TX_PREEQ_BIN_MIC1_6
-697    0x0605    //TX_PREEQ_BIN_MIC1_7
-698    0x050A    //TX_PREEQ_BIN_MIC1_8
-699    0x1505    //TX_PREEQ_BIN_MIC1_9
-700    0x0506    //TX_PREEQ_BIN_MIC1_10
-701    0x0615    //TX_PREEQ_BIN_MIC1_11
-702    0x1516    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x2021    //TX_PREEQ_BIN_MIC1_14
-705    0x2021    //TX_PREEQ_BIN_MIC1_15
-706    0x0800    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x6000    //TX_TDDRC_ALPHA_UP_01
-784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
-785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
-790    0x4000    //TX_TDDRC_ALPHA_DWN_04
-791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
-818    0x0078    //TX_DEADMIC_CNT
-819    0x0078    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0096    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0004    //TX_TDDRC_THRD_0
-855    0x0010    //TX_TDDRC_THRD_1
-856    0x0140    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x6C40    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
-861    0x6000    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0D56    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x006C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7E56    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0400    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0014    //RX_NS_LVL_CTRL
-23    0xF400    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x4854    //RX_FDEQ_GAIN_1
-41    0x5C58    //RX_FDEQ_GAIN_2
-42    0x5050    //RX_FDEQ_GAIN_3
-43    0x4852    //RX_FDEQ_GAIN_4
-44    0x4E48    //RX_FDEQ_GAIN_5
-45    0x4E72    //RX_FDEQ_GAIN_6
-46    0x868E    //RX_FDEQ_GAIN_7
-47    0x8E72    //RX_FDEQ_GAIN_8
-48    0x7078    //RX_FDEQ_GAIN_9
-49    0x787A    //RX_FDEQ_GAIN_10
-50    0x9478    //RX_FDEQ_GAIN_11
-51    0x5C6C    //RX_FDEQ_GAIN_12
-52    0x7A78    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0034    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0051    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0081    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00CC    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0143    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0217    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0504    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+#SINGLE_API_VER  1.2.1
+#SAVE_TIME  2023-03-24 17:27:48
 
 #CASE_NAME  HANDSFREE-HANDSFREE-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6F78    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0000    //TX_SAMPLINGFREQ_SIG
 7    0x0000    //TX_SAMPLINGFREQ_PROC
@@ -5287,8 +29,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -5413,31 +155,31 @@
 144    0x0000    //TX_PP_RESRV_6
 145    0x0000    //TX_PP_RESRV_7
 146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
+147    0x0100    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7800    //TX_EAD_THR
+150    0x7E00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x1000    //TX_MIN_EQ_RE_EST_1
-154    0x2000    //TX_MIN_EQ_RE_EST_2
-155    0x1000    //TX_MIN_EQ_RE_EST_3
-156    0x0800    //TX_MIN_EQ_RE_EST_4
-157    0x0800    //TX_MIN_EQ_RE_EST_5
-158    0x0800    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x0800    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
+152    0x0200    //TX_MIN_EQ_RE_EST_0
+153    0x0200    //TX_MIN_EQ_RE_EST_1
+154    0x0200    //TX_MIN_EQ_RE_EST_2
+155    0x0200    //TX_MIN_EQ_RE_EST_3
+156    0x0200    //TX_MIN_EQ_RE_EST_4
+157    0x0200    //TX_MIN_EQ_RE_EST_5
+158    0x0200    //TX_MIN_EQ_RE_EST_6
+159    0x1800    //TX_MIN_EQ_RE_EST_7
+160    0x1800    //TX_MIN_EQ_RE_EST_8
+161    0x3000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x6000    //TX_MIN_EQ_RE_EST_11
 164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x2000    //TX_LAMBDA_RE_EST
+165    0x4000    //TX_LAMBDA_RE_EST
 166    0x0000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x2000    //TX_GAIN_NP
 169    0x0180    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x0000    //TX_DT2_HOLD_N
+171    0x0080    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -5464,13 +206,13 @@
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
 197    0x7FF0    //TX_DTD_THR1_0
-198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
+198    0x79E0    //TX_DTD_THR1_1
+199    0x6D60    //TX_DTD_THR1_2
+200    0x73A0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
+204    0x0CCD    //TX_DTD_THR2_0
 205    0x0CCD    //TX_DTD_THR2_1
 206    0x0CCD    //TX_DTD_THR2_2
 207    0x0CCD    //TX_DTD_THR2_3
@@ -5479,7 +221,7 @@
 210    0x0CCD    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x0DAC    //TX_DT_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
 214    0x0100    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
@@ -5489,19 +231,19 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x1000    //TX_ADPT_STRICT_L
 222    0x1000    //TX_ADPT_STRICT_H
-223    0x0FA0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x1F40    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x07D0    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x028A    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x1000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0008    //TX_EPD_OFFSET_00
-233    0x0008    //TX_EPD_OFFST_01
-234    0x0FA0    //TX_RATIO_DT_L0_TH_HIGH
-235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x01F4    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
 238    0x0000    //TX_DTD_THR2_7
@@ -5510,19 +252,19 @@
 241    0x0000    //TX_DT_RESRV_9
 242    0xF800    //TX_THR_SN_EST_0
 243    0xFA00    //TX_THR_SN_EST_1
-244    0xFD00    //TX_THR_SN_EST_2
+244    0xFA00    //TX_THR_SN_EST_2
 245    0xF900    //TX_THR_SN_EST_3
 246    0xFA00    //TX_THR_SN_EST_4
 247    0xFA00    //TX_THR_SN_EST_5
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0050    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -5548,31 +290,31 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0012    //TX_NS_LVL_CTRL_1
-283    0x0017    //TX_NS_LVL_CTRL_2
-284    0x0015    //TX_NS_LVL_CTRL_3
+282    0x0017    //TX_NS_LVL_CTRL_1
+283    0x001A    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
 285    0x0012    //TX_NS_LVL_CTRL_4
-286    0x0012    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0012    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
-290    0x000F    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000F    //TX_MIN_GAIN_S_2
 292    0x000F    //TX_MIN_GAIN_S_3
 293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000F    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x000F    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
-297    0x4000    //TX_NMOS_SUP
+297    0x3C00    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x2000    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x4000    //TX_SNRI_SUP_2
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x1000    //TX_SNRI_SUP_1
+302    0x3000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x3000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -5581,19 +323,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x5000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x3000    //TX_A_POST_FILT_S_5
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x1000    //TX_A_POST_FILT_S_2
+317    0x1000    //TX_A_POST_FILT_S_3
+318    0x3000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
 320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
-324    0x3000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x3000    //TX_B_POST_FILT_5
+324    0x1000    //TX_B_POST_FILT_2
+325    0x3000    //TX_B_POST_FILT_3
+326    0x3000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -5605,13 +347,13 @@
 336    0x6000    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7E00    //TX_LAMBDA_PFILT
-339    0x7F00    //TX_LAMBDA_PFILT_S_0
-340    0x7900    //TX_LAMBDA_PFILT_S_1
-341    0x7400    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
+339    0x7D00    //TX_LAMBDA_PFILT_S_0
+340    0x7400    //TX_LAMBDA_PFILT_S_1
+341    0x7D00    //TX_LAMBDA_PFILT_S_2
+342    0x7000    //TX_LAMBDA_PFILT_S_3
 343    0x7D00    //TX_LAMBDA_PFILT_S_4
 344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
+345    0x7900    //TX_LAMBDA_PFILT_S_6
 346    0x7D00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0800    //TX_A_PEPPER
@@ -5619,37 +361,37 @@
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
-353    0x0040    //TX_DT_BINVAD_TH_0
-354    0x0100    //TX_DT_BINVAD_TH_1
-355    0x0400    //TX_DT_BINVAD_TH_2
-356    0x2000    //TX_DT_BINVAD_TH_3
-357    0x0FA0    //TX_DT_BINVAD_ENDF
-358    0x0080    //TX_C_POST_FLT_DT
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x0BB8    //TX_DT_BINVAD_ENDF
+358    0x0400    //TX_C_POST_FLT_DT
 359    0x4000    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01B0    //TX_DT_BOOST
+360    0x0100    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
 362    0x0005    //TX_BF_DVG_TH
 363    0x001E    //TX_SN_C_F
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0019    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
+370    0x1388    //TX_NOISE_TH_1
 371    0x03ED    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x55F0    //TX_NOISE_TH_4
+372    0x59D8    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
 374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x0FA0    //TX_NOISE_TH_6
+378    0x4650    //TX_NOISE_TH_6
 379    0x000A    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -5657,17 +399,17 @@
 388    0x1000    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7000    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0003    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -5775,21 +517,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -5818,31 +560,31 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
-567    0x4E4E    //TX_FDEQ_GAIN_0
-568    0x4E4D    //TX_FDEQ_GAIN_1
-569    0x4D4D    //TX_FDEQ_GAIN_2
-570    0x4D48    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
-573    0x5248    //TX_FDEQ_GAIN_6
-574    0x403E    //TX_FDEQ_GAIN_7
-575    0x3C3C    //TX_FDEQ_GAIN_8
-576    0x3C3C    //TX_FDEQ_GAIN_9
+567    0x5854    //TX_FDEQ_GAIN_0
+568    0x4C48    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4A43    //TX_FDEQ_GAIN_3
+571    0x374B    //TX_FDEQ_GAIN_4
+572    0x3444    //TX_FDEQ_GAIN_5
+573    0x433C    //TX_FDEQ_GAIN_6
+574    0x3436    //TX_FDEQ_GAIN_7
+575    0x2C2E    //TX_FDEQ_GAIN_8
+576    0x3234    //TX_FDEQ_GAIN_9
 577    0x4848    //TX_FDEQ_GAIN_10
 578    0x4848    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
@@ -5860,13 +602,13 @@
 591    0x0202    //TX_FDEQ_BIN_0
 592    0x0203    //TX_FDEQ_BIN_1
 593    0x0303    //TX_FDEQ_BIN_2
-594    0x0403    //TX_FDEQ_BIN_3
+594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0805    //TX_FDEQ_BIN_6
-598    0x070E    //TX_FDEQ_BIN_7
-599    0x0B0E    //TX_FDEQ_BIN_8
-600    0x0B0E    //TX_FDEQ_BIN_9
+597    0x0906    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x0000    //TX_FDEQ_BIN_10
 602    0x0000    //TX_FDEQ_BIN_11
 603    0x0000    //TX_FDEQ_BIN_12
@@ -5891,8 +633,8 @@
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
 624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x484A    //TX_PREEQ_GAIN_MIC0_8
-626    0x4C50    //TX_PREEQ_GAIN_MIC0_9
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
 627    0x4848    //TX_PREEQ_GAIN_MIC0_10
 628    0x4848    //TX_PREEQ_GAIN_MIC0_11
 629    0x4848    //TX_PREEQ_GAIN_MIC0_12
@@ -5916,7 +658,7 @@
 647    0x0708    //TX_PREEQ_BIN_MIC0_6
 648    0x090A    //TX_PREEQ_BIN_MIC0_7
 649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D08    //TX_PREEQ_BIN_MIC0_9
+650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0000    //TX_PREEQ_BIN_MIC0_10
 652    0x0000    //TX_PREEQ_BIN_MIC0_11
 653    0x0000    //TX_PREEQ_BIN_MIC0_12
@@ -5939,9 +681,9 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+673    0x4A4A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4B4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4D4E    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
 678    0x4848    //TX_PREEQ_GAIN_MIC1_12
@@ -5956,16 +698,16 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C08    //TX_PREEQ_BIN_MIC1_2
-693    0x0700    //TX_PREEQ_BIN_MIC1_3
-694    0x0000    //TX_PREEQ_BIN_MIC1_4
-695    0x0000    //TX_PREEQ_BIN_MIC1_5
-696    0x0000    //TX_PREEQ_BIN_MIC1_6
-697    0x0000    //TX_PREEQ_BIN_MIC1_7
-698    0x0000    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
 700    0x0000    //TX_PREEQ_BIN_MIC1_10
 701    0x0000    //TX_PREEQ_BIN_MIC1_11
 702    0x0000    //TX_PREEQ_BIN_MIC1_12
@@ -5987,10 +729,10 @@
 718    0x4848    //TX_PREEQ_GAIN_MIC2_3
 719    0x4848    //TX_PREEQ_GAIN_MIC2_4
 720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+721    0x484A    //TX_PREEQ_GAIN_MIC2_6
+722    0x4B4B    //TX_PREEQ_GAIN_MIC2_7
+723    0x4B4C    //TX_PREEQ_GAIN_MIC2_8
+724    0x4D50    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
 727    0x4848    //TX_PREEQ_GAIN_MIC2_12
@@ -6005,16 +747,16 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x7800    //TX_PREEQ_BIN_MIC2_0
-740    0x0000    //TX_PREEQ_BIN_MIC2_1
-741    0x0000    //TX_PREEQ_BIN_MIC2_2
-742    0x0000    //TX_PREEQ_BIN_MIC2_3
-743    0x0000    //TX_PREEQ_BIN_MIC2_4
-744    0x0000    //TX_PREEQ_BIN_MIC2_5
-745    0x0000    //TX_PREEQ_BIN_MIC2_6
-746    0x0000    //TX_PREEQ_BIN_MIC2_7
-747    0x0000    //TX_PREEQ_BIN_MIC2_8
-748    0x0000    //TX_PREEQ_BIN_MIC2_9
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0708    //TX_PREEQ_BIN_MIC2_6
+746    0x090A    //TX_PREEQ_BIN_MIC2_7
+747    0x0B0C    //TX_PREEQ_BIN_MIC2_8
+748    0x0D0E    //TX_PREEQ_BIN_MIC2_9
 749    0x0000    //TX_PREEQ_BIN_MIC2_10
 750    0x0000    //TX_PREEQ_BIN_MIC2_11
 751    0x0000    //TX_PREEQ_BIN_MIC2_12
@@ -6031,18 +773,18 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0044    //TX_MIC_PWR_BIAS_0
 770    0x0044    //TX_MIC_PWR_BIAS_1
 771    0x0044    //TX_MIC_PWR_BIAS_2
 772    0x0044    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
 774    0x0003    //TX_GAIN_LIMIT_1
-775    0x0006    //TX_GAIN_LIMIT_2
-776    0x0006    //TX_GAIN_LIMIT_3
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -6050,12 +792,12 @@
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
 783    0x6000    //TX_TDDRC_ALPHA_UP_01
-784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
-785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
+785    0x4000    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
 788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+789    0x4000    //TX_TDDRC_ALPHA_DWN_03
 790    0x4000    //TX_TDDRC_ALPHA_DWN_04
 791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
@@ -6082,8 +824,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -6120,19 +862,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0006    //TX_TDDRC_THRD_0
-855    0x0012    //TX_TDDRC_THRD_1
-856    0x1200    //TX_TDDRC_THRD_2
-857    0x1C60    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0C60    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -6157,22 +899,87 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x0217    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7918    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xCD38    //TX_AMS_RESRV_02
+945    0x2710    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x047C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
 11    0x7652    //RX_A_HP
@@ -6186,14 +993,14 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
@@ -6203,16 +1010,16 @@
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x4E4F    //RX_FDEQ_GAIN_1
+41    0x4743    //RX_FDEQ_GAIN_2
+42    0x454C    //RX_FDEQ_GAIN_3
+43    0x4C49    //RX_FDEQ_GAIN_4
+44    0x584A    //RX_FDEQ_GAIN_5
+45    0x4642    //RX_FDEQ_GAIN_6
+46    0x4043    //RX_FDEQ_GAIN_7
+47    0x454A    //RX_FDEQ_GAIN_8
+48    0x4C53    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6228,15 +1035,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0107    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6275,25 +1082,25 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
+111    0x0005    //RX_FILTINDX
+112    0x0002    //RX_TDDRC_THRD_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x13E0    //RX_TPKA_FP
+126    0x10D3    //RX_TPKA_FP
 127    0x0400    //RX_MIN_G_FP
-128    0x0A10    //RX_MAX_G_FP
-129    0x004E    //RX_SPK_VOL
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -6322,40 +1129,40 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x05E3    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6371,15 +1178,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6418,43 +1225,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x004E    //RX_SPK_VOL
+129    0x000C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6470,15 +1277,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6517,43 +1324,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x007A    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x062A    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6569,15 +1376,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6616,43 +1423,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00BD    //RX_SPK_VOL
+129    0x001C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x4000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1B60    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0127    //RX_TDDRC_DRC_GAIN
+124    0x0607    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6668,15 +1475,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6715,43 +1522,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x002E    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x4000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1B60    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01CE    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x6058    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5E58    //RX_FDEQ_GAIN_4
-44    0x584E    //RX_FDEQ_GAIN_5
-45    0x5450    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6767,15 +1574,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6814,43 +1621,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x004A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x4000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1B60    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02E3    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x605A    //RX_FDEQ_GAIN_2
-42    0x6666    //RX_FDEQ_GAIN_3
-43    0x6460    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6866,15 +1673,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -6913,43 +1720,43 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0082    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x4000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0007    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1B60    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0xA8A8    //RX_FDEQ_GAIN_0
-40    0x7658    //RX_FDEQ_GAIN_1
-41    0x605A    //RX_FDEQ_GAIN_2
-42    0x6666    //RX_FDEQ_GAIN_3
-43    0x6460    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4854    //RX_FDEQ_GAIN_8
-48    0x5454    //RX_FDEQ_GAIN_9
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -6965,15 +1772,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0303    //RX_FDEQ_BIN_1
-65    0x0202    //RX_FDEQ_BIN_2
-66    0x0705    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B14    //RX_FDEQ_BIN_8
-72    0x0B08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -7014,16 +1821,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0005    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0015    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0082    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HANDSFREE-HANDSFREE-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6F78    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0001    //TX_SAMPLINGFREQ_SIG
 7    0x0001    //TX_SAMPLINGFREQ_PROC
@@ -7040,8 +2699,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -7126,8 +2785,8 @@
 104    0x0000    //TX_MIC_LOC_23
 105    0x0000    //TX_MIC_LOC_24
 106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0C00    //TX_MIC_BLOCK_VOLUME
 109    0x0000    //TX_INVERSE_MASK
 110    0x0000    //TX_ADCS_MASK
 111    0x04D0    //TX_ADCS_GAIN
@@ -7166,31 +2825,31 @@
 144    0x0000    //TX_PP_RESRV_6
 145    0x0000    //TX_PP_RESRV_7
 146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
+147    0x0300    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6800    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
+150    0x6C00    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x0200    //TX_MIN_EQ_RE_EST_0
 153    0x2000    //TX_MIN_EQ_RE_EST_1
-154    0x4000    //TX_MIN_EQ_RE_EST_2
-155    0x6000    //TX_MIN_EQ_RE_EST_3
-156    0x6000    //TX_MIN_EQ_RE_EST_4
-157    0x7FFF    //TX_MIN_EQ_RE_EST_5
-158    0x7FFF    //TX_MIN_EQ_RE_EST_6
-159    0x7FFF    //TX_MIN_EQ_RE_EST_7
-160    0x7FFF    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
-164    0x7FFF    //TX_MIN_EQ_RE_EST_12
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x2000    //TX_MIN_EQ_RE_EST_3
+156    0x2000    //TX_MIN_EQ_RE_EST_4
+157    0x2000    //TX_MIN_EQ_RE_EST_5
+158    0x4000    //TX_MIN_EQ_RE_EST_6
+159    0x4000    //TX_MIN_EQ_RE_EST_7
+160    0x4000    //TX_MIN_EQ_RE_EST_8
+161    0x4000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x4000    //TX_MIN_EQ_RE_EST_11
+164    0x4000    //TX_MIN_EQ_RE_EST_12
 165    0x4000    //TX_LAMBDA_RE_EST
-166    0x0800    //TX_LAMBDA_CB_NLE
+166    0x4000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x5000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+169    0x02A0    //TX_SE_HOLD_N
+170    0x0060    //TX_DT_HOLD_N
+171    0x00C0    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -7216,15 +2875,15 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x76D0    //TX_DTD_THR1_0
-198    0x76D0    //TX_DTD_THR1_1
-199    0x76D0    //TX_DTD_THR1_2
+197    0x79E0    //TX_DTD_THR1_0
+198    0x7C38    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
-205    0x7E00    //TX_DTD_THR2_1
+204    0x5000    //TX_DTD_THR2_0
+205    0x5000    //TX_DTD_THR2_1
 206    0x5000    //TX_DTD_THR2_2
 207    0x5000    //TX_DTD_THR2_3
 208    0x5000    //TX_DTD_THR2_4
@@ -7232,8 +2891,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
-214    0x0001    //TX_DT_CUT_THR
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -7242,18 +2901,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x03E8    //TX_RATIO_DT_L_TH_LOW
-224    0x251C    //TX_RATIO_DT_H_TH_LOW
-225    0x07D0    //TX_RATIO_DT_L_TH_HIGH
-226    0x31CE    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x5000    //TX_B_POST_FILT_ECHO_L
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x0A98    //TX_RATIO_DT_H_TH_LOW
+225    0x0320    //TX_RATIO_DT_L_TH_HIGH
+226    0x1388    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x6000    //TX_B_POST_FILT_ECHO_L
 229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0016    //TX_EPD_OFFSET_00
-233    0x0016    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x012C    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -7270,11 +2929,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -7302,16 +2961,16 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
 291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0014    //TX_MIN_GAIN_S_3
+292    0x0010    //TX_MIN_GAIN_S_3
 293    0x0010    //TX_MIN_GAIN_S_4
 294    0x0010    //TX_MIN_GAIN_S_5
 295    0x0010    //TX_MIN_GAIN_S_6
@@ -7319,13 +2978,13 @@
 297    0x6000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x2000    //TX_SNRI_SUP_0
+300    0x7FFF    //TX_SNRI_SUP_0
 301    0x4000    //TX_SNRI_SUP_1
 302    0x4000    //TX_SNRI_SUP_2
-303    0x1800    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -7334,19 +2993,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x1C00    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -7354,14 +3013,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -7372,14 +3031,14 @@
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
-353    0x0100    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0400    //TX_DT_BINVAD_TH_2
+353    0x0200    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
 356    0x2000    //TX_DT_BINVAD_TH_3
-357    0x0DAC    //TX_DT_BINVAD_ENDF
-358    0x0400    //TX_C_POST_FLT_DT
+357    0x0BB8    //TX_DT_BINVAD_ENDF
+358    0x2000    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01B0    //TX_DT_BOOST
+360    0x0140    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
 362    0x0005    //TX_BF_DVG_TH
 363    0x001E    //TX_SN_C_F
@@ -7389,20 +3048,20 @@
 367    0x0032    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x0578    //TX_NOISE_TH_1
+370    0x017E    //TX_NOISE_TH_1
 371    0x0230    //TX_NOISE_TH_2
-372    0x4A38    //TX_NOISE_TH_3
+372    0x3492    //TX_NOISE_TH_3
 373    0x4E20    //TX_NOISE_TH_4
 374    0x55B8    //TX_NOISE_TH_5
-375    0x7148    //TX_NOISE_TH_5_2
+375    0x49E6    //TX_NOISE_TH_5_2
 376    0x0001    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0F0A    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -7410,17 +3069,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7FFF    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0005    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -7528,21 +3187,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0008    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -7571,35 +3230,35 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x001C    //TX_FDEQ_SUBNUM
-567    0x4E4E    //TX_FDEQ_GAIN_0
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x5048    //TX_FDEQ_GAIN_0
 568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4D4D    //TX_FDEQ_GAIN_2
-570    0x4D48    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4A48    //TX_FDEQ_GAIN_5
-573    0x5248    //TX_FDEQ_GAIN_6
-574    0x4844    //TX_FDEQ_GAIN_7
-575    0x4444    //TX_FDEQ_GAIN_8
-576    0x4048    //TX_FDEQ_GAIN_9
-577    0x4848    //TX_FDEQ_GAIN_10
-578    0x5050    //TX_FDEQ_GAIN_11
+569    0x4A4F    //TX_FDEQ_GAIN_2
+570    0x4E48    //TX_FDEQ_GAIN_3
+571    0x4444    //TX_FDEQ_GAIN_4
+572    0x4450    //TX_FDEQ_GAIN_5
+573    0x5452    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x4A4C    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4850    //TX_FDEQ_GAIN_10
+578    0x5454    //TX_FDEQ_GAIN_11
 579    0x5454    //TX_FDEQ_GAIN_12
-580    0x5858    //TX_FDEQ_GAIN_13
+580    0x5454    //TX_FDEQ_GAIN_13
 581    0x4848    //TX_FDEQ_GAIN_14
 582    0x4848    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
@@ -7613,17 +3272,17 @@
 591    0x0202    //TX_FDEQ_BIN_0
 592    0x0203    //TX_FDEQ_BIN_1
 593    0x0303    //TX_FDEQ_BIN_2
-594    0x0403    //TX_FDEQ_BIN_3
+594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
-596    0x0509    //TX_FDEQ_BIN_5
-597    0x0901    //TX_FDEQ_BIN_6
-598    0x070E    //TX_FDEQ_BIN_7
-599    0x0B0E    //TX_FDEQ_BIN_8
-600    0x0B0E    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x1011    //TX_FDEQ_BIN_12
-604    0x1112    //TX_FDEQ_BIN_13
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x0F10    //TX_FDEQ_BIN_10
+602    0x1011    //TX_FDEQ_BIN_11
+603    0x1112    //TX_FDEQ_BIN_12
+604    0x120B    //TX_FDEQ_BIN_13
 605    0x0000    //TX_FDEQ_BIN_14
 606    0x0000    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
@@ -7644,12 +3303,12 @@
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
 624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x484A    //TX_PREEQ_GAIN_MIC0_8
-626    0x4C50    //TX_PREEQ_GAIN_MIC0_9
-627    0x5050    //TX_PREEQ_GAIN_MIC0_10
-628    0x5054    //TX_PREEQ_GAIN_MIC0_11
-629    0x585C    //TX_PREEQ_GAIN_MIC0_12
-630    0x5C64    //TX_PREEQ_GAIN_MIC0_13
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
 631    0x4848    //TX_PREEQ_GAIN_MIC0_14
 632    0x4848    //TX_PREEQ_GAIN_MIC0_15
 633    0x4848    //TX_PREEQ_GAIN_MIC0_16
@@ -7672,8 +3331,8 @@
 650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0F10    //TX_PREEQ_BIN_MIC0_10
 652    0x1011    //TX_PREEQ_BIN_MIC0_11
-653    0x1104    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
+653    0x1112    //TX_PREEQ_BIN_MIC0_12
+654    0x120B    //TX_PREEQ_BIN_MIC0_13
 655    0x0000    //TX_PREEQ_BIN_MIC0_14
 656    0x0000    //TX_PREEQ_BIN_MIC0_15
 657    0x0000    //TX_PREEQ_BIN_MIC0_16
@@ -7692,13 +3351,13 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+673    0x484A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4C4E    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5454    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
 680    0x4848    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
@@ -7709,20 +3368,20 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x0700    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0F10    //TX_PREEQ_BIN_MIC1_10
+701    0x1011    //TX_PREEQ_BIN_MIC1_11
+702    0x1112    //TX_PREEQ_BIN_MIC1_12
+703    0x120B    //TX_PREEQ_BIN_MIC1_13
 704    0x0000    //TX_PREEQ_BIN_MIC1_14
 705    0x0000    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
@@ -7737,19 +3396,19 @@
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+718    0x484A    //TX_PREEQ_GAIN_MIC2_3
+719    0x4B4A    //TX_PREEQ_GAIN_MIC2_4
+720    0x4B4C    //TX_PREEQ_GAIN_MIC2_5
+721    0x4C4D    //TX_PREEQ_GAIN_MIC2_6
+722    0x4F50    //TX_PREEQ_GAIN_MIC2_7
+723    0x5050    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5252    //TX_PREEQ_GAIN_MIC2_10
+726    0x5253    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x5454    //TX_PREEQ_GAIN_MIC2_13
+729    0x5455    //TX_PREEQ_GAIN_MIC2_14
+730    0x5555    //TX_PREEQ_GAIN_MIC2_15
 731    0x4848    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
@@ -7773,7 +3432,7 @@
 751    0x0808    //TX_PREEQ_BIN_MIC2_12
 752    0x0808    //TX_PREEQ_BIN_MIC2_13
 753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
+754    0x0808    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
@@ -7784,18 +3443,18 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
 770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
 774    0x0003    //TX_GAIN_LIMIT_1
-775    0x0006    //TX_GAIN_LIMIT_2
-776    0x0006    //TX_GAIN_LIMIT_3
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0009    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -7807,8 +3466,8 @@
 785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
 790    0x4000    //TX_TDDRC_ALPHA_DWN_04
 791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
@@ -7835,8 +3494,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -7875,17 +3534,17 @@
 853    0x0002    //TX_FILTINDX
 854    0x0004    //TX_TDDRC_THRD_0
 855    0x0010    //TX_TDDRC_THRD_1
-856    0x1200    //TX_TDDRC_THRD_2
-857    0x1C60    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
 860    0x4000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0E75    //TX_TDDRC_DRC_GAIN
+866    0x0F23    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -7910,14 +3569,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0230    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7DC8    //TX_DTD_THR1_MICMUTE_0
+912    0x733C    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xD8F0    //TX_AMS_RESRV_02
+945    0x2EE0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x047C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -7925,7 +3649,7 @@
 5    0x0000    //RX_DELAY_OPT
 6    0x6000    //RX_TDDRC_ALPHA_UP_1
 7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
 11    0x7B02    //RX_A_HP
@@ -7939,13 +3663,13 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
@@ -7955,23 +3679,23 @@
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x847A    //RX_FDEQ_GAIN_0
+40    0x6C66    //RX_FDEQ_GAIN_1
+41    0x6868    //RX_FDEQ_GAIN_2
+42    0x7084    //RX_FDEQ_GAIN_3
+43    0x7E82    //RX_FDEQ_GAIN_4
+44    0x7874    //RX_FDEQ_GAIN_5
+45    0x5864    //RX_FDEQ_GAIN_6
+46    0x625C    //RX_FDEQ_GAIN_7
+47    0x5C50    //RX_FDEQ_GAIN_8
+48    0x545A    //RX_FDEQ_GAIN_9
+49    0x5C58    //RX_FDEQ_GAIN_10
+50    0x5858    //RX_FDEQ_GAIN_11
+51    0x6460    //RX_FDEQ_GAIN_12
+52    0x5048    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -7980,22 +3704,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
-72    0x0A0A    //RX_FDEQ_BIN_9
-73    0x0A0A    //RX_FDEQ_BIN_10
-74    0x0A0A    //RX_FDEQ_BIN_11
-75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+63    0x0401    //RX_FDEQ_BIN_0
+64    0x0104    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0202    //RX_FDEQ_BIN_3
+67    0x0704    //RX_FDEQ_BIN_4
+68    0x0605    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1006    //RX_FDEQ_BIN_10
+74    0x1614    //RX_FDEQ_BIN_11
+75    0x1414    //RX_FDEQ_BIN_12
+76    0x1404    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8030,23 +3754,23 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 111    0x0004    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
+113    0x0002    //RX_TDDRC_THRD_1
 114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
+115    0x0CE0    //RX_TDDRC_THRD_3
 116    0x0000    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x03FC    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x13E0    //RX_TPKA_FP
+126    0x1134    //RX_TPKA_FP
 127    0x0400    //RX_MIN_G_FP
-128    0x0800    //RX_MAX_G_FP
-129    0x0042    //RX_SPK_VOL
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -8075,46 +3799,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x0607    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8124,21 +3848,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8171,49 +3895,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0042    //RX_SPK_VOL
+129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8223,21 +3947,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8270,49 +3994,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0066    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8322,21 +4046,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8369,49 +4093,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00A1    //RX_SPK_VOL
+129    0x001C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x0607    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8421,21 +4145,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8468,49 +4192,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x002D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8520,21 +4244,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8567,49 +4291,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x004B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0003    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0293    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x7488    //RX_FDEQ_GAIN_8
-48    0x7E80    //RX_FDEQ_GAIN_9
-49    0x646E    //RX_FDEQ_GAIN_10
-50    0x6A72    //RX_FDEQ_GAIN_11
-51    0x727A    //RX_FDEQ_GAIN_12
-52    0x6060    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x5860    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x8076    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8619,21 +4343,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8666,49 +4390,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0084    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0715    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4856    //RX_FDEQ_GAIN_2
-42    0x605C    //RX_FDEQ_GAIN_3
-43    0x5E56    //RX_FDEQ_GAIN_4
-44    0x544E    //RX_FDEQ_GAIN_5
-45    0x4E58    //RX_FDEQ_GAIN_6
-46    0x4E4E    //RX_FDEQ_GAIN_7
-47    0x748A    //RX_FDEQ_GAIN_8
-48    0x8C8C    //RX_FDEQ_GAIN_9
-49    0x7480    //RX_FDEQ_GAIN_10
-50    0x7C84    //RX_FDEQ_GAIN_11
-51    0x848C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x7080    //RX_FDEQ_GAIN_14
-54    0x7C98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x5860    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x8076    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -8718,21 +4442,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0201    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0505    //RX_FDEQ_BIN_3
-67    0x0205    //RX_FDEQ_BIN_4
-68    0x0303    //RX_FDEQ_BIN_5
-69    0x0A08    //RX_FDEQ_BIN_6
-70    0x1910    //RX_FDEQ_BIN_7
-71    0x110A    //RX_FDEQ_BIN_8
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1E13    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x0F23    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -8767,16 +4491,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0019    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0033    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0049    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6864    //RX_FDEQ_GAIN_1
+198    0x7070    //RX_FDEQ_GAIN_2
+199    0x6058    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HANDSFREE-HANDSFREE-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x6F78    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
 7    0x0003    //TX_SAMPLINGFREQ_PROC
@@ -8793,8 +5369,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -8922,28 +5498,28 @@
 147    0x0400    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7600    //TX_EAD_THR
+150    0x7000    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x2000    //TX_MIN_EQ_RE_EST_1
-154    0x6000    //TX_MIN_EQ_RE_EST_2
-155    0x7FFF    //TX_MIN_EQ_RE_EST_3
-156    0x7FFF    //TX_MIN_EQ_RE_EST_4
-157    0x7FFF    //TX_MIN_EQ_RE_EST_5
-158    0x7FFF    //TX_MIN_EQ_RE_EST_6
-159    0x7FFF    //TX_MIN_EQ_RE_EST_7
-160    0x7FFF    //TX_MIN_EQ_RE_EST_8
-161    0x7FFF    //TX_MIN_EQ_RE_EST_9
-162    0x7FFF    //TX_MIN_EQ_RE_EST_10
-163    0x7FFF    //TX_MIN_EQ_RE_EST_11
-164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
 166    0x3000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x4000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
+169    0x0260    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x0080    //TX_DT2_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -8969,12 +5545,12 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
+197    0x7080    //TX_DTD_THR1_0
 198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
+199    0x7C38    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
+202    0x7D00    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
 204    0x7E00    //TX_DTD_THR2_0
 205    0x7E00    //TX_DTD_THR2_1
@@ -8985,8 +5561,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x0BB0    //TX_DT_CUT_K
-214    0x0001    //TX_DT_CUT_THR
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -8995,18 +5571,18 @@
 220    0x7FFF    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x04B0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x0960    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x4000    //TX_B_POST_FILT_ECHO_L
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
 229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0032    //TX_EPD_OFFSET_00
-233    0x0032    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -9015,20 +5591,20 @@
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
 242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFB00    //TX_THR_SN_EST_2
-245    0xFB00    //TX_THR_SN_EST_3
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
 246    0xF800    //TX_THR_SN_EST_4
 247    0xFA00    //TX_THR_SN_EST_5
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0120    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
 253    0x0100    //TX_DELTA_THR_SN_EST_3
-254    0x0000    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -9054,52 +5630,52 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0020    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0028    //TX_NS_LVL_CTRL_3
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
 285    0x0014    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0012    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0011    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x1400    //TX_SNRI_SUP_0
-301    0x1000    //TX_SNRI_SUP_1
-302    0x1400    //TX_SNRI_SUP_2
-303    0x1400    //TX_SNRI_SUP_3
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
 310    0x09C4    //TX_GAIN0_NTH
 311    0x000A    //TX_MUSIC_MORENS
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x7C00    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x2000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -9107,32 +5683,32 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7F20    //TX_LAMBDA_PFILT_S_0
-340    0x7D00    //TX_LAMBDA_PFILT_S_1
-341    0x7D00    //TX_LAMBDA_PFILT_S_2
-342    0x7D00    //TX_LAMBDA_PFILT_S_3
-343    0x7D00    //TX_LAMBDA_PFILT_S_4
-344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
-346    0x7D00    //TX_LAMBDA_PFILT_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
-348    0x0400    //TX_A_PEPPER
+348    0x0800    //TX_A_PEPPER
 349    0x1EAA    //TX_K_PEPPER_HF
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0040    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x07D0    //TX_DT_BINVAD_TH_2
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
 356    0x2000    //TX_DT_BINVAD_TH_3
-357    0x0BB8    //TX_DT_BINVAD_ENDF
+357    0x36B0    //TX_DT_BINVAD_ENDF
 358    0x0200    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01B0    //TX_DT_BOOST
+360    0x0140    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
 362    0x0005    //TX_BF_DVG_TH
 363    0x001E    //TX_SN_C_F
@@ -9144,18 +5720,18 @@
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
 371    0x01F4    //TX_NOISE_TH_2
-372    0x4E20    //TX_NOISE_TH_3
+372    0x36B0    //TX_NOISE_TH_3
 373    0x2710    //TX_NOISE_TH_4
-374    0x2710    //TX_NOISE_TH_5
+374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0DAC    //TX_NOISE_TH_6
 379    0x0050    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -9163,15 +5739,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -9281,21 +5857,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -9324,37 +5900,37 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
-567    0x7848    //TX_FDEQ_GAIN_0
+567    0x4848    //TX_FDEQ_GAIN_0
 568    0x484C    //TX_FDEQ_GAIN_1
-569    0x4E4C    //TX_FDEQ_GAIN_2
-570    0x504C    //TX_FDEQ_GAIN_3
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
 571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x584C    //TX_FDEQ_GAIN_6
-574    0x4C54    //TX_FDEQ_GAIN_7
-575    0x4E54    //TX_FDEQ_GAIN_8
-576    0x4C50    //TX_FDEQ_GAIN_9
-577    0x545A    //TX_FDEQ_GAIN_10
-578    0x5C68    //TX_FDEQ_GAIN_11
-579    0x6168    //TX_FDEQ_GAIN_12
-580    0x7270    //TX_FDEQ_GAIN_13
-581    0x786C    //TX_FDEQ_GAIN_14
-582    0x84CA    //TX_FDEQ_GAIN_15
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
 584    0x4848    //TX_FDEQ_GAIN_17
 585    0x4848    //TX_FDEQ_GAIN_18
@@ -9366,19 +5942,19 @@
 591    0x0202    //TX_FDEQ_BIN_0
 592    0x0203    //TX_FDEQ_BIN_1
 593    0x0303    //TX_FDEQ_BIN_2
-594    0x0403    //TX_FDEQ_BIN_3
+594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0B02    //TX_FDEQ_BIN_6
-598    0x070E    //TX_FDEQ_BIN_7
-599    0x0B0E    //TX_FDEQ_BIN_8
-600    0x0B0E    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x0C15    //TX_FDEQ_BIN_12
-604    0x1128    //TX_FDEQ_BIN_13
-605    0x5028    //TX_FDEQ_BIN_14
-606    0x284A    //TX_FDEQ_BIN_15
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
 608    0x0000    //TX_FDEQ_BIN_17
 609    0x0000    //TX_FDEQ_BIN_18
@@ -9388,7 +5964,7 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
@@ -9397,15 +5973,15 @@
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
 624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x484A    //TX_PREEQ_GAIN_MIC0_8
-626    0x4C50    //TX_PREEQ_GAIN_MIC0_9
-627    0x5050    //TX_PREEQ_GAIN_MIC0_10
-628    0x5054    //TX_PREEQ_GAIN_MIC0_11
-629    0x5C6A    //TX_PREEQ_GAIN_MIC0_12
-630    0x7A60    //TX_PREEQ_GAIN_MIC0_13
-631    0x5C48    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -9419,17 +5995,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x090A    //TX_PREEQ_BIN_MIC0_7
-649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1719    //TX_PREEQ_BIN_MIC0_11
-653    0x1B1E    //TX_PREEQ_BIN_MIC0_12
-654    0x1E1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -9437,7 +6013,7 @@
 662    0x0000    //TX_PREEQ_BIN_MIC0_21
 663    0x0000    //TX_PREEQ_BIN_MIC0_22
 664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
 666    0x4848    //TX_PREEQ_GAIN_MIC1_0
 667    0x4848    //TX_PREEQ_GAIN_MIC1_1
 668    0x4848    //TX_PREEQ_GAIN_MIC1_2
@@ -9450,11 +6026,11 @@
 675    0x4848    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
 684    0x4848    //TX_PREEQ_GAIN_MIC1_18
 685    0x4848    //TX_PREEQ_GAIN_MIC1_19
@@ -9462,23 +6038,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x070F    //TX_PREEQ_BIN_MIC1_8
-699    0x1F08    //TX_PREEQ_BIN_MIC1_9
-700    0x0808    //TX_PREEQ_BIN_MIC1_10
-701    0x0920    //TX_PREEQ_BIN_MIC1_11
-702    0x2020    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -9486,7 +6062,7 @@
 711    0x0000    //TX_PREEQ_BIN_MIC1_21
 712    0x0000    //TX_PREEQ_BIN_MIC1_22
 713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
@@ -9499,11 +6075,11 @@
 724    0x4848    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
 734    0x4848    //TX_PREEQ_GAIN_MIC2_19
@@ -9511,23 +6087,23 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
 745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0xF200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
 758    0x0000    //TX_PREEQ_BIN_MIC2_19
@@ -9537,18 +6113,18 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0060    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0042    //TX_MIC_PWR_BIAS_1
-771    0x0042    //TX_MIC_PWR_BIAS_2
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0003    //TX_GAIN_LIMIT_0
-774    0x0006    //TX_GAIN_LIMIT_1
-775    0x0006    //TX_GAIN_LIMIT_2
-776    0x0003    //TX_GAIN_LIMIT_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -9560,8 +6136,8 @@
 785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
 790    0x4000    //TX_TDDRC_ALPHA_DWN_04
 791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
@@ -9588,8 +6164,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -9625,20 +6201,20 @@
 850    0x0000    //TX_FFP_RESRV_4
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
-853    0x0001    //TX_FILTINDX
-854    0x0009    //TX_TDDRC_THRD_0
-855    0x0018    //TX_TDDRC_THRD_1
-856    0x1200    //TX_TDDRC_THRD_2
-857    0x1C60    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
 860    0x4000    //TX_TDDRC_ALPHA_UP_00
 861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0DA6    //TX_TDDRC_DRC_GAIN
+866    0x12D6    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -9669,8 +6245,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x047C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -9678,7 +6319,7 @@
 5    0x0000    //RX_DELAY_OPT
 6    0x6000    //RX_TDDRC_ALPHA_UP_1
 7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
 11    0x7D83    //RX_A_HP
@@ -9692,13 +6333,13 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
-25    0x00C8    //RX_FENS_RESRV_0
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
@@ -9709,22 +6350,22 @@
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -9733,22 +6374,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
-72    0x0A0A    //RX_FDEQ_BIN_9
-73    0x0A0A    //RX_FDEQ_BIN_10
-74    0x0A0A    //RX_FDEQ_BIN_11
-75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -9783,23 +6424,23 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 111    0x0004    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
+113    0x0002    //RX_TDDRC_THRD_1
 114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
+115    0x0CE0    //RX_TDDRC_THRD_3
 116    0x0000    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x03FC    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x13E0    //RX_TPKA_FP
+126    0x1134    //RX_TPKA_FP
 127    0x0400    //RX_MIN_G_FP
-128    0x0800    //RX_MAX_G_FP
-129    0x0042    //RX_SPK_VOL
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -9828,46 +6469,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -9878,20 +6519,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -9924,49 +6565,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0042    //RX_SPK_VOL
+129    0x000A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -9977,20 +6618,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10023,49 +6664,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0068    //RX_SPK_VOL
+129    0x0011    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -10076,20 +6717,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10122,49 +6763,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x009F    //RX_SPK_VOL
+129    0x001B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -10175,20 +6816,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10221,49 +6862,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00F8    //RX_SPK_VOL
+129    0x002C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0188    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -10274,20 +6915,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10320,49 +6961,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0048    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x028F    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x707E    //RX_FDEQ_GAIN_8
-48    0x807A    //RX_FDEQ_GAIN_9
-49    0x6A60    //RX_FDEQ_GAIN_10
-50    0x6868    //RX_FDEQ_GAIN_11
-51    0x6C84    //RX_FDEQ_GAIN_12
-52    0x624C    //RX_FDEQ_GAIN_13
-53    0x5862    //RX_FDEQ_GAIN_14
-54    0x6E98    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -10373,20 +7014,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10419,49 +7060,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x007E    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0715    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0xA4A4    //RX_FDEQ_GAIN_0
-40    0x604C    //RX_FDEQ_GAIN_1
-41    0x4854    //RX_FDEQ_GAIN_2
-42    0x5C5C    //RX_FDEQ_GAIN_3
-43    0x5850    //RX_FDEQ_GAIN_4
-44    0x5048    //RX_FDEQ_GAIN_5
-45    0x524E    //RX_FDEQ_GAIN_6
-46    0x484E    //RX_FDEQ_GAIN_7
-47    0x7284    //RX_FDEQ_GAIN_8
-48    0x8C8C    //RX_FDEQ_GAIN_9
-49    0x7E74    //RX_FDEQ_GAIN_10
-50    0x7C7C    //RX_FDEQ_GAIN_11
-51    0x7E96    //RX_FDEQ_GAIN_12
-52    0x7A60    //RX_FDEQ_GAIN_13
-53    0x6A76    //RX_FDEQ_GAIN_14
-54    0x7898    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -10472,20 +7113,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0102    //RX_FDEQ_BIN_1
-65    0x0504    //RX_FDEQ_BIN_2
-66    0x0006    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0309    //RX_FDEQ_BIN_5
-69    0x0806    //RX_FDEQ_BIN_6
-70    0x071E    //RX_FDEQ_BIN_7
-71    0x0D10    //RX_FDEQ_BIN_8
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
 72    0x0A0A    //RX_FDEQ_BIN_9
 73    0x0A0A    //RX_FDEQ_BIN_10
 74    0x0A0A    //RX_FDEQ_BIN_11
 75    0x0A0A    //RX_FDEQ_BIN_12
-76    0x1424    //RX_FDEQ_BIN_13
-77    0x2150    //RX_FDEQ_BIN_14
-78    0x2860    //RX_FDEQ_BIN_15
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -10520,15 +7161,867 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1104    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x069B    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x06AF    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x069B    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0688    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0688    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0049    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x06AF    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0080    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x064F    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5858    //RX_FDEQ_GAIN_1
+198    0x5862    //RX_FDEQ_GAIN_2
+199    0x666A    //RX_FDEQ_GAIN_3
+200    0x6668    //RX_FDEQ_GAIN_4
+201    0x5C60    //RX_FDEQ_GAIN_5
+202    0x4C4C    //RX_FDEQ_GAIN_6
+203    0x5C72    //RX_FDEQ_GAIN_7
+204    0x6C80    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x8C90    //RX_FDEQ_GAIN_10
+207    0x7E78    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HANDSFREE-HANDSFREE-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
 2    0x0033    //TX_PATCH_REG
-3    0x6B78    //TX_SENDFUNC_MODE_0
+3    0x4B7C    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0004    //TX_SAMPLINGFREQ_SIG
@@ -10546,15 +8039,15 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x008A    //TX_DIST2REF1
-22    0x0018    //TX_DIST2REF_02
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
 26    0x0000    //TX_MMIC
-27    0x0E3A    //TX_PGA_0
-28    0x0E3A    //TX_PGA_1
-29    0x0E3A    //TX_PGA_2
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
 30    0x0000    //TX_PGA_3
 31    0x0000    //TX_PGA_4
 32    0x0000    //TX_PGA_5
@@ -10672,16 +8165,16 @@
 144    0x0000    //TX_PP_RESRV_6
 145    0x0000    //TX_PP_RESRV_7
 146    0x0028    //TX_TAIL_LENGTH
-147    0x0400    //TX_AEC_REF_GAIN_0
+147    0x0300    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
 150    0x7A00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
-152    0x2000    //TX_MIN_EQ_RE_EST_0
-153    0x7FFF    //TX_MIN_EQ_RE_EST_1
-154    0x7FFF    //TX_MIN_EQ_RE_EST_2
-155    0x7FFF    //TX_MIN_EQ_RE_EST_3
-156    0x7FFF    //TX_MIN_EQ_RE_EST_4
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x4000    //TX_MIN_EQ_RE_EST_3
+156    0x4000    //TX_MIN_EQ_RE_EST_4
 157    0x7FFF    //TX_MIN_EQ_RE_EST_5
 158    0x7FFF    //TX_MIN_EQ_RE_EST_6
 159    0x7FFF    //TX_MIN_EQ_RE_EST_7
@@ -10692,11 +8185,11 @@
 164    0x7FFF    //TX_MIN_EQ_RE_EST_12
 165    0x4000    //TX_LAMBDA_RE_EST
 166    0x0CCD    //TX_LAMBDA_CB_NLE
-167    0x7FFF    //TX_C_POST_FLT
+167    0x2000    //TX_C_POST_FLT
 168    0x7FFF    //TX_GAIN_NP
 169    0x0180    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x0080    //TX_DT2_HOLD_N
+171    0x09C4    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -10722,23 +8215,23 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
+197    0x7D00    //TX_DTD_THR1_0
 198    0x7FF0    //TX_DTD_THR1_1
 199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
-204    0x7E00    //TX_DTD_THR2_0
-205    0x7E00    //TX_DTD_THR2_1
-206    0x5000    //TX_DTD_THR2_2
-207    0x5000    //TX_DTD_THR2_3
-208    0x5000    //TX_DTD_THR2_4
-209    0x5000    //TX_DTD_THR2_5
-210    0x5000    //TX_DTD_THR2_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
+213    0x0DAC    //TX_DT_CUT_K
 214    0x0020    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
@@ -10748,19 +8241,19 @@
 220    0x7FFF    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x04B0    //TX_RATIO_DT_L_TH_LOW
-224    0x2616    //TX_RATIO_DT_H_TH_LOW
-225    0x0960    //TX_RATIO_DT_L_TH_HIGH
-226    0x32C8    //TX_RATIO_DT_H_TH_HIGH
-227    0x0640    //TX_RATIO_DT_L0_TH
-228    0x7FFF    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0048    //TX_EPD_OFFSET_00
-233    0x0048    //TX_EPD_OFFST_01
-234    0x0C80    //TX_RATIO_DT_L0_TH_HIGH
-235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+232    0x0063    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
 238    0x0000    //TX_DTD_THR2_7
@@ -10776,11 +8269,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -10808,11 +8301,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -10825,13 +8318,13 @@
 297    0x6000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x1400    //TX_SNRI_SUP_0
+300    0x7FFF    //TX_SNRI_SUP_0
 301    0x4000    //TX_SNRI_SUP_1
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -10840,19 +8333,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -10860,32 +8353,32 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7F80    //TX_LAMBDA_PFILT_S_0
+339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
 346    0x7C00    //TX_LAMBDA_PFILT_S_7
-347    0x01F4    //TX_K_PEPPER
+347    0x0000    //TX_K_PEPPER
 348    0x0800    //TX_A_PEPPER
 349    0x1EAA    //TX_K_PEPPER_HF
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
-353    0x0100    //TX_DT_BINVAD_TH_0
+353    0x0200    //TX_DT_BINVAD_TH_0
 354    0x0200    //TX_DT_BINVAD_TH_1
 355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x4000    //TX_DT_BINVAD_TH_3
-357    0x0BB8    //TX_DT_BINVAD_ENDF
-358    0x0200    //TX_C_POST_FLT_DT
+356    0x0200    //TX_DT_BINVAD_TH_3
+357    0x1F40    //TX_DT_BINVAD_ENDF
+358    0x0100    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x01FF    //TX_DT_BOOST
+360    0x0100    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
 362    0x0005    //TX_BF_DVG_TH
 363    0x001E    //TX_SN_C_F
@@ -10905,10 +8398,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x2710    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -10916,15 +8409,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -11034,21 +8527,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0005    //TX_ECHO_SUPP_FC
+509    0x0000    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -11077,37 +8570,37 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
-568    0x484D    //TX_FDEQ_GAIN_1
+568    0x4848    //TX_FDEQ_GAIN_1
 569    0x4848    //TX_FDEQ_GAIN_2
 570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4854    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x4A50    //TX_FDEQ_GAIN_6
-574    0x484C    //TX_FDEQ_GAIN_7
-575    0x5256    //TX_FDEQ_GAIN_8
-576    0x5A5A    //TX_FDEQ_GAIN_9
-577    0x6468    //TX_FDEQ_GAIN_10
-578    0x807C    //TX_FDEQ_GAIN_11
-579    0x84AC    //TX_FDEQ_GAIN_12
-580    0xCACA    //TX_FDEQ_GAIN_13
-581    0xCACA    //TX_FDEQ_GAIN_14
-582    0xCACA    //TX_FDEQ_GAIN_15
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x5048    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
+581    0xC4C4    //TX_FDEQ_GAIN_14
+582    0xC4C4    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
 584    0x4848    //TX_FDEQ_GAIN_17
 585    0x4848    //TX_FDEQ_GAIN_18
@@ -11117,21 +8610,21 @@
 589    0x4848    //TX_FDEQ_GAIN_22
 590    0x4848    //TX_FDEQ_GAIN_23
 591    0x0202    //TX_FDEQ_BIN_0
-592    0x0207    //TX_FDEQ_BIN_1
-593    0x0302    //TX_FDEQ_BIN_2
-594    0x0204    //TX_FDEQ_BIN_3
-595    0x0509    //TX_FDEQ_BIN_4
-596    0x030A    //TX_FDEQ_BIN_5
-597    0x0709    //TX_FDEQ_BIN_6
-598    0x0809    //TX_FDEQ_BIN_7
-599    0x1D0B    //TX_FDEQ_BIN_8
-600    0x0B0B    //TX_FDEQ_BIN_9
-601    0x0B1B    //TX_FDEQ_BIN_10
-602    0x351B    //TX_FDEQ_BIN_11
-603    0x1A0D    //TX_FDEQ_BIN_12
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
 604    0x2020    //TX_FDEQ_BIN_13
 605    0x2020    //TX_FDEQ_BIN_14
-606    0x202F    //TX_FDEQ_BIN_15
+606    0x2011    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
 608    0x0000    //TX_FDEQ_BIN_17
 609    0x0000    //TX_FDEQ_BIN_18
@@ -11141,24 +8634,24 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
 620    0x4848    //TX_PREEQ_GAIN_MIC0_3
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484C    //TX_PREEQ_GAIN_MIC0_7
-625    0x5050    //TX_PREEQ_GAIN_MIC0_8
-626    0x5050    //TX_PREEQ_GAIN_MIC0_9
-627    0x545C    //TX_PREEQ_GAIN_MIC0_10
-628    0x6A7A    //TX_PREEQ_GAIN_MIC0_11
-629    0x625C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+623    0x4849    //TX_PREEQ_GAIN_MIC0_6
+624    0x4A4B    //TX_PREEQ_GAIN_MIC0_7
+625    0x4C4B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4A48    //TX_PREEQ_GAIN_MIC0_9
+627    0x4B4C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4B    //TX_PREEQ_GAIN_MIC0_11
+629    0x4838    //TX_PREEQ_GAIN_MIC0_12
+630    0x3858    //TX_PREEQ_GAIN_MIC0_13
+631    0x7060    //TX_PREEQ_GAIN_MIC0_14
+632    0x9870    //TX_PREEQ_GAIN_MIC0_15
+633    0x5848    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -11172,17 +8665,5357 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
 650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
 652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x3A1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4645    //TX_PREEQ_GAIN_MIC1_6
+673    0x4442    //TX_PREEQ_GAIN_MIC1_7
+674    0x4140    //TX_PREEQ_GAIN_MIC1_8
+675    0x3E3D    //TX_PREEQ_GAIN_MIC1_9
+676    0x3C3C    //TX_PREEQ_GAIN_MIC1_10
+677    0x3C3C    //TX_PREEQ_GAIN_MIC1_11
+678    0x3938    //TX_PREEQ_GAIN_MIC1_12
+679    0x3A3C    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C3E    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x4000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0004    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0016    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x006C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+10    0x065B    //RX_PGA
+11    0x7E56    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF400    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0034    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x004D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0074    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x006C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+167    0x065B    //RX_PGA
+168    0x7E56    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF400    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0025    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x004D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM1-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F75    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x047C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0048    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x007E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1134    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0662    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05D2    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0048    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM1-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x6B74    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0300    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7A00    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x4000    //TX_MIN_EQ_RE_EST_3
+156    0x4000    //TX_MIN_EQ_RE_EST_4
+157    0x7FFF    //TX_MIN_EQ_RE_EST_5
+158    0x7FFF    //TX_MIN_EQ_RE_EST_6
+159    0x7FFF    //TX_MIN_EQ_RE_EST_7
+160    0x7FFF    //TX_MIN_EQ_RE_EST_8
+161    0x7FFF    //TX_MIN_EQ_RE_EST_9
+162    0x7FFF    //TX_MIN_EQ_RE_EST_10
+163    0x7FFF    //TX_MIN_EQ_RE_EST_11
+164    0x7FFF    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x0CCD    //TX_LAMBDA_CB_NLE
+167    0x2000    //TX_C_POST_FLT
+168    0x7FFF    //TX_GAIN_NP
+169    0x0180    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x09C4    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7FF0    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0DAC    //TX_DT_CUT_K
+214    0x0020    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0063    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFB00    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0200    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000F    //TX_MIN_GAIN_S_0
+290    0x0010    //TX_MIN_GAIN_S_1
+291    0x0010    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0010    //TX_MIN_GAIN_S_4
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x0010    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x5000    //TX_A_POST_FILT_S_0
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x4000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C00    //TX_LAMBDA_PFILT
+339    0x7C00    //TX_LAMBDA_PFILT_S_0
+340    0x7C00    //TX_LAMBDA_PFILT_S_1
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
+343    0x7C00    //TX_LAMBDA_PFILT_S_4
+344    0x7C00    //TX_LAMBDA_PFILT_S_5
+345    0x7C00    //TX_LAMBDA_PFILT_S_6
+346    0x7C00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0200    //TX_DT_BINVAD_TH_0
+354    0x0200    //TX_DT_BINVAD_TH_1
+355    0x0200    //TX_DT_BINVAD_TH_2
+356    0x0200    //TX_DT_BINVAD_TH_3
+357    0x1F40    //TX_DT_BINVAD_ENDF
+358    0x0100    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x4E20    //TX_NOISE_TH_3
+373    0x4E20    //TX_NOISE_TH_4
+374    0x59D8    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x2710    //TX_NOISE_TH_6
+379    0x0033    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0033    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x7FFF    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x5048    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
+581    0xC4C4    //TX_FDEQ_GAIN_14
+582    0xC4C4    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4849    //TX_PREEQ_GAIN_MIC0_6
+624    0x4A4B    //TX_PREEQ_GAIN_MIC0_7
+625    0x4C4B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4A48    //TX_PREEQ_GAIN_MIC0_9
+627    0x4B4C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4B    //TX_PREEQ_GAIN_MIC0_11
+629    0x4838    //TX_PREEQ_GAIN_MIC0_12
+630    0x3858    //TX_PREEQ_GAIN_MIC0_13
+631    0x7060    //TX_PREEQ_GAIN_MIC0_14
+632    0x9870    //TX_PREEQ_GAIN_MIC0_15
+633    0x5848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -11308,13 +14141,2683 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0004    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0016    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x006C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+10    0x065B    //RX_PGA
+11    0x7E56    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF400    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x00C8    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0034    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x004D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0074    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x006C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+167    0x065B    //RX_PGA
+168    0x7E56    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF400    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x00C8    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0025    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x004D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F5D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
 783    0x6000    //TX_TDDRC_ALPHA_UP_01
 784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
 785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
 786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x6000    //TX_TDDRC_ALPHA_DWN_02
-789    0x6000    //TX_TDDRC_ALPHA_DWN_03
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
 790    0x4000    //TX_TDDRC_ALPHA_DWN_04
 791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
@@ -11341,8 +16844,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -11381,17 +16884,2687 @@
 853    0x0002    //TX_FILTINDX
 854    0x0004    //TX_TDDRC_THRD_0
 855    0x0010    //TX_TDDRC_THRD_1
-856    0x1200    //TX_TDDRC_THRD_2
-857    0x1C60    //TX_TDDRC_THRD_3
-858    0x0000    //TX_TDDRC_SLANT_0
-859    0x7FFF    //TX_TDDRC_SLANT_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
 860    0x4000    //TX_TDDRC_ALPHA_UP_00
 861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0D56    //TX_TDDRC_DRC_GAIN
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x047C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0048    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x007E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1134    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0662    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05D2    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0048    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-CUSTOM2-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x6B5C    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0300    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7A00    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x4000    //TX_MIN_EQ_RE_EST_3
+156    0x4000    //TX_MIN_EQ_RE_EST_4
+157    0x7FFF    //TX_MIN_EQ_RE_EST_5
+158    0x7FFF    //TX_MIN_EQ_RE_EST_6
+159    0x7FFF    //TX_MIN_EQ_RE_EST_7
+160    0x7FFF    //TX_MIN_EQ_RE_EST_8
+161    0x7FFF    //TX_MIN_EQ_RE_EST_9
+162    0x7FFF    //TX_MIN_EQ_RE_EST_10
+163    0x7FFF    //TX_MIN_EQ_RE_EST_11
+164    0x7FFF    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x0CCD    //TX_LAMBDA_CB_NLE
+167    0x2000    //TX_C_POST_FLT
+168    0x7FFF    //TX_GAIN_NP
+169    0x0180    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x09C4    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7FF0    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0DAC    //TX_DT_CUT_K
+214    0x0020    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0063    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFB00    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0200    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000F    //TX_MIN_GAIN_S_0
+290    0x0010    //TX_MIN_GAIN_S_1
+291    0x0010    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0010    //TX_MIN_GAIN_S_4
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x0010    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x5000    //TX_A_POST_FILT_S_0
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x4000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C00    //TX_LAMBDA_PFILT
+339    0x7C00    //TX_LAMBDA_PFILT_S_0
+340    0x7C00    //TX_LAMBDA_PFILT_S_1
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
+343    0x7C00    //TX_LAMBDA_PFILT_S_4
+344    0x7C00    //TX_LAMBDA_PFILT_S_5
+345    0x7C00    //TX_LAMBDA_PFILT_S_6
+346    0x7C00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0200    //TX_DT_BINVAD_TH_0
+354    0x0200    //TX_DT_BINVAD_TH_1
+355    0x0200    //TX_DT_BINVAD_TH_2
+356    0x0200    //TX_DT_BINVAD_TH_3
+357    0x1F40    //TX_DT_BINVAD_ENDF
+358    0x0100    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x4E20    //TX_NOISE_TH_3
+373    0x4E20    //TX_NOISE_TH_4
+374    0x59D8    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x2710    //TX_NOISE_TH_6
+379    0x0033    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0033    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x7FFF    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x5048    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
+581    0xC4C4    //TX_FDEQ_GAIN_14
+582    0xC4C4    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4849    //TX_PREEQ_GAIN_MIC0_6
+624    0x4A4B    //TX_PREEQ_GAIN_MIC0_7
+625    0x4C4B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4A48    //TX_PREEQ_GAIN_MIC0_9
+627    0x4B4C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4B    //TX_PREEQ_GAIN_MIC0_11
+629    0x4838    //TX_PREEQ_GAIN_MIC0_12
+630    0x3858    //TX_PREEQ_GAIN_MIC0_13
+631    0x7060    //TX_PREEQ_GAIN_MIC0_14
+632    0x9870    //TX_PREEQ_GAIN_MIC0_15
+633    0x5848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x1812    //TX_PREEQ_BIN_MIC1_0
+691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
+692    0x0808    //TX_PREEQ_BIN_MIC1_2
+693    0x080A    //TX_PREEQ_BIN_MIC1_3
+694    0x0B09    //TX_PREEQ_BIN_MIC1_4
+695    0x0A06    //TX_PREEQ_BIN_MIC1_5
+696    0x0606    //TX_PREEQ_BIN_MIC1_6
+697    0x0605    //TX_PREEQ_BIN_MIC1_7
+698    0x050A    //TX_PREEQ_BIN_MIC1_8
+699    0x1505    //TX_PREEQ_BIN_MIC1_9
+700    0x0506    //TX_PREEQ_BIN_MIC1_10
+701    0x0615    //TX_PREEQ_BIN_MIC1_11
+702    0x1516    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x2021    //TX_PREEQ_BIN_MIC1_14
+705    0x2021    //TX_PREEQ_BIN_MIC1_15
+706    0x0800    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0004    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0016    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -11422,6 +19595,71 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x006C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -11429,11 +19667,11 @@
 3    0x0004    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+10    0x065B    //RX_PGA
 11    0x7E56    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x7800    //RX_THR_PITCH_DET_0
@@ -11450,34 +19688,34 @@
 24    0x7E00    //RX_LAMBDA_PFILT
 25    0x00C8    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -11486,22 +19724,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -11534,25 +19772,25 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0004    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x4000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
 126    0x2000    //RX_TPKA_FP
 127    0x2000    //RX_MIN_G_FP
 128    0x0080    //RX_MAX_G_FP
-129    0x0034    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -11581,46 +19819,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x4000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -11629,22 +19867,319 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -11679,344 +20214,47 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0034    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0001    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0051    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0081    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0001    //RX_TDDRC_THRD_0
-113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x00CC    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0001    //RX_TDDRC_THRD_0
 113    0x0002    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x4000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0143    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -12025,22 +20263,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -12073,49 +20311,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x004D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
-29    0x6000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0001    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
 118    0x4000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0217    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
-54    0x9898    //RX_FDEQ_GAIN_15
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -12124,22 +20362,121 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0074    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -12174,46 +20511,1880 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x006C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+167    0x065B    //RX_PGA
+168    0x7E56    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF400    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x00C8    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0025    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x004D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    6
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-RESERVE1-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F55    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x047C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
 6    0x6000    //RX_TDDRC_ALPHA_UP_1
 7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
-8    0x5000    //RX_TDDRC_ALPHA_UP_3
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x6000    //RX_TDDRC_ALPHA_DWN_1
-28    0x6000    //RX_TDDRC_ALPHA_DWN_2
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0006    //RX_TDDRC_THRD_1
-114    0x0340    //RX_TDDRC_THRD_2
-115    0x1C20    //RX_TDDRC_THRD_3
-116    0x0000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x4000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0504    //RX_TDDRC_DRC_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x9858    //RX_FDEQ_GAIN_0
-40    0x505C    //RX_FDEQ_GAIN_1
-41    0x6460    //RX_FDEQ_GAIN_2
-42    0x5656    //RX_FDEQ_GAIN_3
-43    0x5460    //RX_FDEQ_GAIN_4
-44    0x6454    //RX_FDEQ_GAIN_5
-45    0x5678    //RX_FDEQ_GAIN_6
-46    0x8A84    //RX_FDEQ_GAIN_7
-47    0x8474    //RX_FDEQ_GAIN_8
-48    0x6876    //RX_FDEQ_GAIN_9
-49    0x7676    //RX_FDEQ_GAIN_10
-50    0x826C    //RX_FDEQ_GAIN_11
-51    0x505A    //RX_FDEQ_GAIN_12
-52    0x8870    //RX_FDEQ_GAIN_13
-53    0x9898    //RX_FDEQ_GAIN_14
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
 54    0x9898    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -12224,21 +22395,3428 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0301    //RX_FDEQ_BIN_0
-64    0x0403    //RX_FDEQ_BIN_1
-65    0x0602    //RX_FDEQ_BIN_2
-66    0x0302    //RX_FDEQ_BIN_3
-67    0x0605    //RX_FDEQ_BIN_4
-68    0x0405    //RX_FDEQ_BIN_5
-69    0x1409    //RX_FDEQ_BIN_6
-70    0x0A07    //RX_FDEQ_BIN_7
-71    0x0707    //RX_FDEQ_BIN_8
-72    0x0607    //RX_FDEQ_BIN_9
-73    0x0607    //RX_FDEQ_BIN_10
-74    0x070D    //RX_FDEQ_BIN_11
-75    0x1816    //RX_FDEQ_BIN_12
-76    0x361A    //RX_FDEQ_BIN_13
-77    0x5028    //RX_FDEQ_BIN_14
-78    0x284A    //RX_FDEQ_BIN_15
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0048    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x007E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1134    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0662    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05D2    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0048    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-RESERVE1-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x6B54    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0300    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7A00    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x4000    //TX_MIN_EQ_RE_EST_3
+156    0x4000    //TX_MIN_EQ_RE_EST_4
+157    0x7FFF    //TX_MIN_EQ_RE_EST_5
+158    0x7FFF    //TX_MIN_EQ_RE_EST_6
+159    0x7FFF    //TX_MIN_EQ_RE_EST_7
+160    0x7FFF    //TX_MIN_EQ_RE_EST_8
+161    0x7FFF    //TX_MIN_EQ_RE_EST_9
+162    0x7FFF    //TX_MIN_EQ_RE_EST_10
+163    0x7FFF    //TX_MIN_EQ_RE_EST_11
+164    0x7FFF    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x0CCD    //TX_LAMBDA_CB_NLE
+167    0x2000    //TX_C_POST_FLT
+168    0x7FFF    //TX_GAIN_NP
+169    0x0180    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x09C4    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7D00    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7FF0    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0DAC    //TX_DT_CUT_K
+214    0x0020    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x2000    //TX_B_POST_FILT_ECHO_L
+229    0x2000    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0063    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFB00    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0200    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000F    //TX_MIN_GAIN_S_0
+290    0x0010    //TX_MIN_GAIN_S_1
+291    0x0010    //TX_MIN_GAIN_S_2
+292    0x0010    //TX_MIN_GAIN_S_3
+293    0x0010    //TX_MIN_GAIN_S_4
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x0010    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x6000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x4000    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x5000    //TX_A_POST_FILT_S_0
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
+321    0x7000    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x4000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7C00    //TX_LAMBDA_PFILT
+339    0x7C00    //TX_LAMBDA_PFILT_S_0
+340    0x7C00    //TX_LAMBDA_PFILT_S_1
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
+343    0x7C00    //TX_LAMBDA_PFILT_S_4
+344    0x7C00    //TX_LAMBDA_PFILT_S_5
+345    0x7C00    //TX_LAMBDA_PFILT_S_6
+346    0x7C00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0200    //TX_DT_BINVAD_TH_0
+354    0x0200    //TX_DT_BINVAD_TH_1
+355    0x0200    //TX_DT_BINVAD_TH_2
+356    0x0200    //TX_DT_BINVAD_TH_3
+357    0x1F40    //TX_DT_BINVAD_ENDF
+358    0x0100    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x0DAC    //TX_NOISE_TH_2
+372    0x4E20    //TX_NOISE_TH_3
+373    0x4E20    //TX_NOISE_TH_4
+374    0x59D8    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x2710    //TX_NOISE_TH_6
+379    0x0033    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0033    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x7FFF    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x5048    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
+581    0xC4C4    //TX_FDEQ_GAIN_14
+582    0xC4C4    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x484B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x484C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4C    //TX_PREEQ_GAIN_MIC0_11
+629    0x4038    //TX_PREEQ_GAIN_MIC0_12
+630    0x3838    //TX_PREEQ_GAIN_MIC0_13
+631    0x4840    //TX_PREEQ_GAIN_MIC0_14
+632    0x3848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0030    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x1812    //TX_PREEQ_BIN_MIC1_0
+691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
+692    0x0808    //TX_PREEQ_BIN_MIC1_2
+693    0x080A    //TX_PREEQ_BIN_MIC1_3
+694    0x0B09    //TX_PREEQ_BIN_MIC1_4
+695    0x0A06    //TX_PREEQ_BIN_MIC1_5
+696    0x0606    //TX_PREEQ_BIN_MIC1_6
+697    0x0605    //TX_PREEQ_BIN_MIC1_7
+698    0x050A    //TX_PREEQ_BIN_MIC1_8
+699    0x1505    //TX_PREEQ_BIN_MIC1_9
+700    0x0506    //TX_PREEQ_BIN_MIC1_10
+701    0x0615    //TX_PREEQ_BIN_MIC1_11
+702    0x1516    //TX_PREEQ_BIN_MIC1_12
+703    0x2021    //TX_PREEQ_BIN_MIC1_13
+704    0x2021    //TX_PREEQ_BIN_MIC1_14
+705    0x2021    //TX_PREEQ_BIN_MIC1_15
+706    0x0800    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0004    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0016    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x006C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+10    0x065B    //RX_PGA
+11    0x7E56    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0014    //RX_NS_LVL_CTRL
+23    0xF400    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x00C8    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0012    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0025    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0034    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x004D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0074    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x4000    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x4000    //RX_TDDRC_ALPHA_UP_3
+9    0x4000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0001    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x6000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x4000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03C3    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4870    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4850    //RX_FDEQ_GAIN_6
+46    0x485C    //RX_FDEQ_GAIN_7
+47    0x5C60    //RX_FDEQ_GAIN_8
+48    0x685C    //RX_FDEQ_GAIN_9
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0402    //RX_FDEQ_BIN_3
+67    0x0504    //RX_FDEQ_BIN_4
+68    0x0209    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -12273,4 +25851,3525 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x006C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+167    0x065B    //RX_PGA
+168    0x7E56    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF400    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x00C8    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0025    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x004D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HANDSFREE-HANDSFREE-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x047C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0048    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x007E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1134    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0662    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05D2    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0048    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
diff --git a/audio/felix/tuning/fortemedia/HEADSET.dat b/audio/felix/tuning/fortemedia/HEADSET.dat
index 9fd56dd..ebf6031 100644
--- a/audio/felix/tuning/fortemedia/HEADSET.dat
+++ b/audio/felix/tuning/fortemedia/HEADSET.dat
Binary files differ
diff --git a/audio/felix/tuning/fortemedia/HEADSET.mods b/audio/felix/tuning/fortemedia/HEADSET.mods
index 9f29f96..094c923 100644
--- a/audio/felix/tuning/fortemedia/HEADSET.mods
+++ b/audio/felix/tuning/fortemedia/HEADSET.mods
@@ -1,16 +1,17 @@
 #PLATFORM_NAME  gChip
 #EXPORT_FLAG  HEADSET
-#SINGLE_API_VER  1.1.6
-#SAVE_TIME  2021-08-20 16:33:31
+#SINGLE_API_VER  1.2.1
+#SAVE_TIME  2023-03-24 17:30:05
 
 #CASE_NAME  HEADSET-USB_BLACKBIRD-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
 2    0x0033    //TX_PATCH_REG
-3    0x2B68    //TX_SENDFUNC_MODE_0
+3    0x2F68    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0001    //TX_NUM_MIC
 6    0x0000    //TX_SAMPLINGFREQ_SIG
@@ -258,12 +259,12 @@
 248    0xFA00    //TX_THR_SN_EST_6
 249    0xFA00    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
-252    0x0000    //TX_DELTA_THR_SN_EST_2
-253    0x0400    //TX_DELTA_THR_SN_EST_3
+251    0x0000    //TX_DELTA_THR_SN_EST_1
+252    0x0400    //TX_DELTA_THR_SN_EST_2
+253    0x0000    //TX_DELTA_THR_SN_EST_3
 254    0x0000    //TX_DELTA_THR_SN_EST_4
 255    0x0000    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0000    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -290,28 +291,28 @@
 280    0x0400    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0014    //TX_NS_LVL_CTRL_4
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0014    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000D    //TX_MIN_GAIN_S_0
 290    0x0012    //TX_MIN_GAIN_S_1
 291    0x0012    //TX_MIN_GAIN_S_2
 292    0x0012    //TX_MIN_GAIN_S_3
-293    0x0012    //TX_MIN_GAIN_S_4
+293    0x000D    //TX_MIN_GAIN_S_4
 294    0x000D    //TX_MIN_GAIN_S_5
-295    0x000D    //TX_MIN_GAIN_S_6
+295    0x0012    //TX_MIN_GAIN_S_6
 296    0x000D    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x7FFF    //TX_SNRI_SUP_1
+301    0x5000    //TX_SNRI_SUP_1
 302    0x5000    //TX_SNRI_SUP_2
-303    0x5000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
 306    0x7FFF    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
@@ -322,20 +323,20 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x7FFF    //TX_A_POST_FILT_S_1
-316    0x1000    //TX_A_POST_FILT_S_2
-317    0x7000    //TX_A_POST_FILT_S_3
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x7000    //TX_A_POST_FILT_S_2
+317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
+320    0x7FFF    //TX_A_POST_FILT_S_6
 321    0x4000    //TX_A_POST_FILT_S_7
 322    0x0400    //TX_B_POST_FILT_0
-323    0x0400    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x4000    //TX_B_POST_FILT_4
+325    0x4000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
+328    0x0400    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
 331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
@@ -347,12 +348,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7E14    //TX_LAMBDA_PFILT
 339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7F00    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x6000    //TX_LAMBDA_PFILT_S_3
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x6000    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
 343    0x7C29    //TX_LAMBDA_PFILT_S_4
 344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
 346    0x7C29    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0400    //TX_A_PEPPER
@@ -374,7 +375,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0029    //TX_NOISE_TH_0
+367    0x003B    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x0900    //TX_NOISE_TH_1
@@ -386,11 +387,11 @@
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -398,22 +399,22 @@
 388    0x00CE    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0000    //TX_METAL_RTO_THR
@@ -521,16 +522,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -559,19 +560,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -778,12 +779,12 @@
 768    0x0065    //TX_MIC_CALIBRATION_3
 769    0x0044    //TX_MIC_PWR_BIAS_0
 770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x000B    //TX_GAIN_LIMIT_0
-774    0x000B    //TX_GAIN_LIMIT_1
-775    0x000B    //TX_GAIN_LIMIT_2
-776    0x000B    //TX_GAIN_LIMIT_3
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0000    //TX_GAIN_LIMIT_1
+775    0x0007    //TX_GAIN_LIMIT_2
+776    0x0007    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -896,16 +897,81 @@
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
 888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0x2000    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA43C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -927,7 +993,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -938,7 +1004,7 @@
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
@@ -949,11 +1015,11 @@
 41    0x4848    //RX_FDEQ_GAIN_2
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
+44    0x4748    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -977,7 +1043,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1019,22 +1085,22 @@
 111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01F4    //RX_TDDRC_DRC_GAIN
+124    0x0211    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000A    //RX_SPK_VOL
+126    0x280A    //RX_TPKA_FP
+127    0x032D    //RX_MIN_G_FP
+128    0x0A00    //RX_MAX_G_FP
+129    0x0009    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -1071,21 +1137,21 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01F4    //RX_TDDRC_DRC_GAIN
+124    0x0211    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -1096,7 +1162,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1120,7 +1186,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1170,21 +1236,21 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C8    //RX_TDDRC_DRC_GAIN
+124    0x0211    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -1195,7 +1261,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1219,7 +1285,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1258,7 +1324,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
+129    0x0010    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
 6    0x3000    //RX_TDDRC_ALPHA_UP_1
@@ -1269,21 +1335,21 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01D9    //RX_TDDRC_DRC_GAIN
+124    0x0211    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -1294,7 +1360,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1318,7 +1384,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1357,7 +1423,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
+129    0x001A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
 6    0x3000    //RX_TDDRC_ALPHA_UP_1
@@ -1368,14 +1434,14 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
@@ -1393,7 +1459,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1417,7 +1483,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1456,7 +1522,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0030    //RX_SPK_VOL
+129    0x002C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
 6    0x3000    //RX_TDDRC_ALPHA_UP_1
@@ -1467,14 +1533,14 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
@@ -1492,7 +1558,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1516,7 +1582,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1555,7 +1621,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x004A    //RX_SPK_VOL
+129    0x0049    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
 6    0x3000    //RX_TDDRC_ALPHA_UP_1
@@ -1566,14 +1632,14 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
@@ -1591,7 +1657,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1615,7 +1681,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1654,7 +1720,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0087    //RX_SPK_VOL
+129    0x007C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
 6    0x3000    //RX_TDDRC_ALPHA_UP_1
@@ -1665,14 +1731,14 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x5FFC    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x3000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
@@ -1690,7 +1756,7 @@
 45    0x4848    //RX_FDEQ_GAIN_6
 46    0x4848    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4040    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -1714,7 +1780,7 @@
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+72    0x0D0E    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -1755,15 +1821,867 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA43C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x280A    //RX_TPKA_FP
+284    0x032D    //RX_MIN_G_FP
+285    0x0A00    //RX_MAX_G_FP
+286    0x0009    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0009    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0049    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0211    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4040    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-USB_BLACKBIRD-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
 2    0x0033    //TX_PATCH_REG
-3    0x2B68    //TX_SENDFUNC_MODE_0
+3    0x2F68    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0001    //TX_NUM_MIC
 6    0x0001    //TX_SAMPLINGFREQ_SIG
@@ -1910,7 +2828,7 @@
 147    0x0080    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x4500    //TX_EAD_THR
+150    0x36B0    //TX_EAD_THR
 151    0x0800    //TX_THR_RE_EST
 152    0x0800    //TX_MIN_EQ_RE_EST_0
 153    0x0800    //TX_MIN_EQ_RE_EST_1
@@ -2002,7 +2920,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xFA00    //TX_THR_SN_EST_1
 244    0xF700    //TX_THR_SN_EST_2
 245    0xFC00    //TX_THR_SN_EST_3
@@ -2011,20 +2929,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -2042,18 +2960,18 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x0018    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x001C    //TX_NS_LVL_CTRL_3
-285    0x0012    //TX_NS_LVL_CTRL_4
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x001C    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
-287    0x000F    //TX_NS_LVL_CTRL_6
+287    0x0018    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x0009    //TX_MIN_GAIN_S_4
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0009    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
 295    0x000C    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
@@ -2061,10 +2979,10 @@
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x7FFF    //TX_SNRI_SUP_1
-302    0x6000    //TX_SNRI_SUP_2
-303    0x2000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+301    0x6000    //TX_SNRI_SUP_1
+302    0x2000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
 306    0x7FFF    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
@@ -2075,17 +2993,17 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
-324    0x1000    //TX_B_POST_FILT_2
-325    0x3000    //TX_B_POST_FILT_3
+324    0x3000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
 326    0x1000    //TX_B_POST_FILT_4
 327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
@@ -2100,12 +3018,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7CCD    //TX_LAMBDA_PFILT
 339    0x7B00    //TX_LAMBDA_PFILT_S_0
-340    0x7F00    //TX_LAMBDA_PFILT_S_1
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
 341    0x7B00    //TX_LAMBDA_PFILT_S_2
 342    0x7B00    //TX_LAMBDA_PFILT_S_3
 343    0x7B00    //TX_LAMBDA_PFILT_S_4
 344    0x7B00    //TX_LAMBDA_PFILT_S_5
-345    0x7B00    //TX_LAMBDA_PFILT_S_6
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
 346    0x7B00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0400    //TX_A_PEPPER
@@ -2127,7 +3045,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0065    //TX_NOISE_TH_0
+367    0x0102    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x0900    //TX_NOISE_TH_1
@@ -2139,11 +3057,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00FB    //TX_NOISE_TH_6
-379    0x0029    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -2151,22 +3069,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0029    //TX_MINENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -2274,16 +3192,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -2312,19 +3230,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -2531,12 +3449,12 @@
 768    0x0062    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
 770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x000C    //TX_GAIN_LIMIT_0
-774    0x000C    //TX_GAIN_LIMIT_1
-775    0x000C    //TX_GAIN_LIMIT_2
-776    0x000C    //TX_GAIN_LIMIT_3
+771    0x0048    //TX_MIC_PWR_BIAS_2
+772    0x0048    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0000    //TX_GAIN_LIMIT_1
+775    0x0003    //TX_GAIN_LIMIT_2
+776    0x0003    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -2657,8 +3575,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA43C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -2680,7 +3663,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -2784,9 +3767,9 @@
 123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x01AE    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
+126    0x280A    //RX_TPKA_FP
+127    0x032D    //RX_MIN_G_FP
+128    0x0A00    //RX_MAX_G_FP
 129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
@@ -2824,13 +3807,13 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
@@ -2838,7 +3821,7 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01AE    //RX_TDDRC_DRC_GAIN
+124    0x01A0    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -2849,10 +3832,10 @@
 45    0x484B    //RX_FDEQ_GAIN_6
 46    0x4B48    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4846    //RX_FDEQ_GAIN_10
 50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
+51    0x3F3F    //RX_FDEQ_GAIN_12
 52    0x4248    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -2923,13 +3906,13 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
@@ -2937,7 +3920,7 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01B6    //RX_TDDRC_DRC_GAIN
+124    0x01A0    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
@@ -2948,10 +3931,10 @@
 45    0x484B    //RX_FDEQ_GAIN_6
 46    0x4B48    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4846    //RX_FDEQ_GAIN_10
 50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
+51    0x3F3F    //RX_FDEQ_GAIN_12
 52    0x4248    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -3022,409 +4005,13 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x484B    //RX_FDEQ_GAIN_6
-46    0x4B48    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4846    //RX_FDEQ_GAIN_10
-50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
-52    0x4248    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001D    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x484B    //RX_FDEQ_GAIN_6
-46    0x4B48    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4846    //RX_FDEQ_GAIN_10
-50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
-52    0x4248    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0030    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x484B    //RX_FDEQ_GAIN_6
-46    0x4B48    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4846    //RX_FDEQ_GAIN_10
-50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
-52    0x4248    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0051    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x01C9    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x484B    //RX_FDEQ_GAIN_6
-46    0x4B48    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4846    //RX_FDEQ_GAIN_10
-50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
-52    0x4248    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0095    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1D00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
@@ -3443,10 +4030,406 @@
 45    0x484B    //RX_FDEQ_GAIN_6
 46    0x4B48    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4846    //RX_FDEQ_GAIN_10
 50    0x403F    //RX_FDEQ_GAIN_11
-51    0x3F40    //RX_FDEQ_GAIN_12
+51    0x3F3F    //RX_FDEQ_GAIN_12
+52    0x4248    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01A0    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x484B    //RX_FDEQ_GAIN_6
+46    0x4B48    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4444    //RX_FDEQ_GAIN_9
+49    0x4846    //RX_FDEQ_GAIN_10
+50    0x403F    //RX_FDEQ_GAIN_11
+51    0x3F3F    //RX_FDEQ_GAIN_12
+52    0x4248    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0031    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01A0    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x484B    //RX_FDEQ_GAIN_6
+46    0x4B48    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4444    //RX_FDEQ_GAIN_9
+49    0x4846    //RX_FDEQ_GAIN_10
+50    0x403F    //RX_FDEQ_GAIN_11
+51    0x3F3F    //RX_FDEQ_GAIN_12
+52    0x4248    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0052    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01A0    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x484B    //RX_FDEQ_GAIN_6
+46    0x4B48    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4444    //RX_FDEQ_GAIN_9
+49    0x4846    //RX_FDEQ_GAIN_10
+50    0x403F    //RX_FDEQ_GAIN_11
+51    0x3F3F    //RX_FDEQ_GAIN_12
+52    0x4248    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x008B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01A0    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x484B    //RX_FDEQ_GAIN_6
+46    0x4B48    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4444    //RX_FDEQ_GAIN_9
+49    0x4846    //RX_FDEQ_GAIN_10
+50    0x403F    //RX_FDEQ_GAIN_11
+51    0x3F3F    //RX_FDEQ_GAIN_12
 52    0x4248    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -3508,15 +4491,867 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA43C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F40    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1D00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01AE    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x280A    //RX_TPKA_FP
+284    0x032D    //RX_MIN_G_FP
+285    0x0A00    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0031    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0052    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x008B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01A0    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484B    //RX_FDEQ_GAIN_6
+203    0x4B48    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4846    //RX_FDEQ_GAIN_10
+207    0x403F    //RX_FDEQ_GAIN_11
+208    0x3F3F    //RX_FDEQ_GAIN_12
+209    0x4248    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-USB_BLACKBIRD-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
 2    0x0033    //TX_PATCH_REG
-3    0x6B68    //TX_SENDFUNC_MODE_0
+3    0x6F68    //TX_SENDFUNC_MODE_0
 4    0x0001    //TX_SENDFUNC_MODE_1
 5    0x0001    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
@@ -3710,9 +5545,9 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7D00    //TX_DTD_THR1_0
+197    0x6590    //TX_DTD_THR1_0
 198    0x7D00    //TX_DTD_THR1_1
-199    0x7FFF    //TX_DTD_THR1_2
+199    0x6590    //TX_DTD_THR1_2
 200    0x7FFF    //TX_DTD_THR1_3
 201    0x7FFF    //TX_DTD_THR1_4
 202    0x7FFF    //TX_DTD_THR1_5
@@ -3755,7 +5590,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xFA00    //TX_THR_SN_EST_1
 244    0xF700    //TX_THR_SN_EST_2
 245    0xFA00    //TX_THR_SN_EST_3
@@ -3764,20 +5599,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -3795,18 +5630,18 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x0018    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0012    //TX_NS_LVL_CTRL_4
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
-287    0x000F    //TX_NS_LVL_CTRL_6
+287    0x001C    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x0009    //TX_MIN_GAIN_S_4
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0009    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
 295    0x000C    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
@@ -3814,12 +5649,12 @@
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x7FFF    //TX_SNRI_SUP_1
-302    0x6000    //TX_SNRI_SUP_2
-303    0x5000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+301    0x6000    //TX_SNRI_SUP_1
+302    0x5000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x3000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x000E    //TX_G_LFNS
@@ -3828,17 +5663,17 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
-324    0x1000    //TX_B_POST_FILT_2
-325    0x3000    //TX_B_POST_FILT_3
+324    0x3000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
 326    0x1000    //TX_B_POST_FILT_4
 327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
@@ -3853,12 +5688,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7CCD    //TX_LAMBDA_PFILT
 339    0x7B00    //TX_LAMBDA_PFILT_S_0
-340    0x7F00    //TX_LAMBDA_PFILT_S_1
-341    0x7B00    //TX_LAMBDA_PFILT_S_2
-342    0x7000    //TX_LAMBDA_PFILT_S_3
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7000    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
 343    0x7B00    //TX_LAMBDA_PFILT_S_4
 344    0x7B00    //TX_LAMBDA_PFILT_S_5
-345    0x7B00    //TX_LAMBDA_PFILT_S_6
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
 346    0x7B00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0400    //TX_A_PEPPER
@@ -3880,23 +5715,23 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x00FA    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
+370    0x0C80    //TX_NOISE_TH_1
 371    0x00C8    //TX_NOISE_TH_2
 372    0x2904    //TX_NOISE_TH_3
-373    0x0FA0    //TX_NOISE_TH_4
+373    0x07D0    //TX_NOISE_TH_4
 374    0x157C    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -3904,22 +5739,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0064    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -4027,16 +5862,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -4065,19 +5900,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -4283,13 +6118,13 @@
 767    0x0062    //TX_MIC_CALIBRATION_2
 768    0x0062    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
+770    0x0050    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x000C    //TX_GAIN_LIMIT_0
-774    0x000C    //TX_GAIN_LIMIT_1
-775    0x000C    //TX_GAIN_LIMIT_2
-776    0x000C    //TX_GAIN_LIMIT_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0002    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
@@ -4402,7 +6237,7 @@
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
 891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
@@ -4410,8 +6245,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x243C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -4537,9 +6437,9 @@
 123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x023E    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
+126    0x0D90    //RX_TPKA_FP
+127    0x032D    //RX_MIN_G_FP
+128    0x0A00    //RX_MAX_G_FP
 129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
@@ -4577,38 +6477,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -4665,7 +6565,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000B    //RX_SPK_VOL
+129    0x000A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -4676,38 +6576,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -4764,7 +6664,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0012    //RX_SPK_VOL
+129    0x0011    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -4775,38 +6675,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0236    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -4863,7 +6763,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001F    //RX_SPK_VOL
+129    0x001D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -4874,38 +6774,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -4962,7 +6862,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0033    //RX_SPK_VOL
+129    0x0030    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -4973,38 +6873,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -5061,7 +6961,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0055    //RX_SPK_VOL
+129    0x0050    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -5072,38 +6972,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -5160,7 +7060,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x008F    //RX_SPK_VOL
+129    0x0089    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
 6    0x5000    //RX_TDDRC_ALPHA_UP_1
@@ -5171,38 +7071,38 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x65AD    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x5000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x023E    //RX_TDDRC_DRC_GAIN
+124    0x04CA    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4E52    //RX_FDEQ_GAIN_0
-40    0x5252    //RX_FDEQ_GAIN_1
-41    0x5252    //RX_FDEQ_GAIN_2
-42    0x5250    //RX_FDEQ_GAIN_3
-43    0x4C46    //RX_FDEQ_GAIN_4
-44    0x4748    //RX_FDEQ_GAIN_5
-45    0x5768    //RX_FDEQ_GAIN_6
-46    0x6162    //RX_FDEQ_GAIN_7
-47    0x5252    //RX_FDEQ_GAIN_8
-48    0x5256    //RX_FDEQ_GAIN_9
-49    0x5248    //RX_FDEQ_GAIN_10
-50    0x3434    //RX_FDEQ_GAIN_11
-51    0x3436    //RX_FDEQ_GAIN_12
-52    0x2A18    //RX_FDEQ_GAIN_13
-53    0x1830    //RX_FDEQ_GAIN_14
-54    0x3648    //RX_FDEQ_GAIN_15
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -5261,10 +7161,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x043C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E52    //RX_FDEQ_GAIN_0
+197    0x5252    //RX_FDEQ_GAIN_1
+198    0x5252    //RX_FDEQ_GAIN_2
+199    0x5250    //RX_FDEQ_GAIN_3
+200    0x4C46    //RX_FDEQ_GAIN_4
+201    0x4748    //RX_FDEQ_GAIN_5
+202    0x5768    //RX_FDEQ_GAIN_6
+203    0x6162    //RX_FDEQ_GAIN_7
+204    0x5252    //RX_FDEQ_GAIN_8
+205    0x5256    //RX_FDEQ_GAIN_9
+206    0x5248    //RX_FDEQ_GAIN_10
+207    0x3434    //RX_FDEQ_GAIN_11
+208    0x3436    //RX_FDEQ_GAIN_12
+209    0x2A18    //RX_FDEQ_GAIN_13
+210    0x1830    //RX_FDEQ_GAIN_14
+211    0x3648    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x023E    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x0D90    //RX_TPKA_FP
+284    0x032D    //RX_MIN_G_FP
+285    0x0A00    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0030    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0050    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0089    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-USB_BLACKBIRD-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -5517,10 +8269,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -5548,31 +8300,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
-283    0x0020    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+282    0x0020    //TX_NS_LVL_CTRL_1
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x0800    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x1000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+301    0x1000    //TX_SNRI_SUP_1
+302    0x7000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -5589,8 +8341,8 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
@@ -5633,7 +8385,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0020    //TX_NOISE_TH_0
+367    0x04E8    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x02A6    //TX_NOISE_TH_1
@@ -5645,11 +8397,11 @@
 376    0x0001    //TX_NOISE_TH_5_3
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x02BC    //TX_NOISE_TH_6
-379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -5657,22 +8409,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0020    //TX_MINENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x2900    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -5780,16 +8532,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -5818,19 +8570,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -6163,8 +8915,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x242C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -6197,25 +9014,25 @@
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6278,22 +9095,22 @@
 111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000A    //RX_SPK_VOL
+126    0x280A    //RX_TPKA_FP
+127    0x032D    //RX_MIN_G_FP
+128    0x0A00    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -6330,35 +9147,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6418,7 +9235,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000A    //RX_SPK_VOL
+129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6429,35 +9246,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6517,7 +9334,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0010    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6528,35 +9345,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6616,7 +9433,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001C    //RX_SPK_VOL
+129    0x001F    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6627,35 +9444,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6715,7 +9532,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x002F    //RX_SPK_VOL
+129    0x0034    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6726,35 +9543,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6814,7 +9631,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x004F    //RX_SPK_VOL
+129    0x0056    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6825,35 +9642,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -6913,7 +9730,7 @@
 108    0x5333    //RX_FDDRC_SLANT_1_2
 109    0x5333    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0081    //RX_SPK_VOL
+129    0x0090    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
 6    0x1000    //RX_TDDRC_ALPHA_UP_1
@@ -6924,35 +9741,35 @@
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
 32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+33    0x7220    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
+124    0x0231    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4852    //RX_FDEQ_GAIN_0
-40    0x5858    //RX_FDEQ_GAIN_1
-41    0x5C5A    //RX_FDEQ_GAIN_2
-42    0x4F50    //RX_FDEQ_GAIN_3
-43    0x5A61    //RX_FDEQ_GAIN_4
-44    0x605B    //RX_FDEQ_GAIN_5
-45    0x5050    //RX_FDEQ_GAIN_6
-46    0x5050    //RX_FDEQ_GAIN_7
-47    0x5044    //RX_FDEQ_GAIN_8
-48    0x3633    //RX_FDEQ_GAIN_9
-49    0x3424    //RX_FDEQ_GAIN_10
-50    0x1A24    //RX_FDEQ_GAIN_11
-51    0x2B37    //RX_FDEQ_GAIN_12
+39    0x4858    //RX_FDEQ_GAIN_0
+40    0x6265    //RX_FDEQ_GAIN_1
+41    0x6568    //RX_FDEQ_GAIN_2
+42    0x5654    //RX_FDEQ_GAIN_3
+43    0x676E    //RX_FDEQ_GAIN_4
+44    0x6E6B    //RX_FDEQ_GAIN_5
+45    0x5B5F    //RX_FDEQ_GAIN_6
+46    0x5864    //RX_FDEQ_GAIN_7
+47    0x6548    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
 52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
@@ -7014,10 +9831,3532 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x242C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x280A    //RX_TPKA_FP
+284    0x032D    //RX_MIN_G_FP
+285    0x0A00    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001F    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0056    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0090    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0231    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4858    //RX_FDEQ_GAIN_0
+197    0x6265    //RX_FDEQ_GAIN_1
+198    0x6568    //RX_FDEQ_GAIN_2
+199    0x5654    //RX_FDEQ_GAIN_3
+200    0x676E    //RX_FDEQ_GAIN_4
+201    0x6E6B    //RX_FDEQ_GAIN_5
+202    0x5B5F    //RX_FDEQ_GAIN_6
+203    0x5864    //RX_FDEQ_GAIN_7
+204    0x6548    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-USB_BLACKBIRD-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x6F68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x6D60    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x6590    //TX_DTD_THR1_0
+198    0x7D00    //TX_DTD_THR1_1
+199    0x6590    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xF700    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000F    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x001C    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x0009    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x6000    //TX_SNRI_SUP_1
+302    0x5000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x3000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x3000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7CCD    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7000    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0400    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x00FA    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x0C80    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x2904    //TX_NOISE_TH_3
+373    0x07D0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0064    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4040    //TX_FDEQ_GAIN_6
+574    0x4040    //TX_FDEQ_GAIN_7
+575    0x4040    //TX_FDEQ_GAIN_8
+576    0x3838    //TX_FDEQ_GAIN_9
+577    0x3838    //TX_FDEQ_GAIN_10
+578    0x3828    //TX_FDEQ_GAIN_11
+579    0x2828    //TX_FDEQ_GAIN_12
+580    0x2828    //TX_FDEQ_GAIN_13
+581    0x1C1C    //TX_FDEQ_GAIN_14
+582    0x1C1C    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x284A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0050    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0002    //TX_GAIN_LIMIT_1
+775    0x0000    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0020    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x07F2    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x003C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4E52    //RX_FDEQ_GAIN_0
+40    0x5252    //RX_FDEQ_GAIN_1
+41    0x5252    //RX_FDEQ_GAIN_2
+42    0x5250    //RX_FDEQ_GAIN_3
+43    0x4C46    //RX_FDEQ_GAIN_4
+44    0x4748    //RX_FDEQ_GAIN_5
+45    0x5768    //RX_FDEQ_GAIN_6
+46    0x6162    //RX_FDEQ_GAIN_7
+47    0x5252    //RX_FDEQ_GAIN_8
+48    0x5256    //RX_FDEQ_GAIN_9
+49    0x5248    //RX_FDEQ_GAIN_10
+50    0x3434    //RX_FDEQ_GAIN_11
+51    0x3436    //RX_FDEQ_GAIN_12
+52    0x2A18    //RX_FDEQ_GAIN_13
+53    0x1830    //RX_FDEQ_GAIN_14
+54    0x3648    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x023E    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x0D90    //RX_TPKA_FP
+127    0x032D    //RX_MIN_G_FP
+128    0x0A00    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001D    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0030    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0050    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0089    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7220    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1800    //RX_TDDRC_THRD_2
+115    0x1800    //RX_TDDRC_THRD_3
+116    0x7FFF    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x04CA    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x6270    //RX_FDEQ_GAIN_0
+40    0x7A70    //RX_FDEQ_GAIN_1
+41    0x7270    //RX_FDEQ_GAIN_2
+42    0x6A70    //RX_FDEQ_GAIN_3
+43    0x645A    //RX_FDEQ_GAIN_4
+44    0x5A5E    //RX_FDEQ_GAIN_5
+45    0x6E72    //RX_FDEQ_GAIN_6
+46    0x7268    //RX_FDEQ_GAIN_7
+47    0x665A    //RX_FDEQ_GAIN_8
+48    0x5A5A    //RX_FDEQ_GAIN_9
+49    0x5A64    //RX_FDEQ_GAIN_10
+50    0x6448    //RX_FDEQ_GAIN_11
+51    0x4949    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x284A    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x003C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4E52    //RX_FDEQ_GAIN_0
+197    0x5252    //RX_FDEQ_GAIN_1
+198    0x5252    //RX_FDEQ_GAIN_2
+199    0x5250    //RX_FDEQ_GAIN_3
+200    0x4C46    //RX_FDEQ_GAIN_4
+201    0x4748    //RX_FDEQ_GAIN_5
+202    0x5768    //RX_FDEQ_GAIN_6
+203    0x6162    //RX_FDEQ_GAIN_7
+204    0x5252    //RX_FDEQ_GAIN_8
+205    0x5256    //RX_FDEQ_GAIN_9
+206    0x5248    //RX_FDEQ_GAIN_10
+207    0x3434    //RX_FDEQ_GAIN_11
+208    0x3436    //RX_FDEQ_GAIN_12
+209    0x2A18    //RX_FDEQ_GAIN_13
+210    0x1830    //RX_FDEQ_GAIN_14
+211    0x3648    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x023E    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x0D90    //RX_TPKA_FP
+284    0x032D    //RX_MIN_G_FP
+285    0x0A00    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0030    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0050    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0089    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7220    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x04CA    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x6270    //RX_FDEQ_GAIN_0
+197    0x7A70    //RX_FDEQ_GAIN_1
+198    0x7270    //RX_FDEQ_GAIN_2
+199    0x6A70    //RX_FDEQ_GAIN_3
+200    0x645A    //RX_FDEQ_GAIN_4
+201    0x5A5E    //RX_FDEQ_GAIN_5
+202    0x6E72    //RX_FDEQ_GAIN_6
+203    0x7268    //RX_FDEQ_GAIN_7
+204    0x665A    //RX_FDEQ_GAIN_8
+205    0x5A5A    //RX_FDEQ_GAIN_9
+206    0x5A64    //RX_FDEQ_GAIN_10
+207    0x6448    //RX_FDEQ_GAIN_11
+208    0x4949    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x284A    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -7334,20 +13673,20 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
-316    0x1000    //TX_A_POST_FILT_S_2
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
 320    0x4000    //TX_A_POST_FILT_S_6
 321    0x4000    //TX_A_POST_FILT_S_7
 322    0x0400    //TX_B_POST_FILT_0
-323    0x0400    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
+328    0x0400    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
 331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
@@ -7386,7 +13725,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x003B    //TX_NOISE_TH_0
 368    0x1B58    //TX_NOISE_TH_0_2
 369    0x2134    //TX_NOISE_TH_0_3
 370    0x02BC    //TX_NOISE_TH_1
@@ -7398,11 +13737,11 @@
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x0032    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -7410,22 +13749,22 @@
 388    0x00CE    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0000    //TX_METAL_RTO_THR
@@ -7533,16 +13872,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -7571,19 +13910,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
 567    0x6048    //TX_FDEQ_GAIN_0
@@ -7593,9 +13932,9 @@
 571    0x4848    //TX_FDEQ_GAIN_4
 572    0x4848    //TX_FDEQ_GAIN_5
 573    0x4844    //TX_FDEQ_GAIN_6
-574    0x4444    //TX_FDEQ_GAIN_7
-575    0x4040    //TX_FDEQ_GAIN_8
-576    0x3C3C    //TX_FDEQ_GAIN_9
+574    0x4242    //TX_FDEQ_GAIN_7
+575    0x3C34    //TX_FDEQ_GAIN_8
+576    0x343A    //TX_FDEQ_GAIN_9
 577    0x4848    //TX_FDEQ_GAIN_10
 578    0x4848    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
@@ -7885,7 +14224,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
+866    0x0650    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -7910,14 +14249,79 @@
 888    0x00C8    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA02C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -7939,7 +14343,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -8105,10 +14509,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8204,10 +14608,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8303,10 +14707,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8402,10 +14806,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8501,10 +14905,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8600,10 +15004,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8699,10 +15103,10 @@
 42    0x4848    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
+45    0x4844    //RX_FDEQ_GAIN_6
+46    0x4444    //RX_FDEQ_GAIN_7
 47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
+48    0x4444    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -8767,10 +15171,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4844    //RX_FDEQ_GAIN_6
+203    0x4444    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4444    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -9014,7 +16270,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF600    //TX_THR_SN_EST_2
 245    0xF400    //TX_THR_SN_EST_3
@@ -9023,20 +16279,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -9054,16 +16310,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -9087,12 +16343,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -9139,7 +16395,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0102    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
@@ -9151,11 +16407,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -9163,22 +16419,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0000    //TX_METAL_RTO_THR
@@ -9286,16 +16542,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -9324,22 +16580,22 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
-567    0x5850    //TX_FDEQ_GAIN_0
+567    0x6056    //TX_FDEQ_GAIN_0
 568    0x4848    //TX_FDEQ_GAIN_1
 569    0x4848    //TX_FDEQ_GAIN_2
 570    0x4848    //TX_FDEQ_GAIN_3
@@ -9638,7 +16894,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
+866    0x0619    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -9663,14 +16919,79 @@
 888    0x00C8    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA02C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -9692,7 +17013,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -10520,10 +17841,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -10767,7 +18940,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF600    //TX_THR_SN_EST_2
 245    0xF400    //TX_THR_SN_EST_3
@@ -10776,20 +18949,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -10807,16 +18980,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -10840,12 +19013,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -10892,7 +19065,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0383    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
@@ -10904,11 +19077,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -10916,22 +19089,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x2900    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -11039,16 +19212,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -11077,19 +19250,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -11414,16 +19587,81 @@
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
 888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -12273,10 +20511,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0009    //TX_OPERATION_MODE_1
@@ -12529,10 +21619,10 @@
 248    0xF600    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
@@ -12560,31 +21650,31 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x2000    //TX_B_POST_FLT_1
 281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
+282    0x0016    //TX_NS_LVL_CTRL_1
 283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
 286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
+287    0x0019    //TX_NS_LVL_CTRL_6
 288    0x0010    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
+290    0x000C    //TX_MIN_GAIN_S_1
 291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
+295    0x0011    //TX_MIN_GAIN_S_6
 296    0x000C    //TX_MIN_GAIN_S_7
 297    0x7FFF    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
+301    0x7000    //TX_SNRI_SUP_1
 302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
 305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
+306    0x6000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0016    //TX_G_LFNS
@@ -12601,1760 +21691,7 @@
 320    0x6000    //TX_A_POST_FILT_S_6
 321    0x6000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x2000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7CCD    //TX_LAMBDA_PFILT
-339    0x7CCD    //TX_LAMBDA_PFILT_S_0
-340    0x7CCD    //TX_LAMBDA_PFILT_S_1
-341    0x7CCD    //TX_LAMBDA_PFILT_S_2
-342    0x7CCD    //TX_LAMBDA_PFILT_S_3
-343    0x7CCD    //TX_LAMBDA_PFILT_S_4
-344    0x7CCD    //TX_LAMBDA_PFILT_S_5
-345    0x7CCD    //TX_LAMBDA_PFILT_S_6
-346    0x7CCD    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0500    //TX_A_PEPPER
-349    0x1600    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0000    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0020    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x02A6    //TX_NOISE_TH_1
-371    0x04B0    //TX_NOISE_TH_2
-372    0x3194    //TX_NOISE_TH_3
-373    0x0960    //TX_NOISE_TH_4
-374    0x5555    //TX_NOISE_TH_5
-375    0x3FF4    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x02BC    //TX_NOISE_TH_6
-379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0020    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4848    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4848    //TX_FDEQ_GAIN_9
-577    0x4848    //TX_FDEQ_GAIN_10
-578    0x4848    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0203    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0405    //TX_FDEQ_BIN_3
-595    0x0607    //TX_FDEQ_BIN_4
-596    0x0809    //TX_FDEQ_BIN_5
-597    0x0A0B    //TX_FDEQ_BIN_6
-598    0x0C0D    //TX_FDEQ_BIN_7
-599    0x0E0F    //TX_FDEQ_BIN_8
-600    0x1011    //TX_FDEQ_BIN_9
-601    0x1214    //TX_FDEQ_BIN_10
-602    0x1618    //TX_FDEQ_BIN_11
-603    0x1C1C    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x2011    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0E10    //TX_PREEQ_BIN_MIC0_0
-642    0x1010    //TX_PREEQ_BIN_MIC0_1
-643    0x1010    //TX_PREEQ_BIN_MIC0_2
-644    0x1010    //TX_PREEQ_BIN_MIC0_3
-645    0x1010    //TX_PREEQ_BIN_MIC0_4
-646    0x1010    //TX_PREEQ_BIN_MIC0_5
-647    0x1010    //TX_PREEQ_BIN_MIC0_6
-648    0x1010    //TX_PREEQ_BIN_MIC0_7
-649    0x1010    //TX_PREEQ_BIN_MIC0_8
-650    0x1010    //TX_PREEQ_BIN_MIC0_9
-651    0x1010    //TX_PREEQ_BIN_MIC0_10
-652    0x1010    //TX_PREEQ_BIN_MIC0_11
-653    0x1010    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
-655    0x1010    //TX_PREEQ_BIN_MIC0_14
-656    0x0200    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0E10    //TX_PREEQ_BIN_MIC1_0
-691    0x1010    //TX_PREEQ_BIN_MIC1_1
-692    0x1010    //TX_PREEQ_BIN_MIC1_2
-693    0x1010    //TX_PREEQ_BIN_MIC1_3
-694    0x1010    //TX_PREEQ_BIN_MIC1_4
-695    0x1010    //TX_PREEQ_BIN_MIC1_5
-696    0x1010    //TX_PREEQ_BIN_MIC1_6
-697    0x1010    //TX_PREEQ_BIN_MIC1_7
-698    0x1010    //TX_PREEQ_BIN_MIC1_8
-699    0x1010    //TX_PREEQ_BIN_MIC1_9
-700    0x1010    //TX_PREEQ_BIN_MIC1_10
-701    0x1010    //TX_PREEQ_BIN_MIC1_11
-702    0x1010    //TX_PREEQ_BIN_MIC1_12
-703    0x1010    //TX_PREEQ_BIN_MIC1_13
-704    0x1010    //TX_PREEQ_BIN_MIC1_14
-705    0x0200    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0C00    //TX_TDDRC_ALPHA_UP_01
-784    0x0C00    //TX_TDDRC_ALPHA_UP_02
-785    0x0C00    //TX_TDDRC_ALPHA_UP_03
-786    0x0C00    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0000    //TX_DEADMIC_SILENCE_TH
-817    0x0000    //TX_MIC_DEGRADE_TH
-818    0x0000    //TX_DEADMIC_CNT
-819    0x0000    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0000    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0001    //TX_TDDRC_THRD_1
-856    0x1900    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x3000    //TX_TDDRC_SLANT_0
-859    0x7B00    //TX_TDDRC_SLANT_1
-860    0x0C00    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x07F2    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x002C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7B02    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0500    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000A    //RX_NS_LVL_CTRL
-23    0xF600    //RX_THR_SN_EST
-24    0x7000    //RX_LAMBDA_PFILT
-25    0x000A    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0013    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0036    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0009    //TX_OPERATION_MODE_0
-1    0x0008    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2B68    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0001    //TX_NUM_MIC
-6    0x0000    //TX_SAMPLINGFREQ_SIG
-7    0x0000    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x009B    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0B80    //TX_PGA_0
-28    0x0800    //TX_PGA_1
-29    0x0000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0001    //TX_MIC_DATA_SRC1
-43    0x0002    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3E00    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0800    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7646    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x7CCC    //TX_THR_PITCH_DET_0
-131    0x7000    //TX_THR_PITCH_DET_1
-132    0x6333    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x001E    //TX_TAIL_LENGTH
-147    0x0010    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x1000    //TX_THR_RE_EST
-152    0x1000    //TX_MIN_EQ_RE_EST_0
-153    0x0800    //TX_MIN_EQ_RE_EST_1
-154    0x0800    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x0800    //TX_MIN_EQ_RE_EST_4
-157    0x0800    //TX_MIN_EQ_RE_EST_5
-158    0x0800    //TX_MIN_EQ_RE_EST_6
-159    0x0800    //TX_MIN_EQ_RE_EST_7
-160    0x0800    //TX_MIN_EQ_RE_EST_8
-161    0x0800    //TX_MIN_EQ_RE_EST_9
-162    0x0800    //TX_MIN_EQ_RE_EST_10
-163    0x0800    //TX_MIN_EQ_RE_EST_11
-164    0x0800    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
-166    0x2000    //TX_LAMBDA_CB_NLE
-167    0x2000    //TX_C_POST_FLT
-168    0x2000    //TX_GAIN_NP
-169    0x00C8    //TX_SE_HOLD_N
-170    0x0064    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x5000    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7F00    //TX_DTD_THR1_2
-200    0x7FFF    //TX_DTD_THR1_3
-201    0x7FFF    //TX_DTD_THR1_4
-202    0x7FFF    //TX_DTD_THR1_5
-203    0x7FFF    //TX_DTD_THR1_6
-204    0x2000    //TX_DTD_THR2_0
-205    0x2000    //TX_DTD_THR2_1
-206    0x2000    //TX_DTD_THR2_2
-207    0x2000    //TX_DTD_THR2_3
-208    0x2000    //TX_DTD_THR2_4
-209    0x2000    //TX_DTD_THR2_5
-210    0x2000    //TX_DTD_THR2_6
-211    0x4100    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x03E8    //TX_DT_CUT_K
-214    0x1000    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0010    //TX_EPD_OFFSET_00
-233    0x0010    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x7FFF    //TX_DTD_THR1_7
-238    0x7FFF    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xFA00    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xFA00    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xFA00    //TX_THR_SN_EST_5
-248    0xFA00    //TX_THR_SN_EST_6
-249    0xFA00    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
-252    0x0000    //TX_DELTA_THR_SN_EST_2
-253    0x0000    //TX_DELTA_THR_SN_EST_3
-254    0x0000    //TX_DELTA_THR_SN_EST_4
-255    0x0000    //TX_DELTA_THR_SN_EST_5
-256    0x0000    //TX_DELTA_THR_SN_EST_6
-257    0x0000    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x0400    //TX_B_POST_FLT_0
-280    0x0400    //TX_B_POST_FLT_1
-281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0010    //TX_NS_LVL_CTRL_1
-283    0x0010    //TX_NS_LVL_CTRL_2
-284    0x0010    //TX_NS_LVL_CTRL_3
-285    0x0010    //TX_NS_LVL_CTRL_4
-286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x000D    //TX_MIN_GAIN_S_0
-290    0x000D    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
-292    0x000D    //TX_MIN_GAIN_S_3
-293    0x000D    //TX_MIN_GAIN_S_4
-294    0x000D    //TX_MIN_GAIN_S_5
-295    0x000D    //TX_MIN_GAIN_S_6
-296    0x000D    //TX_MIN_GAIN_S_7
-297    0x7FFF    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x7FFF    //TX_SNRI_SUP_1
-302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
-304    0x7FFF    //TX_SNRI_SUP_4
-305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0014    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
-316    0x1000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x4000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x4000    //TX_A_POST_FILT_S_6
-321    0x4000    //TX_A_POST_FILT_S_7
-322    0x0400    //TX_B_POST_FILT_0
-323    0x0400    //TX_B_POST_FILT_1
+323    0x4000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
@@ -14369,1772 +21706,19 @@
 335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
 336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7E14    //TX_LAMBDA_PFILT
-339    0x7C29    //TX_LAMBDA_PFILT_S_0
-340    0x7C29    //TX_LAMBDA_PFILT_S_1
-341    0x7C29    //TX_LAMBDA_PFILT_S_2
-342    0x7C29    //TX_LAMBDA_PFILT_S_3
-343    0x7C29    //TX_LAMBDA_PFILT_S_4
-344    0x7C29    //TX_LAMBDA_PFILT_S_5
-345    0x7C29    //TX_LAMBDA_PFILT_S_6
-346    0x7C29    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x0FA0    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x4000    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0000    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
-368    0x1B58    //TX_NOISE_TH_0_2
-369    0x2134    //TX_NOISE_TH_0_3
-370    0x02BC    //TX_NOISE_TH_1
-371    0x1F40    //TX_NOISE_TH_2
-372    0x4650    //TX_NOISE_TH_3
-373    0x7148    //TX_NOISE_TH_4
-374    0x044C    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x0000    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x0032    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
-385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
-387    0x0029    //TX_OUT_ENER_TH_NOISE
-388    0x00CE    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0002    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x7FFF    //TX_MIN_G_CTRL_SSNS
-409    0x0000    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x7FFF    //TX_NOISEDET_BOOST_TH
-412    0x0000    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0280    //TX_N_HOLD_HS
-416    0x006E    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0333    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2400    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0640    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x2000    //TX_WTA_EN_RTO_TH
-429    0x1400    //TX_TOP_ENER_TH_F
-430    0x0064    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x003C    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x0D9A    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x2A3D    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0230    //TX_NOR_OFF_THR
-498    0x0CCD    //TX_MORE_ON_700HZ_THR
-499    0x0000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0014    //TX_FDEQ_SUBNUM
-567    0x6048    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
-573    0x4844    //TX_FDEQ_GAIN_6
-574    0x4444    //TX_FDEQ_GAIN_7
-575    0x4040    //TX_FDEQ_GAIN_8
-576    0x3C3C    //TX_FDEQ_GAIN_9
-577    0x4848    //TX_FDEQ_GAIN_10
-578    0x4848    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0401    //TX_FDEQ_BIN_0
-592    0x0103    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0304    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
-598    0x090A    //TX_FDEQ_BIN_7
-599    0x0B0C    //TX_FDEQ_BIN_8
-600    0x0D0E    //TX_FDEQ_BIN_9
-601    0x0000    //TX_FDEQ_BIN_10
-602    0x0000    //TX_FDEQ_BIN_11
-603    0x0000    //TX_FDEQ_BIN_12
-604    0x0000    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0010    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0608    //TX_PREEQ_BIN_MIC0_0
-642    0x0808    //TX_PREEQ_BIN_MIC0_1
-643    0x0808    //TX_PREEQ_BIN_MIC0_2
-644    0x0808    //TX_PREEQ_BIN_MIC0_3
-645    0x0808    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x0808    //TX_PREEQ_BIN_MIC0_6
-648    0x0802    //TX_PREEQ_BIN_MIC0_7
-649    0x0000    //TX_PREEQ_BIN_MIC0_8
-650    0x0000    //TX_PREEQ_BIN_MIC0_9
-651    0x0000    //TX_PREEQ_BIN_MIC0_10
-652    0x0000    //TX_PREEQ_BIN_MIC0_11
-653    0x0000    //TX_PREEQ_BIN_MIC0_12
-654    0x0000    //TX_PREEQ_BIN_MIC0_13
-655    0x0000    //TX_PREEQ_BIN_MIC0_14
-656    0x0000    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0010    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0608    //TX_PREEQ_BIN_MIC1_0
-691    0x0808    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x0808    //TX_PREEQ_BIN_MIC1_3
-694    0x0808    //TX_PREEQ_BIN_MIC1_4
-695    0x0808    //TX_PREEQ_BIN_MIC1_5
-696    0x0808    //TX_PREEQ_BIN_MIC1_6
-697    0x0802    //TX_PREEQ_BIN_MIC1_7
-698    0x0000    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0010    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0802    //TX_PREEQ_BIN_MIC2_7
-747    0x0000    //TX_PREEQ_BIN_MIC2_8
-748    0x0000    //TX_PREEQ_BIN_MIC2_9
-749    0x0000    //TX_PREEQ_BIN_MIC2_10
-750    0x0000    //TX_PREEQ_BIN_MIC2_11
-751    0x0000    //TX_PREEQ_BIN_MIC2_12
-752    0x0000    //TX_PREEQ_BIN_MIC2_13
-753    0x0000    //TX_PREEQ_BIN_MIC2_14
-754    0x0000    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
-769    0x0044    //TX_MIC_PWR_BIAS_0
-770    0x0044    //TX_MIC_PWR_BIAS_1
-771    0x0044    //TX_MIC_PWR_BIAS_2
-772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x000B    //TX_GAIN_LIMIT_0
-774    0x000B    //TX_GAIN_LIMIT_1
-775    0x000B    //TX_GAIN_LIMIT_2
-776    0x000B    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x1000    //TX_TDDRC_ALPHA_UP_01
-784    0x1000    //TX_TDDRC_ALPHA_UP_02
-785    0x1000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0000    //TX_DEADMIC_SILENCE_TH
-817    0x0000    //TX_MIC_DEGRADE_TH
-818    0x0000    //TX_DEADMIC_CNT
-819    0x0000    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0000    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0001    //TX_FILTINDX
-854    0x0000    //TX_TDDRC_THRD_0
-855    0x0000    //TX_TDDRC_THRD_1
-856    0x2000    //TX_TDDRC_THRD_2
-857    0x2000    //TX_TDDRC_THRD_3
-858    0x3000    //TX_TDDRC_SLANT_0
-859    0x6E00    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0xF800    //TX_TFMASKLTH_DOA
-875    0x0CCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x002C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
-12    0x0000    //RX_B_PE
-13    0x3800    //RX_THR_PITCH_DET_0
-14    0x3000    //RX_THR_PITCH_DET_1
-15    0x2800    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7CCD    //RX_LAMBDA_PFILT
-25    0x000A    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
-#VOL    0
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    1
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0013    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    2
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0036    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    5
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-#VOL    6
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0200    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0009    //TX_OPERATION_MODE_0
-1    0x0008    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2B68    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0001    //TX_NUM_MIC
-6    0x0001    //TX_SAMPLINGFREQ_SIG
-7    0x0001    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x009B    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0B80    //TX_PGA_0
-28    0x0800    //TX_PGA_1
-29    0x0800    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0001    //TX_MIC_DATA_SRC1
-43    0x0002    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3E00    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0800    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7D83    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x6800    //TX_THR_PITCH_DET_0
-131    0x6000    //TX_THR_PITCH_DET_1
-132    0x5800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x001E    //TX_TAIL_LENGTH
-147    0x0080    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7000    //TX_EAD_THR
-151    0x0800    //TX_THR_RE_EST
-152    0x0800    //TX_MIN_EQ_RE_EST_0
-153    0x0800    //TX_MIN_EQ_RE_EST_1
-154    0x0800    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x0800    //TX_MIN_EQ_RE_EST_4
-157    0x0800    //TX_MIN_EQ_RE_EST_5
-158    0x0800    //TX_MIN_EQ_RE_EST_6
-159    0x0800    //TX_MIN_EQ_RE_EST_7
-160    0x0800    //TX_MIN_EQ_RE_EST_8
-161    0x0800    //TX_MIN_EQ_RE_EST_9
-162    0x0800    //TX_MIN_EQ_RE_EST_10
-163    0x0800    //TX_MIN_EQ_RE_EST_11
-164    0x0800    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
-166    0x2000    //TX_LAMBDA_CB_NLE
-167    0x6000    //TX_C_POST_FLT
-168    0x7000    //TX_GAIN_NP
-169    0x00C8    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7800    //TX_DTD_THR1_0
-198    0x7000    //TX_DTD_THR1_1
-199    0x7FFF    //TX_DTD_THR1_2
-200    0x7FFF    //TX_DTD_THR1_3
-201    0x7FFF    //TX_DTD_THR1_4
-202    0x7FFF    //TX_DTD_THR1_5
-203    0x7FFF    //TX_DTD_THR1_6
-204    0x7FFF    //TX_DTD_THR2_0
-205    0x7FFF    //TX_DTD_THR2_1
-206    0x7FFF    //TX_DTD_THR2_2
-207    0x7FFF    //TX_DTD_THR2_3
-208    0x7FFF    //TX_DTD_THR2_4
-209    0x7FFF    //TX_DTD_THR2_5
-210    0x7FFF    //TX_DTD_THR2_6
-211    0x1000    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x0BB8    //TX_DT_CUT_K
-214    0x0CCD    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x0019    //TX_EPD_OFFSET_00
-233    0x0019    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x7FFF    //TX_DTD_THR1_7
-238    0x7FFF    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
-243    0xF400    //TX_THR_SN_EST_1
-244    0xF600    //TX_THR_SN_EST_2
-245    0xF400    //TX_THR_SN_EST_3
-246    0xF400    //TX_THR_SN_EST_4
-247    0xF400    //TX_THR_SN_EST_5
-248    0xF400    //TX_THR_SN_EST_6
-249    0xF600    //TX_THR_SN_EST_7
-250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
-252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0200    //TX_DELTA_THR_SN_EST_4
-255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x1000    //TX_B_POST_FLT_0
-280    0x1000    //TX_B_POST_FLT_1
-281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
-284    0x000F    //TX_NS_LVL_CTRL_3
-285    0x000F    //TX_NS_LVL_CTRL_4
-286    0x000F    //TX_NS_LVL_CTRL_5
-287    0x000F    //TX_NS_LVL_CTRL_6
-288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000C    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x7FFF    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7FFF    //TX_SNRI_SUP_0
-301    0x7FFF    //TX_SNRI_SUP_1
-302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
-304    0x7FFF    //TX_SNRI_SUP_4
-305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x000E    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
-316    0x5000    //TX_A_POST_FILT_S_2
-317    0x5000    //TX_A_POST_FILT_S_3
-318    0x5000    //TX_A_POST_FILT_S_4
-319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x5000    //TX_A_POST_FILT_S_7
-322    0x1000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
-324    0x1000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x1000    //TX_B_POST_FILT_4
-327    0x1000    //TX_B_POST_FILT_5
-328    0x1000    //TX_B_POST_FILT_6
-329    0x1000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7CCD    //TX_LAMBDA_PFILT
-339    0x7B00    //TX_LAMBDA_PFILT_S_0
-340    0x7B00    //TX_LAMBDA_PFILT_S_1
-341    0x7B00    //TX_LAMBDA_PFILT_S_2
-342    0x7B00    //TX_LAMBDA_PFILT_S_3
-343    0x7B00    //TX_LAMBDA_PFILT_S_4
-344    0x7B00    //TX_LAMBDA_PFILT_S_5
-345    0x7B00    //TX_LAMBDA_PFILT_S_6
-346    0x7B00    //TX_LAMBDA_PFILT_S_7
+339    0x7CCD    //TX_LAMBDA_PFILT_S_0
+340    0x7CCD    //TX_LAMBDA_PFILT_S_1
+341    0x7CCD    //TX_LAMBDA_PFILT_S_2
+342    0x7CCD    //TX_LAMBDA_PFILT_S_3
+343    0x7CCD    //TX_LAMBDA_PFILT_S_4
+344    0x7CCD    //TX_LAMBDA_PFILT_S_5
+345    0x7CCD    //TX_LAMBDA_PFILT_S_6
+346    0x7CCD    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
-348    0x0800    //TX_A_PEPPER
-349    0x1EAA    //TX_K_PEPPER_HF
-350    0x0800    //TX_A_PEPPER_HF
+348    0x0500    //TX_A_PEPPER
+349    0x1600    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0800    //TX_DT_BINVAD_TH_0
@@ -16151,23 +21735,23 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x04E8    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
-371    0x00C8    //TX_NOISE_TH_2
-372    0x3A98    //TX_NOISE_TH_3
-373    0x0FA0    //TX_NOISE_TH_4
-374    0x157C    //TX_NOISE_TH_5
-375    0x7FFF    //TX_NOISE_TH_5_2
-376    0x7FFF    //TX_NOISE_TH_5_3
-377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+370    0x02A6    //TX_NOISE_TH_1
+371    0x04B0    //TX_NOISE_TH_2
+372    0x3194    //TX_NOISE_TH_3
+373    0x0960    //TX_NOISE_TH_4
+374    0x5555    //TX_NOISE_TH_5
+375    0x3FF4    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x02BC    //TX_NOISE_TH_6
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -16175,28 +21759,28 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0002    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x7FFF    //TX_MIN_G_CTRL_SSNS
-409    0x0000    //TX_METAL_RTO_THR
-410    0x0000    //TX_NS_FP_K_METAL
-411    0x7FFF    //TX_NOISEDET_BOOST_TH
-412    0x0000    //TX_NSMOOTH_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
 413    0x0000    //TX_NS_RESRV_8
 414    0x1800    //TX_RHO_UPB
 415    0x0BB8    //TX_N_HOLD_HS
@@ -16281,8 +21865,8 @@
 494    0x0000    //TX_DFLT_SRC_LOC_2
 495    0x038E    //TX_DOA_TRACK_VADTH
 496    0x0000    //TX_DOA_TRACK_NEW
-497    0x0230    //TX_NOR_OFF_THR
-498    0x0CCD    //TX_MORE_ON_700HZ_THR
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
 499    0x2000    //TX_MU_BF_ADPT_NS
 500    0x0000    //TX_ADAPT_LEN
 501    0x6666    //TX_MORE_SNS
@@ -16298,16 +21882,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -16336,22 +21920,22 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x001C    //TX_FDEQ_SUBNUM
-567    0x5850    //TX_FDEQ_GAIN_0
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
 568    0x4848    //TX_FDEQ_GAIN_1
 569    0x4848    //TX_FDEQ_GAIN_2
 570    0x4848    //TX_FDEQ_GAIN_3
@@ -16376,21 +21960,21 @@
 589    0x4848    //TX_FDEQ_GAIN_22
 590    0x4848    //TX_FDEQ_GAIN_23
 591    0x0202    //TX_FDEQ_BIN_0
-592    0x0302    //TX_FDEQ_BIN_1
-593    0x0303    //TX_FDEQ_BIN_2
-594    0x0304    //TX_FDEQ_BIN_3
-595    0x0405    //TX_FDEQ_BIN_4
-596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
-598    0x090A    //TX_FDEQ_BIN_7
-599    0x0B0C    //TX_FDEQ_BIN_8
-600    0x0D07    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x1011    //TX_FDEQ_BIN_12
-604    0x1119    //TX_FDEQ_BIN_13
-605    0x0000    //TX_FDEQ_BIN_14
-606    0x0000    //TX_FDEQ_BIN_15
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
 608    0x0000    //TX_FDEQ_BIN_17
 609    0x0000    //TX_FDEQ_BIN_18
@@ -16425,21 +22009,21 @@
 638    0x4848    //TX_PREEQ_GAIN_MIC0_21
 639    0x4848    //TX_PREEQ_GAIN_MIC0_22
 640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0608    //TX_PREEQ_BIN_MIC0_0
-642    0x0808    //TX_PREEQ_BIN_MIC0_1
-643    0x0808    //TX_PREEQ_BIN_MIC0_2
-644    0x0808    //TX_PREEQ_BIN_MIC0_3
-645    0x0808    //TX_PREEQ_BIN_MIC0_4
-646    0x0808    //TX_PREEQ_BIN_MIC0_5
-647    0x0808    //TX_PREEQ_BIN_MIC0_6
-648    0x0808    //TX_PREEQ_BIN_MIC0_7
-649    0x0808    //TX_PREEQ_BIN_MIC0_8
-650    0x0808    //TX_PREEQ_BIN_MIC0_9
-651    0x0808    //TX_PREEQ_BIN_MIC0_10
-652    0x0808    //TX_PREEQ_BIN_MIC0_11
-653    0x0808    //TX_PREEQ_BIN_MIC0_12
-654    0x0808    //TX_PREEQ_BIN_MIC0_13
-655    0x0808    //TX_PREEQ_BIN_MIC0_14
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
 656    0x0200    //TX_PREEQ_BIN_MIC0_15
 657    0x0000    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
@@ -16474,21 +22058,21 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0608    //TX_PREEQ_BIN_MIC1_0
-691    0x0808    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x0808    //TX_PREEQ_BIN_MIC1_3
-694    0x0808    //TX_PREEQ_BIN_MIC1_4
-695    0x0808    //TX_PREEQ_BIN_MIC1_5
-696    0x0808    //TX_PREEQ_BIN_MIC1_6
-697    0x0808    //TX_PREEQ_BIN_MIC1_7
-698    0x0808    //TX_PREEQ_BIN_MIC1_8
-699    0x0808    //TX_PREEQ_BIN_MIC1_9
-700    0x0808    //TX_PREEQ_BIN_MIC1_10
-701    0x0808    //TX_PREEQ_BIN_MIC1_11
-702    0x0808    //TX_PREEQ_BIN_MIC1_12
-703    0x0808    //TX_PREEQ_BIN_MIC1_13
-704    0x0808    //TX_PREEQ_BIN_MIC1_14
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
 705    0x0200    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
@@ -16523,21 +22107,21 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
-745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
 754    0x0200    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
@@ -16548,29 +22132,29 @@
 761    0x0000    //TX_PREEQ_BIN_MIC2_22
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
-764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
-769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0046    //TX_MIC_PWR_BIAS_1
-771    0x0046    //TX_MIC_PWR_BIAS_2
-772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x000C    //TX_GAIN_LIMIT_0
-774    0x000C    //TX_GAIN_LIMIT_1
-775    0x000C    //TX_GAIN_LIMIT_2
-776    0x000C    //TX_GAIN_LIMIT_3
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x1000    //TX_TDDRC_ALPHA_UP_01
-784    0x1000    //TX_TDDRC_ALPHA_UP_02
-785    0x1000    //TX_TDDRC_ALPHA_UP_03
-786    0x1000    //TX_TDDRC_ALPHA_UP_04
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
 787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
 788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
 789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
@@ -16617,7 +22201,7 @@
 830    0x2000    //TX_TPKA_FP
 831    0x0080    //TX_MIN_G_FP
 832    0x2000    //TX_MAX_G_FP
-833    0x0000    //TX_FFP_FP_K_METAL
+833    0x4848    //TX_FFP_FP_K_METAL
 834    0x4000    //TX_A_POST_FLT_FP
 835    0x0F5C    //TX_RTO_OUTBEAM_TH
 836    0x4CCD    //TX_TPKA_FP_THD
@@ -16637,20 +22221,20 @@
 850    0x0000    //TX_FFP_RESRV_4
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
-853    0x0001    //TX_FILTINDX
-854    0x0000    //TX_TDDRC_THRD_0
-855    0x0000    //TX_TDDRC_THRD_1
-856    0x2000    //TX_TDDRC_THRD_2
-857    0x2000    //TX_TDDRC_THRD_3
+853    0x0002    //TX_FILTINDX
+854    0x0001    //TX_TDDRC_THRD_0
+855    0x0001    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
 858    0x3000    //TX_TDDRC_SLANT_0
-859    0x6E00    //TX_TDDRC_SLANT_1
-860    0x1000    //TX_TDDRC_ALPHA_UP_00
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
 861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x05A0    //TX_TDDRC_DRC_GAIN
+866    0x07F2    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -16672,41 +22256,106 @@
 885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x00C8    //TX_FASTNS_ARSPC_TH
+888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x7000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0001    //RX_SAMPLINGFREQ_SIG
-3    0x0001    //RX_SAMPLINGFREQ_PROC
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
-11    0x7FFF    //RX_A_HP
+11    0x7B02    //RX_A_HP
 12    0x4000    //RX_B_PE
-13    0x3800    //RX_THR_PITCH_DET_0
-14    0x3000    //RX_THR_PITCH_DET_1
-15    0x2800    //RX_THR_PITCH_DET_2
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
 16    0x0008    //RX_PITCH_BFR_LEN
 17    0x0003    //RX_SBD_PITCH_DET
 18    0x0100    //RX_PP_RESRV_0
 19    0x0020    //RX_PP_RESRV_1
-20    0x0600    //RX_N_SN_EST
+20    0x0500    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
-23    0xF800    //RX_THR_SN_EST
-24    0x7CCD    //RX_LAMBDA_PFILT
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF600    //RX_THR_SN_EST
+24    0x7000    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
@@ -16720,7 +22369,7 @@
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
-38    0x001C    //RX_FDEQ_SUBNUM
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -16747,20 +22396,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -16796,17 +22445,17 @@
 111    0x0002    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
+124    0x0240    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
 126    0x2000    //RX_TPKA_FP
 127    0x2000    //RX_MIN_G_FP
@@ -16840,10 +22489,10 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -16852,18 +22501,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -16890,20 +22539,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -16939,10 +22588,10 @@
 129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -16951,18 +22600,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -16989,20 +22638,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17038,10 +22687,10 @@
 129    0x0013    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -17050,18 +22699,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -17088,20 +22737,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17137,10 +22786,10 @@
 129    0x0020    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -17149,18 +22798,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -17187,20 +22836,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17236,10 +22885,10 @@
 129    0x0036    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -17248,18 +22897,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -17286,20 +22935,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17335,10 +22984,10 @@
 129    0x005B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -17347,18 +22996,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -17385,20 +23034,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17434,10 +23083,10 @@
 129    0x0099    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
 29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
@@ -17446,18 +23095,18 @@
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
 113    0x0000    //RX_TDDRC_THRD_1
-114    0x2000    //RX_TDDRC_THRD_2
-115    0x3000    //RX_TDDRC_THRD_3
-116    0x0800    //RX_TDDRC_SLANT_0
-117    0x7EB8    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0196    //RX_TDDRC_DRC_GAIN
-38    0x001C    //RX_FDEQ_SUBNUM
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
@@ -17484,20 +23133,20 @@
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
 64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -17532,10 +23181,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x202C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
-#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#CASE_NAME  HEADSET-GOOGLE_CONDOR-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -17779,7 +24280,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF600    //TX_THR_SN_EST_2
 245    0xF400    //TX_THR_SN_EST_3
@@ -17788,20 +24289,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -17819,16 +24320,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -17852,12 +24353,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -17904,7 +24405,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0383    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
@@ -17916,11 +24417,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -17928,22 +24429,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x2900    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -18051,16 +24552,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -18089,19 +24590,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -18426,14 +24927,79 @@
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
 888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x002C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -19285,1769 +25851,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0009    //TX_OPERATION_MODE_0
-1    0x0009    //TX_OPERATION_MODE_1
-2    0x0020    //TX_PATCH_REG
-3    0x6B6A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0001    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x009B    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0B4C    //TX_PGA_0
-28    0x0800    //TX_PGA_1
-29    0x0000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0001    //TX_MIC_DATA_SRC1
-43    0x0002    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3E00    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0800    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x6800    //TX_THR_PITCH_DET_0
-131    0x6000    //TX_THR_PITCH_DET_1
-132    0x5800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x001E    //TX_TAIL_LENGTH
-147    0x0200    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x61A8    //TX_EAD_THR
-151    0x0400    //TX_THR_RE_EST
-152    0x3000    //TX_MIN_EQ_RE_EST_0
-153    0x3000    //TX_MIN_EQ_RE_EST_1
-154    0x4000    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x0800    //TX_MIN_EQ_RE_EST_4
-157    0x0800    //TX_MIN_EQ_RE_EST_5
-158    0x6000    //TX_MIN_EQ_RE_EST_6
-159    0x6000    //TX_MIN_EQ_RE_EST_7
-160    0x6000    //TX_MIN_EQ_RE_EST_8
-161    0x6000    //TX_MIN_EQ_RE_EST_9
-162    0x4000    //TX_MIN_EQ_RE_EST_10
-163    0x4000    //TX_MIN_EQ_RE_EST_11
-164    0x4000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x4000    //TX_LAMBDA_CB_NLE
-167    0x3000    //TX_C_POST_FLT
-168    0x7FFF    //TX_GAIN_NP
-169    0x00C8    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x0800    //TX_DTD_THR1_0
-198    0x0800    //TX_DTD_THR1_1
-199    0x0800    //TX_DTD_THR1_2
-200    0x0800    //TX_DTD_THR1_3
-201    0x0800    //TX_DTD_THR1_4
-202    0x0800    //TX_DTD_THR1_5
-203    0x0800    //TX_DTD_THR1_6
-204    0x0800    //TX_DTD_THR2_0
-205    0x0800    //TX_DTD_THR2_1
-206    0x0800    //TX_DTD_THR2_2
-207    0x0800    //TX_DTD_THR2_3
-208    0x0800    //TX_DTD_THR2_4
-209    0x0100    //TX_DTD_THR2_5
-210    0x0100    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x03E8    //TX_DT_CUT_K
-214    0x0CCD    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x00C0    //TX_EPD_OFFSET_00
-233    0x00C0    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x7FFF    //TX_DTD_THR1_7
-238    0x7FFF    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF700    //TX_THR_SN_EST_0
-243    0xFB00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF700    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF600    //TX_THR_SN_EST_5
-248    0xF600    //TX_THR_SN_EST_6
-249    0xF600    //TX_THR_SN_EST_7
-250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
-255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x2000    //TX_B_POST_FLT_0
-280    0x2000    //TX_B_POST_FLT_1
-281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
-283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
-296    0x000C    //TX_MIN_GAIN_S_7
-297    0x7FFF    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0016    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x6000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x6000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x6000    //TX_A_POST_FILT_S_6
-321    0x6000    //TX_A_POST_FILT_S_7
-322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x2000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7CCD    //TX_LAMBDA_PFILT
-339    0x7CCD    //TX_LAMBDA_PFILT_S_0
-340    0x7CCD    //TX_LAMBDA_PFILT_S_1
-341    0x7CCD    //TX_LAMBDA_PFILT_S_2
-342    0x7CCD    //TX_LAMBDA_PFILT_S_3
-343    0x7CCD    //TX_LAMBDA_PFILT_S_4
-344    0x7CCD    //TX_LAMBDA_PFILT_S_5
-345    0x7CCD    //TX_LAMBDA_PFILT_S_6
-346    0x7CCD    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0500    //TX_A_PEPPER
-349    0x1600    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0000    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0020    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x02A6    //TX_NOISE_TH_1
-371    0x04B0    //TX_NOISE_TH_2
-372    0x3194    //TX_NOISE_TH_3
-373    0x0960    //TX_NOISE_TH_4
-374    0x5555    //TX_NOISE_TH_5
-375    0x3FF4    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x02BC    //TX_NOISE_TH_6
-379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0020    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4848    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4848    //TX_FDEQ_GAIN_9
-577    0x4848    //TX_FDEQ_GAIN_10
-578    0x4848    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0203    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0405    //TX_FDEQ_BIN_3
-595    0x0607    //TX_FDEQ_BIN_4
-596    0x0809    //TX_FDEQ_BIN_5
-597    0x0A0B    //TX_FDEQ_BIN_6
-598    0x0C0D    //TX_FDEQ_BIN_7
-599    0x0E0F    //TX_FDEQ_BIN_8
-600    0x1011    //TX_FDEQ_BIN_9
-601    0x1214    //TX_FDEQ_BIN_10
-602    0x1618    //TX_FDEQ_BIN_11
-603    0x1C1C    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x2011    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0E10    //TX_PREEQ_BIN_MIC0_0
-642    0x1010    //TX_PREEQ_BIN_MIC0_1
-643    0x1010    //TX_PREEQ_BIN_MIC0_2
-644    0x1010    //TX_PREEQ_BIN_MIC0_3
-645    0x1010    //TX_PREEQ_BIN_MIC0_4
-646    0x1010    //TX_PREEQ_BIN_MIC0_5
-647    0x1010    //TX_PREEQ_BIN_MIC0_6
-648    0x1010    //TX_PREEQ_BIN_MIC0_7
-649    0x1010    //TX_PREEQ_BIN_MIC0_8
-650    0x1010    //TX_PREEQ_BIN_MIC0_9
-651    0x1010    //TX_PREEQ_BIN_MIC0_10
-652    0x1010    //TX_PREEQ_BIN_MIC0_11
-653    0x1010    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
-655    0x1010    //TX_PREEQ_BIN_MIC0_14
-656    0x0200    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0E10    //TX_PREEQ_BIN_MIC1_0
-691    0x1010    //TX_PREEQ_BIN_MIC1_1
-692    0x1010    //TX_PREEQ_BIN_MIC1_2
-693    0x1010    //TX_PREEQ_BIN_MIC1_3
-694    0x1010    //TX_PREEQ_BIN_MIC1_4
-695    0x1010    //TX_PREEQ_BIN_MIC1_5
-696    0x1010    //TX_PREEQ_BIN_MIC1_6
-697    0x1010    //TX_PREEQ_BIN_MIC1_7
-698    0x1010    //TX_PREEQ_BIN_MIC1_8
-699    0x1010    //TX_PREEQ_BIN_MIC1_9
-700    0x1010    //TX_PREEQ_BIN_MIC1_10
-701    0x1010    //TX_PREEQ_BIN_MIC1_11
-702    0x1010    //TX_PREEQ_BIN_MIC1_12
-703    0x1010    //TX_PREEQ_BIN_MIC1_13
-704    0x1010    //TX_PREEQ_BIN_MIC1_14
-705    0x0200    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0C00    //TX_TDDRC_ALPHA_UP_01
-784    0x0C00    //TX_TDDRC_ALPHA_UP_02
-785    0x0C00    //TX_TDDRC_ALPHA_UP_03
-786    0x0C00    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0000    //TX_DEADMIC_SILENCE_TH
-817    0x0000    //TX_MIC_DEGRADE_TH
-818    0x0000    //TX_DEADMIC_CNT
-819    0x0000    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0000    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0001    //TX_TDDRC_THRD_1
-856    0x1900    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x3000    //TX_TDDRC_SLANT_0
-859    0x7B00    //TX_TDDRC_SLANT_1
-860    0x0C00    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x07F2    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x002C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7B02    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0500    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000A    //RX_NS_LVL_CTRL
-23    0xF600    //RX_THR_SN_EST
-24    0x7000    //RX_LAMBDA_PFILT
-25    0x000A    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0013    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0036    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0000    //TX_SAMPLINGFREQ_SIG
 7    0x0000    //TX_SAMPLINGFREQ_PROC
@@ -21064,8 +26729,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -21193,7 +26858,7 @@
 147    0x0100    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7500    //TX_EAD_THR
+150    0x7E00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
 153    0x0200    //TX_MIN_EQ_RE_EST_1
@@ -21208,13 +26873,13 @@
 162    0x4000    //TX_MIN_EQ_RE_EST_10
 163    0x6000    //TX_MIN_EQ_RE_EST_11
 164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x2000    //TX_LAMBDA_RE_EST
+165    0x4000    //TX_LAMBDA_RE_EST
 166    0x0000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x2000    //TX_GAIN_NP
 169    0x0180    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0080    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -21240,10 +26905,10 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
+197    0x7FF0    //TX_DTD_THR1_0
+198    0x79E0    //TX_DTD_THR1_1
+199    0x6D60    //TX_DTD_THR1_2
+200    0x73A0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
@@ -21256,7 +26921,7 @@
 210    0x0CCD    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x157C    //TX_DT_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
 214    0x0100    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
@@ -21266,18 +26931,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x1000    //TX_ADPT_STRICT_L
 222    0x1000    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
 224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+225    0x028A    //TX_RATIO_DT_L_TH_HIGH
 226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x1000    //TX_B_POST_FILT_ECHO_L
 229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+234    0x01F4    //TX_RATIO_DT_L0_TH_HIGH
 235    0x3A98    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -21294,12 +26959,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0050    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -21325,31 +26990,31 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0012    //TX_NS_LVL_CTRL_1
-283    0x0017    //TX_NS_LVL_CTRL_2
-284    0x0015    //TX_NS_LVL_CTRL_3
+282    0x0017    //TX_NS_LVL_CTRL_1
+283    0x001A    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
 285    0x0012    //TX_NS_LVL_CTRL_4
-286    0x0012    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0012    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
-290    0x000F    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000F    //TX_MIN_GAIN_S_2
 292    0x000F    //TX_MIN_GAIN_S_3
 293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000F    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x000F    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
-297    0x4000    //TX_NMOS_SUP
+297    0x3C00    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x1000    //TX_SNRI_SUP_2
+301    0x1000    //TX_SNRI_SUP_1
+302    0x3000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
-304    0x2400    //TX_SNRI_SUP_4
+304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x3000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -21358,19 +27023,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x2000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x1000    //TX_A_POST_FILT_S_4
-319    0x3000    //TX_A_POST_FILT_S_5
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x1000    //TX_A_POST_FILT_S_2
+317    0x1000    //TX_A_POST_FILT_S_3
+318    0x3000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
 320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
 324    0x1000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x3000    //TX_B_POST_FILT_5
+325    0x3000    //TX_B_POST_FILT_3
+326    0x3000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -21383,12 +27048,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7E00    //TX_LAMBDA_PFILT
 339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7900    //TX_LAMBDA_PFILT_S_1
-341    0x7400    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7000    //TX_LAMBDA_PFILT_S_4
+340    0x7400    //TX_LAMBDA_PFILT_S_1
+341    0x7D00    //TX_LAMBDA_PFILT_S_2
+342    0x7000    //TX_LAMBDA_PFILT_S_3
+343    0x7D00    //TX_LAMBDA_PFILT_S_4
 344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
+345    0x7900    //TX_LAMBDA_PFILT_S_6
 346    0x7D00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0800    //TX_A_PEPPER
@@ -21400,7 +27065,7 @@
 354    0x0800    //TX_DT_BINVAD_TH_1
 355    0x0800    //TX_DT_BINVAD_TH_2
 356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0FA0    //TX_DT_BINVAD_ENDF
+357    0x0BB8    //TX_DT_BINVAD_ENDF
 358    0x0400    //TX_C_POST_FLT_DT
 359    0x4000    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0100    //TX_DT_BOOST
@@ -21410,23 +27075,23 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0019    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
+370    0x1388    //TX_NOISE_TH_1
 371    0x03ED    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5528    //TX_NOISE_TH_4
+372    0x59D8    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
 374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x0FA0    //TX_NOISE_TH_6
+378    0x4650    //TX_NOISE_TH_6
 379    0x000A    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -21434,17 +27099,17 @@
 388    0x1000    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7000    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -21552,21 +27217,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -21595,31 +27260,31 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
-567    0x5858    //TX_FDEQ_GAIN_0
-568    0x5850    //TX_FDEQ_GAIN_1
-569    0x5050    //TX_FDEQ_GAIN_2
-570    0x5048    //TX_FDEQ_GAIN_3
-571    0x3C48    //TX_FDEQ_GAIN_4
-572    0x3C48    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4842    //TX_FDEQ_GAIN_7
-575    0x3030    //TX_FDEQ_GAIN_8
-576    0x3030    //TX_FDEQ_GAIN_9
+567    0x5854    //TX_FDEQ_GAIN_0
+568    0x4C48    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4A43    //TX_FDEQ_GAIN_3
+571    0x374B    //TX_FDEQ_GAIN_4
+572    0x3444    //TX_FDEQ_GAIN_5
+573    0x433C    //TX_FDEQ_GAIN_6
+574    0x3436    //TX_FDEQ_GAIN_7
+575    0x2C2E    //TX_FDEQ_GAIN_8
+576    0x3234    //TX_FDEQ_GAIN_9
 577    0x4848    //TX_FDEQ_GAIN_10
 578    0x4848    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
@@ -21640,10 +27305,10 @@
 594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
+597    0x0906    //TX_FDEQ_BIN_6
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
-600    0x0D08    //TX_FDEQ_BIN_9
+600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x0000    //TX_FDEQ_BIN_10
 602    0x0000    //TX_FDEQ_BIN_11
 603    0x0000    //TX_FDEQ_BIN_12
@@ -21667,9 +27332,9 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4B4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
 627    0x4848    //TX_PREEQ_GAIN_MIC0_10
 628    0x4848    //TX_PREEQ_GAIN_MIC0_11
 629    0x4848    //TX_PREEQ_GAIN_MIC0_12
@@ -21693,7 +27358,7 @@
 647    0x0708    //TX_PREEQ_BIN_MIC0_6
 648    0x090A    //TX_PREEQ_BIN_MIC0_7
 649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D08    //TX_PREEQ_BIN_MIC0_9
+650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0000    //TX_PREEQ_BIN_MIC0_10
 652    0x0000    //TX_PREEQ_BIN_MIC0_11
 653    0x0000    //TX_PREEQ_BIN_MIC0_12
@@ -21716,9 +27381,9 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+673    0x4A4A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4B4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4D4E    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
 678    0x4848    //TX_PREEQ_GAIN_MIC1_12
@@ -21733,16 +27398,16 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C08    //TX_PREEQ_BIN_MIC1_2
-693    0x0700    //TX_PREEQ_BIN_MIC1_3
-694    0x0000    //TX_PREEQ_BIN_MIC1_4
-695    0x0000    //TX_PREEQ_BIN_MIC1_5
-696    0x0000    //TX_PREEQ_BIN_MIC1_6
-697    0x0000    //TX_PREEQ_BIN_MIC1_7
-698    0x0000    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
 700    0x0000    //TX_PREEQ_BIN_MIC1_10
 701    0x0000    //TX_PREEQ_BIN_MIC1_11
 702    0x0000    //TX_PREEQ_BIN_MIC1_12
@@ -21764,10 +27429,10 @@
 718    0x4848    //TX_PREEQ_GAIN_MIC2_3
 719    0x4848    //TX_PREEQ_GAIN_MIC2_4
 720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+721    0x484A    //TX_PREEQ_GAIN_MIC2_6
+722    0x4B4B    //TX_PREEQ_GAIN_MIC2_7
+723    0x4B4C    //TX_PREEQ_GAIN_MIC2_8
+724    0x4D50    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
 727    0x4848    //TX_PREEQ_GAIN_MIC2_12
@@ -21782,16 +27447,16 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x7800    //TX_PREEQ_BIN_MIC2_0
-740    0x0000    //TX_PREEQ_BIN_MIC2_1
-741    0x0000    //TX_PREEQ_BIN_MIC2_2
-742    0x0000    //TX_PREEQ_BIN_MIC2_3
-743    0x0000    //TX_PREEQ_BIN_MIC2_4
-744    0x0000    //TX_PREEQ_BIN_MIC2_5
-745    0x0000    //TX_PREEQ_BIN_MIC2_6
-746    0x0000    //TX_PREEQ_BIN_MIC2_7
-747    0x0000    //TX_PREEQ_BIN_MIC2_8
-748    0x0000    //TX_PREEQ_BIN_MIC2_9
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0708    //TX_PREEQ_BIN_MIC2_6
+746    0x090A    //TX_PREEQ_BIN_MIC2_7
+747    0x0B0C    //TX_PREEQ_BIN_MIC2_8
+748    0x0D0E    //TX_PREEQ_BIN_MIC2_9
 749    0x0000    //TX_PREEQ_BIN_MIC2_10
 750    0x0000    //TX_PREEQ_BIN_MIC2_11
 751    0x0000    //TX_PREEQ_BIN_MIC2_12
@@ -21808,16 +27473,16 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0044    //TX_MIC_PWR_BIAS_0
 770    0x0044    //TX_MIC_PWR_BIAS_1
 771    0x0044    //TX_MIC_PWR_BIAS_2
 772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
 776    0x000F    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
@@ -21826,15 +27491,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x4000    //TX_TDDRC_ALPHA_UP_02
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
 785    0x4000    //TX_TDDRC_ALPHA_UP_03
-786    0x4000    //TX_TDDRC_ALPHA_UP_04
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x4000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -21859,8 +27524,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -21899,17 +27564,17 @@
 853    0x0002    //TX_FILTINDX
 854    0x0004    //TX_TDDRC_THRD_0
 855    0x0010    //TX_TDDRC_THRD_1
-856    0x1800    //TX_TDDRC_THRD_2
+856    0x1000    //TX_TDDRC_THRD_2
 857    0x1800    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
 861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0C60    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -21934,14 +27599,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x0217    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7918    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xCD38    //TX_AMS_RESRV_02
+945    0x2710    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA02C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -21963,7 +27693,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -22791,16 +28521,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0001    //TX_SAMPLINGFREQ_SIG
 7    0x0001    //TX_SAMPLINGFREQ_PROC
@@ -22817,8 +29399,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -22946,28 +29528,28 @@
 147    0x0300    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6800    //TX_EAD_THR
+150    0x6C00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0200    //TX_MIN_EQ_RE_EST_2
-155    0x0200    //TX_MIN_EQ_RE_EST_3
-156    0x0200    //TX_MIN_EQ_RE_EST_4
-157    0x0200    //TX_MIN_EQ_RE_EST_5
-158    0x0200    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x1000    //TX_MIN_EQ_RE_EST_8
-161    0x1000    //TX_MIN_EQ_RE_EST_9
-162    0x1000    //TX_MIN_EQ_RE_EST_10
-163    0x1000    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x2000    //TX_MIN_EQ_RE_EST_3
+156    0x2000    //TX_MIN_EQ_RE_EST_4
+157    0x2000    //TX_MIN_EQ_RE_EST_5
+158    0x4000    //TX_MIN_EQ_RE_EST_6
+159    0x4000    //TX_MIN_EQ_RE_EST_7
+160    0x4000    //TX_MIN_EQ_RE_EST_8
+161    0x4000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x4000    //TX_MIN_EQ_RE_EST_11
+164    0x4000    //TX_MIN_EQ_RE_EST_12
 165    0x4000    //TX_LAMBDA_RE_EST
 166    0x4000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x5000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+169    0x02A0    //TX_SE_HOLD_N
+170    0x0060    //TX_DT_HOLD_N
+171    0x00C0    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -22993,9 +29575,9 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
+197    0x79E0    //TX_DTD_THR1_0
+198    0x7C38    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
@@ -23009,8 +29591,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x07D0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -23019,18 +29601,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x0A98    //TX_RATIO_DT_H_TH_LOW
+225    0x0320    //TX_RATIO_DT_L_TH_HIGH
+226    0x1388    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x6000    //TX_B_POST_FILT_ECHO_L
 229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+234    0x012C    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -23047,11 +29629,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -23079,11 +29661,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -23101,8 +29683,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -23111,19 +29693,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -23131,14 +29713,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -23150,11 +29732,11 @@
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0200    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x0200    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0800    //TX_C_POST_FLT_DT
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x0BB8    //TX_DT_BINVAD_ENDF
+358    0x2000    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0140    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
@@ -23176,10 +29758,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0F0A    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -23187,17 +29769,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7FFF    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0005    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -23305,21 +29887,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -23348,35 +29930,35 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x001C    //TX_FDEQ_SUBNUM
-567    0x5050    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x5050    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4844    //TX_FDEQ_GAIN_9
-577    0x3C36    //TX_FDEQ_GAIN_10
-578    0x3A3A    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x5048    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4A4F    //TX_FDEQ_GAIN_2
+570    0x4E48    //TX_FDEQ_GAIN_3
+571    0x4444    //TX_FDEQ_GAIN_4
+572    0x4450    //TX_FDEQ_GAIN_5
+573    0x5452    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x4A4C    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4850    //TX_FDEQ_GAIN_10
+578    0x5454    //TX_FDEQ_GAIN_11
+579    0x5454    //TX_FDEQ_GAIN_12
+580    0x5454    //TX_FDEQ_GAIN_13
 581    0x4848    //TX_FDEQ_GAIN_14
 582    0x4848    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
@@ -23397,10 +29979,10 @@
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
 600    0x0D0E    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x1011    //TX_FDEQ_BIN_12
-604    0x1104    //TX_FDEQ_BIN_13
+601    0x0F10    //TX_FDEQ_BIN_10
+602    0x1011    //TX_FDEQ_BIN_11
+603    0x1112    //TX_FDEQ_BIN_12
+604    0x120B    //TX_FDEQ_BIN_13
 605    0x0000    //TX_FDEQ_BIN_14
 606    0x0000    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
@@ -23420,13 +30002,13 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x5E64    //TX_PREEQ_GAIN_MIC0_12
-630    0x6464    //TX_PREEQ_GAIN_MIC0_13
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
 631    0x4848    //TX_PREEQ_GAIN_MIC0_14
 632    0x4848    //TX_PREEQ_GAIN_MIC0_15
 633    0x4848    //TX_PREEQ_GAIN_MIC0_16
@@ -23449,8 +30031,8 @@
 650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0F10    //TX_PREEQ_BIN_MIC0_10
 652    0x1011    //TX_PREEQ_BIN_MIC0_11
-653    0x1104    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
+653    0x1112    //TX_PREEQ_BIN_MIC0_12
+654    0x120B    //TX_PREEQ_BIN_MIC0_13
 655    0x0000    //TX_PREEQ_BIN_MIC0_14
 656    0x0000    //TX_PREEQ_BIN_MIC0_15
 657    0x0000    //TX_PREEQ_BIN_MIC0_16
@@ -23469,13 +30051,13 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+673    0x484A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4C4E    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5454    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
 680    0x4848    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
@@ -23486,20 +30068,20 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x0700    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0F10    //TX_PREEQ_BIN_MIC1_10
+701    0x1011    //TX_PREEQ_BIN_MIC1_11
+702    0x1112    //TX_PREEQ_BIN_MIC1_12
+703    0x120B    //TX_PREEQ_BIN_MIC1_13
 704    0x0000    //TX_PREEQ_BIN_MIC1_14
 705    0x0000    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
@@ -23514,19 +30096,19 @@
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+718    0x484A    //TX_PREEQ_GAIN_MIC2_3
+719    0x4B4A    //TX_PREEQ_GAIN_MIC2_4
+720    0x4B4C    //TX_PREEQ_GAIN_MIC2_5
+721    0x4C4D    //TX_PREEQ_GAIN_MIC2_6
+722    0x4F50    //TX_PREEQ_GAIN_MIC2_7
+723    0x5050    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5252    //TX_PREEQ_GAIN_MIC2_10
+726    0x5253    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x5454    //TX_PREEQ_GAIN_MIC2_13
+729    0x5455    //TX_PREEQ_GAIN_MIC2_14
+730    0x5555    //TX_PREEQ_GAIN_MIC2_15
 731    0x4848    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
@@ -23550,7 +30132,7 @@
 751    0x0808    //TX_PREEQ_BIN_MIC2_12
 752    0x0808    //TX_PREEQ_BIN_MIC2_13
 753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
+754    0x0808    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
@@ -23561,33 +30143,33 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
 770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
+776    0x0009    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0800    //TX_TDDRC_ALPHA_UP_01
-784    0x0800    //TX_TDDRC_ALPHA_UP_02
-785    0x0800    //TX_TDDRC_ALPHA_UP_03
-786    0x0800    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
 788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
 789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -23612,8 +30194,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -23650,19 +30232,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0002    //TX_TDDRC_THRD_1
-856    0x1800    //TX_TDDRC_THRD_2
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
 857    0x1800    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x0800    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0F23    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -23687,14 +30269,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0230    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7DC8    //TX_DTD_THR1_MICMUTE_0
+912    0x733C    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xD8F0    //TX_AMS_RESRV_02
+945    0x2EE0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0xA02C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -23716,7 +30363,7 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0600    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
 24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
@@ -24544,16 +31191,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
 7    0x0003    //TX_SAMPLINGFREQ_PROC
@@ -24570,8 +32069,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -24699,28 +32198,28 @@
 147    0x0400    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7600    //TX_EAD_THR
+150    0x7000    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x2000    //TX_MIN_EQ_RE_EST_0
 153    0x0600    //TX_MIN_EQ_RE_EST_1
 154    0x3000    //TX_MIN_EQ_RE_EST_2
-155    0x3000    //TX_MIN_EQ_RE_EST_3
+155    0x6000    //TX_MIN_EQ_RE_EST_3
 156    0x3000    //TX_MIN_EQ_RE_EST_4
 157    0x3000    //TX_MIN_EQ_RE_EST_5
 158    0x3000    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
+159    0x3000    //TX_MIN_EQ_RE_EST_7
 160    0x7800    //TX_MIN_EQ_RE_EST_8
 161    0x7800    //TX_MIN_EQ_RE_EST_9
 162    0x7800    //TX_MIN_EQ_RE_EST_10
 163    0x7800    //TX_MIN_EQ_RE_EST_11
 164    0x7800    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
+165    0x3000    //TX_LAMBDA_RE_EST
 166    0x3000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x4000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
+169    0x0260    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -24746,12 +32245,12 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
+197    0x7080    //TX_DTD_THR1_0
 198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
+199    0x7C38    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
+202    0x7D00    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
 204    0x7E00    //TX_DTD_THR2_0
 205    0x7E00    //TX_DTD_THR2_1
@@ -24762,8 +32261,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x36B0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -24772,18 +32271,18 @@
 220    0x7FFF    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1F40    //TX_RATIO_DT_L_TH_HIGH
-226    0x6590    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
-229    0x1000    //TX_B_POST_FILT_ECHO_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x2328    //TX_RATIO_DT_L0_TH_HIGH
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -24792,7 +32291,7 @@
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
 242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
+243    0xFB00    //TX_THR_SN_EST_1
 244    0xFA00    //TX_THR_SN_EST_2
 245    0xFA00    //TX_THR_SN_EST_3
 246    0xF800    //TX_THR_SN_EST_4
@@ -24800,12 +32299,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0120    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
 253    0x0100    //TX_DELTA_THR_SN_EST_3
-254    0x0000    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -24831,52 +32330,52 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x003C    //TX_NS_LVL_CTRL_1
-283    0x003C    //TX_NS_LVL_CTRL_2
-284    0x0024    //TX_NS_LVL_CTRL_3
-285    0x003C    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x1400    //TX_SNRI_SUP_1
-302    0x1400    //TX_SNRI_SUP_2
-303    0x1400    //TX_SNRI_SUP_3
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
 310    0x09C4    //TX_GAIN0_NTH
 311    0x000A    //TX_MUSIC_MORENS
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x7C00    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x6000    //TX_B_POST_FILT_1
 324    0x6000    //TX_B_POST_FILT_2
 325    0x6000    //TX_B_POST_FILT_3
-326    0x6000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -24884,28 +32383,28 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7D00    //TX_LAMBDA_PFILT_S_1
-341    0x7D00    //TX_LAMBDA_PFILT_S_2
-342    0x7D00    //TX_LAMBDA_PFILT_S_3
-343    0x7D00    //TX_LAMBDA_PFILT_S_4
-344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
-346    0x7D00    //TX_LAMBDA_PFILT_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
-348    0x0400    //TX_A_PEPPER
+348    0x0800    //TX_A_PEPPER
 349    0x1EAA    //TX_K_PEPPER_HF
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0040    //TX_DT_BINVAD_TH_0
-354    0x0040    //TX_DT_BINVAD_TH_1
-355    0x0100    //TX_DT_BINVAD_TH_2
-356    0x0100    //TX_DT_BINVAD_TH_3
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
 357    0x36B0    //TX_DT_BINVAD_ENDF
 358    0x0200    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
@@ -24923,16 +32422,16 @@
 371    0x01F4    //TX_NOISE_TH_2
 372    0x36B0    //TX_NOISE_TH_3
 373    0x2710    //TX_NOISE_TH_4
-374    0x2CEC    //TX_NOISE_TH_5
+374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0DAC    //TX_NOISE_TH_6
 379    0x0050    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -24940,17 +32439,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -25058,21 +32557,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -25101,37 +32600,37 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4850    //TX_FDEQ_GAIN_2
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
 570    0x5050    //TX_FDEQ_GAIN_3
 571    0x4848    //TX_FDEQ_GAIN_4
-572    0x484A    //TX_FDEQ_GAIN_5
-573    0x4E5E    //TX_FDEQ_GAIN_6
-574    0x5C4C    //TX_FDEQ_GAIN_7
-575    0x4C4E    //TX_FDEQ_GAIN_8
-576    0x4844    //TX_FDEQ_GAIN_9
-577    0x4448    //TX_FDEQ_GAIN_10
-578    0x4850    //TX_FDEQ_GAIN_11
-579    0x5C6A    //TX_FDEQ_GAIN_12
-580    0x5A84    //TX_FDEQ_GAIN_13
-581    0x7880    //TX_FDEQ_GAIN_14
-582    0x7F7F    //TX_FDEQ_GAIN_15
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
 584    0x4848    //TX_FDEQ_GAIN_17
 585    0x4848    //TX_FDEQ_GAIN_18
@@ -25146,16 +32645,16 @@
 594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
-598    0x090A    //TX_FDEQ_BIN_7
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
 600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x1013    //TX_FDEQ_BIN_10
-602    0x1719    //TX_FDEQ_BIN_11
-603    0x1B1E    //TX_FDEQ_BIN_12
-604    0x1E1E    //TX_FDEQ_BIN_13
-605    0x1E28    //TX_FDEQ_BIN_14
-606    0x282C    //TX_FDEQ_BIN_15
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
 608    0x0000    //TX_FDEQ_BIN_17
 609    0x0000    //TX_FDEQ_BIN_18
@@ -25165,7 +32664,7 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
@@ -25173,16 +32672,16 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x6474    //TX_PREEQ_GAIN_MIC0_12
-630    0x7870    //TX_PREEQ_GAIN_MIC0_13
-631    0x5C48    //TX_PREEQ_GAIN_MIC0_14
-632    0x383C    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -25196,17 +32695,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x090A    //TX_PREEQ_BIN_MIC0_7
-649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1719    //TX_PREEQ_BIN_MIC0_11
-653    0x1B1E    //TX_PREEQ_BIN_MIC0_12
-654    0x1E1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -25214,7 +32713,7 @@
 662    0x0000    //TX_PREEQ_BIN_MIC0_21
 663    0x0000    //TX_PREEQ_BIN_MIC0_22
 664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
 666    0x4848    //TX_PREEQ_GAIN_MIC1_0
 667    0x4848    //TX_PREEQ_GAIN_MIC1_1
 668    0x4848    //TX_PREEQ_GAIN_MIC1_2
@@ -25227,11 +32726,11 @@
 675    0x4848    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
 684    0x4848    //TX_PREEQ_GAIN_MIC1_18
 685    0x4848    //TX_PREEQ_GAIN_MIC1_19
@@ -25239,23 +32738,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x070F    //TX_PREEQ_BIN_MIC1_8
-699    0x1F08    //TX_PREEQ_BIN_MIC1_9
-700    0x0808    //TX_PREEQ_BIN_MIC1_10
-701    0x0920    //TX_PREEQ_BIN_MIC1_11
-702    0x2020    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -25263,7 +32762,7 @@
 711    0x0000    //TX_PREEQ_BIN_MIC1_21
 712    0x0000    //TX_PREEQ_BIN_MIC1_22
 713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
@@ -25276,11 +32775,11 @@
 724    0x4848    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
 734    0x4848    //TX_PREEQ_GAIN_MIC2_19
@@ -25288,23 +32787,23 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
 745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0xF200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
 758    0x0000    //TX_PREEQ_BIN_MIC2_19
@@ -25314,17 +32813,17 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
+770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
 774    0x000F    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
+775    0x000F    //TX_GAIN_LIMIT_2
 776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
@@ -25332,15 +32831,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0800    //TX_TDDRC_ALPHA_UP_01
-784    0x0800    //TX_TDDRC_ALPHA_UP_02
-785    0x0800    //TX_TDDRC_ALPHA_UP_03
-786    0x0800    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
 788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
 789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -25365,8 +32864,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -25403,19 +32902,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0002    //TX_TDDRC_THRD_1
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
 856    0x1000    //TX_TDDRC_THRD_2
-857    0x1000    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x0800    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0E21    //TX_TDDRC_DRC_GAIN
+866    0x12D6    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -25446,8 +32945,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
@@ -26297,10 +33861,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -26323,15 +34739,15 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
 26    0x0000    //TX_MMIC
-27    0x0FF7    //TX_PGA_0
-28    0x0FF7    //TX_PGA_1
-29    0x0FF7    //TX_PGA_2
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
 30    0x0000    //TX_PGA_3
 31    0x0000    //TX_PGA_4
 32    0x0000    //TX_PGA_5
@@ -26534,7 +34950,7 @@
 229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
+232    0x0063    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
 234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
 235    0x3A98    //TX_RATIO_DT_H_TH_CUT
@@ -26553,11 +34969,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -26585,11 +35001,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -26607,8 +35023,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -26617,19 +35033,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -26637,14 +35053,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -26682,10 +35098,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x2710    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -26693,15 +35109,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -26816,16 +35232,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -26854,19 +35270,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -26874,15 +35290,15 @@
 569    0x4848    //TX_FDEQ_GAIN_2
 570    0x4848    //TX_FDEQ_GAIN_3
 571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
+572    0x5048    //TX_FDEQ_GAIN_5
 573    0x4848    //TX_FDEQ_GAIN_6
 574    0x4848    //TX_FDEQ_GAIN_7
 575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4853    //TX_FDEQ_GAIN_9
-577    0x5450    //TX_FDEQ_GAIN_10
-578    0x7465    //TX_FDEQ_GAIN_11
-579    0x807F    //TX_FDEQ_GAIN_12
-580    0x82C4    //TX_FDEQ_GAIN_13
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
 581    0xC4C4    //TX_FDEQ_GAIN_14
 582    0xC4C4    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
@@ -26918,24 +35334,24 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
 620    0x4848    //TX_PREEQ_GAIN_MIC0_3
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4A4C    //TX_PREEQ_GAIN_MIC0_6
-624    0x4E50    //TX_PREEQ_GAIN_MIC0_7
-625    0x5456    //TX_PREEQ_GAIN_MIC0_8
-626    0x585C    //TX_PREEQ_GAIN_MIC0_9
-627    0x5C64    //TX_PREEQ_GAIN_MIC0_10
-628    0x7478    //TX_PREEQ_GAIN_MIC0_11
-629    0x705C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4838    //TX_PREEQ_GAIN_MIC0_13
-631    0x3C70    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+623    0x4849    //TX_PREEQ_GAIN_MIC0_6
+624    0x4A4B    //TX_PREEQ_GAIN_MIC0_7
+625    0x4C4B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4A48    //TX_PREEQ_GAIN_MIC0_9
+627    0x4B4C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4B    //TX_PREEQ_GAIN_MIC0_11
+629    0x4838    //TX_PREEQ_GAIN_MIC0_12
+630    0x3858    //TX_PREEQ_GAIN_MIC0_13
+631    0x7060    //TX_PREEQ_GAIN_MIC0_14
+632    0x9870    //TX_PREEQ_GAIN_MIC0_15
+633    0x5848    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -26949,17 +35365,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
 650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
 652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x1C1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x462C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -26974,15 +35390,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4645    //TX_PREEQ_GAIN_MIC1_6
+673    0x4442    //TX_PREEQ_GAIN_MIC1_7
+674    0x4140    //TX_PREEQ_GAIN_MIC1_8
+675    0x3E3D    //TX_PREEQ_GAIN_MIC1_9
+676    0x3C3C    //TX_PREEQ_GAIN_MIC1_10
+677    0x3C3C    //TX_PREEQ_GAIN_MIC1_11
+678    0x3938    //TX_PREEQ_GAIN_MIC1_12
+679    0x3A3C    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C3E    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -26992,23 +35408,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x1812    //TX_PREEQ_BIN_MIC1_0
-691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x080A    //TX_PREEQ_BIN_MIC1_3
-694    0x0B09    //TX_PREEQ_BIN_MIC1_4
-695    0x0A06    //TX_PREEQ_BIN_MIC1_5
-696    0x0606    //TX_PREEQ_BIN_MIC1_6
-697    0x0605    //TX_PREEQ_BIN_MIC1_7
-698    0x050A    //TX_PREEQ_BIN_MIC1_8
-699    0x1505    //TX_PREEQ_BIN_MIC1_9
-700    0x0506    //TX_PREEQ_BIN_MIC1_10
-701    0x0615    //TX_PREEQ_BIN_MIC1_11
-702    0x1516    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x2021    //TX_PREEQ_BIN_MIC1_14
-705    0x2021    //TX_PREEQ_BIN_MIC1_15
-706    0x0800    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x4000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -27168,7 +35584,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0A98    //TX_TDDRC_DRC_GAIN
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -27199,8 +35615,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x002C    //RX_RECVFUNC_MODE_0
+0    0x202C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0004    //RX_SAMPLINGFREQ_SIG
 3    0x0004    //RX_SAMPLINGFREQ_PROC
@@ -28050,10 +36531,3532 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x202C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-GOOGLE_CONDOR_HEADPHONE-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x002C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -28370,20 +40373,20 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
-316    0x1000    //TX_A_POST_FILT_S_2
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
 317    0x4000    //TX_A_POST_FILT_S_3
 318    0x4000    //TX_A_POST_FILT_S_4
 319    0x4000    //TX_A_POST_FILT_S_5
 320    0x4000    //TX_A_POST_FILT_S_6
 321    0x4000    //TX_A_POST_FILT_S_7
 322    0x0400    //TX_B_POST_FILT_0
-323    0x0400    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
 325    0x2000    //TX_B_POST_FILT_3
 326    0x2000    //TX_B_POST_FILT_4
 327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
+328    0x0400    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
 331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
@@ -28422,7 +40425,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x003B    //TX_NOISE_TH_0
 368    0x1B58    //TX_NOISE_TH_0_2
 369    0x2134    //TX_NOISE_TH_0_3
 370    0x02BC    //TX_NOISE_TH_1
@@ -28434,11 +40437,11 @@
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x0000    //TX_NOISE_TH_5_4
 378    0x0032    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
 385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
@@ -28446,22 +40449,22 @@
 388    0x00CE    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0000    //TX_METAL_RTO_THR
@@ -28569,16 +40572,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -28607,19 +40610,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -28946,14 +40949,79 @@
 888    0x00C8    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0024    //RX_RECVFUNC_MODE_0
+0    0xA024    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -29803,10 +41871,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA024    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0021    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0037    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2030    //RX_TDDRC_THRD_2
+272    0x2030    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0478    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0008    //TX_OPERATION_MODE_1
@@ -30050,7 +42970,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF600    //TX_THR_SN_EST_2
 245    0xF400    //TX_THR_SN_EST_3
@@ -30059,20 +42979,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -30090,16 +43010,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000F    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -30123,12 +43043,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -30175,7 +43095,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0102    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
@@ -30187,11 +43107,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -30199,22 +43119,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x7FFF    //TX_MIN_G_CTRL_SSNS
 409    0x0000    //TX_METAL_RTO_THR
@@ -30322,16 +43242,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -30360,19 +43280,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x001C    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -30699,14 +43619,79 @@
 888    0x00C8    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0024    //RX_RECVFUNC_MODE_0
+0    0xA024    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
@@ -31556,10 +44541,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA024    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0021    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0037    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0009    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -31803,7 +45640,7 @@
 239    0x0800    //TX_DT_RESRV_7
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF400    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF600    //TX_THR_SN_EST_2
 245    0xF400    //TX_THR_SN_EST_3
@@ -31812,20 +45649,20 @@
 248    0xF400    //TX_THR_SN_EST_6
 249    0xF600    //TX_THR_SN_EST_7
 250    0x0000    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
 253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x6000    //TX_LAMBDA_NN_EST_0
-259    0x6000    //TX_LAMBDA_NN_EST_1
+259    0x4000    //TX_LAMBDA_NN_EST_1
 260    0x4000    //TX_LAMBDA_NN_EST_2
 261    0x4000    //TX_LAMBDA_NN_EST_3
 262    0x4000    //TX_LAMBDA_NN_EST_4
 263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
+264    0x6000    //TX_LAMBDA_NN_EST_6
 265    0x4000    //TX_LAMBDA_NN_EST_7
 266    0x0400    //TX_N_SN_EST
 267    0x001E    //TX_INBEAM_T
@@ -31843,16 +45680,16 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x000B    //TX_NS_LVL_CTRL_0
-282    0x000F    //TX_NS_LVL_CTRL_1
-283    0x0011    //TX_NS_LVL_CTRL_2
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
 284    0x000F    //TX_NS_LVL_CTRL_3
 285    0x000F    //TX_NS_LVL_CTRL_4
 286    0x000F    //TX_NS_LVL_CTRL_5
 287    0x000F    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000C    //TX_MIN_GAIN_S_0
-290    0x000C    //TX_MIN_GAIN_S_1
-291    0x000F    //TX_MIN_GAIN_S_2
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
 292    0x000C    //TX_MIN_GAIN_S_3
 293    0x000C    //TX_MIN_GAIN_S_4
 294    0x000C    //TX_MIN_GAIN_S_5
@@ -31876,12 +45713,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x2000    //TX_A_POST_FILT_S_0
-315    0x4000    //TX_A_POST_FILT_S_1
+315    0x5000    //TX_A_POST_FILT_S_1
 316    0x5000    //TX_A_POST_FILT_S_2
 317    0x5000    //TX_A_POST_FILT_S_3
 318    0x5000    //TX_A_POST_FILT_S_4
 319    0x5000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+320    0x4000    //TX_A_POST_FILT_S_6
 321    0x5000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
@@ -31928,7 +45765,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0190    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0383    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
 370    0x07D0    //TX_NOISE_TH_1
@@ -31940,11 +45777,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x044C    //TX_NOISE_TH_6
-379    0x0014    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -31952,22 +45789,22 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
 405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
 407    0x012C    //TX_MINENOISE_MIC0_S_TH
 408    0x2900    //TX_MIN_G_CTRL_SSNS
 409    0x0800    //TX_METAL_RTO_THR
@@ -32075,16 +45912,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -32113,19 +45950,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -32450,14 +46287,5419 @@
 886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
 888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x2024    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0014    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0021    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0037    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0024    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0021    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0037    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0009    //TX_OPERATION_MODE_1
+2    0x0020    //TX_PATCH_REG
+3    0x6B6A    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B4C    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x6800    //TX_THR_PITCH_DET_0
+131    0x6000    //TX_THR_PITCH_DET_1
+132    0x5800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0200    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x61A8    //TX_EAD_THR
+151    0x0400    //TX_THR_RE_EST
+152    0x3000    //TX_MIN_EQ_RE_EST_0
+153    0x3000    //TX_MIN_EQ_RE_EST_1
+154    0x4000    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x6000    //TX_MIN_EQ_RE_EST_6
+159    0x6000    //TX_MIN_EQ_RE_EST_7
+160    0x6000    //TX_MIN_EQ_RE_EST_8
+161    0x6000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x4000    //TX_MIN_EQ_RE_EST_11
+164    0x4000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x4000    //TX_LAMBDA_CB_NLE
+167    0x3000    //TX_C_POST_FLT
+168    0x7FFF    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x0800    //TX_DTD_THR1_0
+198    0x0800    //TX_DTD_THR1_1
+199    0x0800    //TX_DTD_THR1_2
+200    0x0800    //TX_DTD_THR1_3
+201    0x0800    //TX_DTD_THR1_4
+202    0x0800    //TX_DTD_THR1_5
+203    0x0800    //TX_DTD_THR1_6
+204    0x0800    //TX_DTD_THR2_0
+205    0x0800    //TX_DTD_THR2_1
+206    0x0800    //TX_DTD_THR2_2
+207    0x0800    //TX_DTD_THR2_3
+208    0x0800    //TX_DTD_THR2_4
+209    0x0100    //TX_DTD_THR2_5
+210    0x0100    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x03E8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00C0    //TX_EPD_OFFSET_00
+233    0x00C0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF700    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xF700    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF600    //TX_THR_SN_EST_5
+248    0xF600    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0200    //TX_DELTA_THR_SN_EST_0
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0200    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x2000    //TX_B_POST_FLT_1
+281    0x0012    //TX_NS_LVL_CTRL_0
+282    0x0016    //TX_NS_LVL_CTRL_1
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
+286    0x0010    //TX_NS_LVL_CTRL_5
+287    0x0019    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x0011    //TX_MIN_GAIN_S_6
+296    0x000C    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7000    //TX_SNRI_SUP_0
+301    0x7000    //TX_SNRI_SUP_1
+302    0x7000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x6000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0016    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x6000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x6000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x6000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
+321    0x6000    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x2000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7CCD    //TX_LAMBDA_PFILT
+339    0x7CCD    //TX_LAMBDA_PFILT_S_0
+340    0x7CCD    //TX_LAMBDA_PFILT_S_1
+341    0x7CCD    //TX_LAMBDA_PFILT_S_2
+342    0x7CCD    //TX_LAMBDA_PFILT_S_3
+343    0x7CCD    //TX_LAMBDA_PFILT_S_4
+344    0x7CCD    //TX_LAMBDA_PFILT_S_5
+345    0x7CCD    //TX_LAMBDA_PFILT_S_6
+346    0x7CCD    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0500    //TX_A_PEPPER
+349    0x1600    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x04E8    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x02A6    //TX_NOISE_TH_1
+371    0x04B0    //TX_NOISE_TH_2
+372    0x3194    //TX_NOISE_TH_3
+373    0x0960    //TX_NOISE_TH_4
+374    0x5555    //TX_NOISE_TH_5
+375    0x3FF4    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x02BC    //TX_NOISE_TH_6
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0001    //TX_TDDRC_THRD_0
+855    0x0001    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x07F2    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x202C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7B02    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0500    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF600    //RX_THR_SN_EST
+24    0x7000    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x202C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2B68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0383    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x05A0    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x0024    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -33309,1763 +52551,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-
-#CASE_NAME  HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
-#TX
-0    0x0009    //TX_OPERATION_MODE_0
-1    0x0009    //TX_OPERATION_MODE_1
-2    0x0020    //TX_PATCH_REG
-3    0x6B6A    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
-5    0x0001    //TX_NUM_MIC
-6    0x0004    //TX_SAMPLINGFREQ_SIG
-7    0x0004    //TX_SAMPLINGFREQ_PROC
-8    0x000A    //TX_FRAME_SZ_SIG
-9    0x000A    //TX_FRAME_SZ
-10    0x0000    //TX_DELAY_OPT
-11    0x0028    //TX_MAX_TAIL_LENGTH
-12    0x0001    //TX_NUM_LOUTCHN
-13    0x0001    //TX_MAXNUM_AECREF
-14    0x0000    //TX_DBG_FUNC_REG
-15    0x0000    //TX_DBG_FUNC_REG1
-16    0x0000    //TX_SYS_RESRV_0
-17    0x0000    //TX_SYS_RESRV_1
-18    0x0000    //TX_SYS_RESRV_2
-19    0x0000    //TX_SYS_RESRV_3
-20    0x0000    //TX_DIST2REF0
-21    0x009B    //TX_DIST2REF1
-22    0x0000    //TX_DIST2REF_02
-23    0x0000    //TX_DIST2REF_03
-24    0x0000    //TX_DIST2REF_04
-25    0x0000    //TX_DIST2REF_05
-26    0x0000    //TX_MMIC
-27    0x0B4C    //TX_PGA_0
-28    0x0800    //TX_PGA_1
-29    0x0000    //TX_PGA_2
-30    0x0000    //TX_PGA_3
-31    0x0000    //TX_PGA_4
-32    0x0000    //TX_PGA_5
-33    0x0000    //TX_MIC_PAIRS
-34    0x0000    //TX_MIC_PAIRS_HS
-35    0x0002    //TX_MICS_FOR_BF
-36    0x0000    //TX_MIC_PAIRS_FORL1
-37    0x0002    //TX_MICS_OF_PAIR0
-38    0x0002    //TX_MICS_OF_PAIR1
-39    0x0002    //TX_MICS_OF_PAIR2
-40    0x0002    //TX_MICS_OF_PAIR3
-41    0x0000    //TX_MIC_DATA_SRC0
-42    0x0001    //TX_MIC_DATA_SRC1
-43    0x0002    //TX_MIC_DATA_SRC2
-44    0x0000    //TX_MIC_DATA_SRC3
-45    0x0000    //TX_MIC_PAIR_CH_04
-46    0x0000    //TX_MIC_PAIR_CH_05
-47    0x0000    //TX_MIC_PAIR_CH_10
-48    0x0000    //TX_MIC_PAIR_CH_11
-49    0x0000    //TX_MIC_PAIR_CH_12
-50    0x0000    //TX_MIC_PAIR_CH_13
-51    0x0000    //TX_MIC_PAIR_CH_14
-52    0x05DC    //TX_HD_BIN_MASK
-53    0x0010    //TX_HD_SUBAND_MASK
-54    0x19A1    //TX_HD_FRAME_AVG_MASK
-55    0x0320    //TX_HD_MIN_FRQ
-56    0x1000    //TX_HD_ALPHA_PSD
-57    0x1100    //TX_T_PHPR1
-58    0x0000    //TX_T_PHPR2
-59    0x0000    //TX_T_PTPR
-60    0x0000    //TX_T_PNPR
-61    0x0000    //TX_T_PAPR1
-62    0xEE6C    //TX_T_PSDVAT
-63    0x0800    //TX_CNT
-64    0x4000    //TX_ANTI_HOWL_GAIN
-65    0x0001    //TX_MICFORBFMARK_0
-66    0x0001    //TX_MICFORBFMARK_1
-67    0x0001    //TX_MICFORBFMARK_2
-68    0x0001    //TX_MICFORBFMARK_3
-69    0x0001    //TX_MICFORBFMARK_4
-70    0x0001    //TX_MICFORBFMARK_5
-71    0x0000    //TX_DIST2REF_10
-72    0x3E00    //TX_DIST2REF_11
-73    0x0000    //TX_DIST2REF2
-74    0x0000    //TX_DIST2REF_13
-75    0x0000    //TX_DIST2REF_14
-76    0x0000    //TX_DIST2REF_15
-77    0x0000    //TX_DIST2REF_20
-78    0x0000    //TX_DIST2REF_21
-79    0x0000    //TX_DIST2REF_22
-80    0x0000    //TX_DIST2REF_23
-81    0x0000    //TX_DIST2REF_24
-82    0x0000    //TX_DIST2REF_25
-83    0x0000    //TX_DIST2REF_30
-84    0x0000    //TX_DIST2REF_31
-85    0x0000    //TX_DIST2REF_32
-86    0x0000    //TX_DIST2REF_33
-87    0x0000    //TX_DIST2REF_34
-88    0x0000    //TX_DIST2REF_35
-89    0x0000    //TX_MIC_LOC_00
-90    0x0000    //TX_MIC_LOC_01
-91    0x0000    //TX_MIC_LOC_02
-92    0x0000    //TX_MIC_LOC_03
-93    0x0000    //TX_MIC_LOC_04
-94    0x0000    //TX_MIC_LOC_05
-95    0x0000    //TX_MIC_LOC_10
-96    0x0000    //TX_MIC_LOC_11
-97    0x0000    //TX_MIC_LOC_12
-98    0x0000    //TX_MIC_LOC_13
-99    0x0000    //TX_MIC_LOC_14
-100    0x0000    //TX_MIC_LOC_15
-101    0x0000    //TX_MIC_LOC_20
-102    0x0000    //TX_MIC_LOC_21
-103    0x0000    //TX_MIC_LOC_22
-104    0x0000    //TX_MIC_LOC_23
-105    0x0000    //TX_MIC_LOC_24
-106    0x0000    //TX_MIC_LOC_25
-107    0x0200    //TX_MIC_REFBLK_VOLUME
-108    0x0800    //TX_MIC_BLOCK_VOLUME
-109    0x0000    //TX_INVERSE_MASK
-110    0x0000    //TX_ADCS_MASK
-111    0x04D0    //TX_ADCS_GAIN
-112    0x4000    //TX_NFC_GAINFAC
-113    0x0000    //TX_MAINMIC_BLKFACTOR
-114    0x0000    //TX_REFMIC_BLKFACTOR
-115    0x0000    //TX_BLMIC_BLKFACTOR
-116    0x0000    //TX_BRMIC_BLKFACTOR
-117    0x0031    //TX_MICBLK_START_BIN
-118    0x0060    //TX_MICBLK_END_BIN
-119    0x0015    //TX_MICBLK_FE_HOLD
-120    0xFFF2    //TX_MICBLK_MR_EXP_TH
-121    0xFFF2    //TX_MICBLK_LR_EXP_TH
-122    0x0000    //TX_FENE_HOLD
-123    0x4000    //TX_FE_ENER_TH_MTS
-124    0x0004    //TX_FE_ENER_TH_EXP
-125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
-126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
-127    0x0010    //TX_MIC_BLOCK_N
-128    0x7E56    //TX_A_HP
-129    0x4000    //TX_B_PE
-130    0x6800    //TX_THR_PITCH_DET_0
-131    0x6000    //TX_THR_PITCH_DET_1
-132    0x5800    //TX_THR_PITCH_DET_2
-133    0x0008    //TX_PITCH_BFR_LEN
-134    0x0003    //TX_SBD_PITCH_DET
-135    0x0050    //TX_TD_AEC_L
-136    0x4000    //TX_MU0_UNP_TD_AEC
-137    0x1000    //TX_MU0_PTD_TD_AEC
-138    0x0000    //TX_PP_RESRV_0
-139    0x2A94    //TX_PP_RESRV_1
-140    0x55F0    //TX_PP_RESRV_2
-141    0x0000    //TX_PP_RESRV_3
-142    0x0000    //TX_PP_RESRV_4
-143    0x0000    //TX_PP_RESRV_5
-144    0x0000    //TX_PP_RESRV_6
-145    0x0000    //TX_PP_RESRV_7
-146    0x001E    //TX_TAIL_LENGTH
-147    0x0200    //TX_AEC_REF_GAIN_0
-148    0x0800    //TX_AEC_REF_GAIN_1
-149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x61A8    //TX_EAD_THR
-151    0x0400    //TX_THR_RE_EST
-152    0x3000    //TX_MIN_EQ_RE_EST_0
-153    0x3000    //TX_MIN_EQ_RE_EST_1
-154    0x4000    //TX_MIN_EQ_RE_EST_2
-155    0x0800    //TX_MIN_EQ_RE_EST_3
-156    0x0800    //TX_MIN_EQ_RE_EST_4
-157    0x0800    //TX_MIN_EQ_RE_EST_5
-158    0x6000    //TX_MIN_EQ_RE_EST_6
-159    0x6000    //TX_MIN_EQ_RE_EST_7
-160    0x6000    //TX_MIN_EQ_RE_EST_8
-161    0x6000    //TX_MIN_EQ_RE_EST_9
-162    0x4000    //TX_MIN_EQ_RE_EST_10
-163    0x4000    //TX_MIN_EQ_RE_EST_11
-164    0x4000    //TX_MIN_EQ_RE_EST_12
-165    0x3000    //TX_LAMBDA_RE_EST
-166    0x4000    //TX_LAMBDA_CB_NLE
-167    0x3000    //TX_C_POST_FLT
-168    0x7FFF    //TX_GAIN_NP
-169    0x00C8    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x03E8    //TX_DT2_HOLD_N
-172    0x6666    //TX_AEC_RESRV_0
-173    0x0000    //TX_AEC_RESRV_1
-174    0x0014    //TX_AEC_RESRV_2
-175    0x0000    //TX_MIC_DELAY_LENGTH
-176    0x0000    //TX_REF_DELAY_LENGTH
-177    0x0000    //TX_ADD_LINEIN_GAINL
-178    0x0000    //TX_ADD_LINEIN_GAINH
-179    0x0000    //TX_MIN_EQ_RE_EST_14
-180    0x0000    //TX_DTD_THR1_8
-181    0x7FFF    //TX_DTD_THR2_8
-182    0x0000    //TX_DTD_MIC_BLK2
-183    0x0008    //TX_FRQ_LIN_LEN
-184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
-185    0x6000    //TX_MU0_UNP_FRQ_AEC
-186    0x4000    //TX_MU0_PTD_FRQ_AEC
-187    0x000A    //TX_MINENOISETH
-188    0x0800    //TX_MU0_RE_EST
-189    0x0001    //TX_AEC_NUM_CH
-190    0x0000    //TX_BIGECHOATTENUATION_MAX
-191    0x2000    //TX_A_POST_FLT_MICBLK
-192    0x0000    //TX_BLKENERTH
-193    0x0000    //TX_BLKENERHIGHTH
-194    0x0000    //TX_NORMENERTH
-195    0x0000    //TX_NORMENERHIGHTH
-196    0x0000    //TX_NORMENERHIGHTHL
-197    0x0800    //TX_DTD_THR1_0
-198    0x0800    //TX_DTD_THR1_1
-199    0x0800    //TX_DTD_THR1_2
-200    0x0800    //TX_DTD_THR1_3
-201    0x0800    //TX_DTD_THR1_4
-202    0x0800    //TX_DTD_THR1_5
-203    0x0800    //TX_DTD_THR1_6
-204    0x0800    //TX_DTD_THR2_0
-205    0x0800    //TX_DTD_THR2_1
-206    0x0800    //TX_DTD_THR2_2
-207    0x0800    //TX_DTD_THR2_3
-208    0x0800    //TX_DTD_THR2_4
-209    0x0100    //TX_DTD_THR2_5
-210    0x0100    //TX_DTD_THR2_6
-211    0x7FFF    //TX_DTD_THR3
-212    0x0000    //TX_SPK_CUT_K
-213    0x03E8    //TX_DT_CUT_K
-214    0x0CCD    //TX_DT_CUT_THR
-215    0x04EB    //TX_COMFORT_G
-216    0x01F4    //TX_POWER_YOUT_TH
-217    0x4000    //TX_FDPFGAINECHO
-218    0x0000    //TX_DTD_HD_THR
-219    0x0000    //TX_SPK_CUT_K_S
-220    0x0000    //TX_DTD_MIC_BLK
-221    0x0400    //TX_ADPT_STRICT_L
-222    0x0200    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
-229    0x7FFF    //TX_B_POST_FILT_ECHO_H
-230    0x0200    //TX_MIN_G_CTRL_ECHO
-231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
-232    0x00C0    //TX_EPD_OFFSET_00
-233    0x00C0    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
-235    0x3A98    //TX_RATIO_DT_H_TH_CUT
-236    0x7FFF    //TX_MIN_EQ_RE_EST_13
-237    0x7FFF    //TX_DTD_THR1_7
-238    0x7FFF    //TX_DTD_THR2_7
-239    0x0800    //TX_DT_RESRV_7
-240    0x0800    //TX_DT_RESRV_8
-241    0x0000    //TX_DT_RESRV_9
-242    0xF700    //TX_THR_SN_EST_0
-243    0xFB00    //TX_THR_SN_EST_1
-244    0xFA00    //TX_THR_SN_EST_2
-245    0xF700    //TX_THR_SN_EST_3
-246    0xFA00    //TX_THR_SN_EST_4
-247    0xF600    //TX_THR_SN_EST_5
-248    0xF600    //TX_THR_SN_EST_6
-249    0xF600    //TX_THR_SN_EST_7
-250    0x0200    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0400    //TX_DELTA_THR_SN_EST_2
-253    0x0300    //TX_DELTA_THR_SN_EST_3
-254    0x0600    //TX_DELTA_THR_SN_EST_4
-255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
-257    0x0200    //TX_DELTA_THR_SN_EST_7
-258    0x4000    //TX_LAMBDA_NN_EST_0
-259    0x4000    //TX_LAMBDA_NN_EST_1
-260    0x4000    //TX_LAMBDA_NN_EST_2
-261    0x4000    //TX_LAMBDA_NN_EST_3
-262    0x4000    //TX_LAMBDA_NN_EST_4
-263    0x4000    //TX_LAMBDA_NN_EST_5
-264    0x4000    //TX_LAMBDA_NN_EST_6
-265    0x4000    //TX_LAMBDA_NN_EST_7
-266    0x0400    //TX_N_SN_EST
-267    0x001E    //TX_INBEAM_T
-268    0x0041    //TX_INBEAMHOLDT
-269    0x2000    //TX_G_STRICT
-270    0x2000    //TX_EQ_THR_BF
-271    0x799A    //TX_LAMBDA_EQ_BF
-272    0x1000    //TX_NE_RTO_TH
-273    0x0400    //TX_NE_RTO_TH_L
-274    0x0800    //TX_MAINREFRTOH_TH_H
-275    0x0800    //TX_MAINREFRTOH_TH_L
-276    0x0800    //TX_MAINREFRTO_TH_H
-277    0x0800    //TX_MAINREFRTO_TH_L
-278    0x0200    //TX_MAINREFRTO_TH_EQ
-279    0x2000    //TX_B_POST_FLT_0
-280    0x2000    //TX_B_POST_FLT_1
-281    0x0012    //TX_NS_LVL_CTRL_0
-282    0x0019    //TX_NS_LVL_CTRL_1
-283    0x0016    //TX_NS_LVL_CTRL_2
-284    0x0016    //TX_NS_LVL_CTRL_3
-285    0x0019    //TX_NS_LVL_CTRL_4
-286    0x0010    //TX_NS_LVL_CTRL_5
-287    0x0010    //TX_NS_LVL_CTRL_6
-288    0x0010    //TX_NS_LVL_CTRL_7
-289    0x000C    //TX_MIN_GAIN_S_0
-290    0x0011    //TX_MIN_GAIN_S_1
-291    0x000C    //TX_MIN_GAIN_S_2
-292    0x000C    //TX_MIN_GAIN_S_3
-293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000C    //TX_MIN_GAIN_S_5
-295    0x000C    //TX_MIN_GAIN_S_6
-296    0x000C    //TX_MIN_GAIN_S_7
-297    0x7FFF    //TX_NMOS_SUP
-298    0x0000    //TX_NS_MAX_PRI_SNR_TH
-299    0x0000    //TX_NMOS_SUP_MENSA
-300    0x7000    //TX_SNRI_SUP_0
-301    0x6000    //TX_SNRI_SUP_1
-302    0x7000    //TX_SNRI_SUP_2
-303    0x7000    //TX_SNRI_SUP_3
-304    0x6000    //TX_SNRI_SUP_4
-305    0x7FFF    //TX_SNRI_SUP_5
-306    0x7FFF    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
-308    0x7FFF    //TX_THR_LFNS
-309    0x0016    //TX_G_LFNS
-310    0x09C4    //TX_GAIN0_NTH
-311    0x000A    //TX_MUSIC_MORENS
-312    0x7FFF    //TX_A_POST_FILT_0
-313    0x2000    //TX_A_POST_FILT_1
-314    0x6000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x6000    //TX_A_POST_FILT_S_2
-317    0x6000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x6000    //TX_A_POST_FILT_S_5
-320    0x6000    //TX_A_POST_FILT_S_6
-321    0x6000    //TX_A_POST_FILT_S_7
-322    0x2000    //TX_B_POST_FILT_0
-323    0x2000    //TX_B_POST_FILT_1
-324    0x4000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
-326    0x2000    //TX_B_POST_FILT_4
-327    0x2000    //TX_B_POST_FILT_5
-328    0x2000    //TX_B_POST_FILT_6
-329    0x2000    //TX_B_POST_FILT_7
-330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
-331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
-332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
-333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
-334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
-337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7CCD    //TX_LAMBDA_PFILT
-339    0x7CCD    //TX_LAMBDA_PFILT_S_0
-340    0x7CCD    //TX_LAMBDA_PFILT_S_1
-341    0x7CCD    //TX_LAMBDA_PFILT_S_2
-342    0x7CCD    //TX_LAMBDA_PFILT_S_3
-343    0x7CCD    //TX_LAMBDA_PFILT_S_4
-344    0x7CCD    //TX_LAMBDA_PFILT_S_5
-345    0x7CCD    //TX_LAMBDA_PFILT_S_6
-346    0x7CCD    //TX_LAMBDA_PFILT_S_7
-347    0x0200    //TX_K_PEPPER
-348    0x0500    //TX_A_PEPPER
-349    0x1600    //TX_K_PEPPER_HF
-350    0x0400    //TX_A_PEPPER_HF
-351    0x0001    //TX_HMNC_BST_FLG
-352    0x0200    //TX_HMNC_BST_THR
-353    0x0800    //TX_DT_BINVAD_TH_0
-354    0x0800    //TX_DT_BINVAD_TH_1
-355    0x0800    //TX_DT_BINVAD_TH_2
-356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0000    //TX_C_POST_FLT_DT
-359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
-360    0x0100    //TX_DT_BOOST
-361    0x0000    //TX_BF_SGRAD_FLG
-362    0x0005    //TX_BF_DVG_TH
-363    0x001E    //TX_SN_C_F
-364    0x0000    //TX_K_APT
-365    0x0001    //TX_NOISEDET
-366    0x0190    //TX_NDETCT
-367    0x0020    //TX_NOISE_TH_0
-368    0x7FFF    //TX_NOISE_TH_0_2
-369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x02A6    //TX_NOISE_TH_1
-371    0x04B0    //TX_NOISE_TH_2
-372    0x3194    //TX_NOISE_TH_3
-373    0x0960    //TX_NOISE_TH_4
-374    0x5555    //TX_NOISE_TH_5
-375    0x3FF4    //TX_NOISE_TH_5_2
-376    0x0001    //TX_NOISE_TH_5_3
-377    0x0000    //TX_NOISE_TH_5_4
-378    0x02BC    //TX_NOISE_TH_6
-379    0x0020    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
-384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
-385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
-386    0x0333    //TX_OUT_ENER_S_TH_NOISY
-387    0x019A    //TX_OUT_ENER_TH_NOISE
-388    0x0333    //TX_OUT_ENER_TH_SPEECH
-389    0x2000    //TX_SN_NPB_GAIN
-390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
-397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
-400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0004    //TX_MAXLEVEL_CNG
-402    0x00B4    //TX_STN_NOISE_TH
-403    0x4000    //TX_POST_MASK_SUP
-404    0x7FFF    //TX_POST_MASK_ADJUST
-405    0x00C8    //TX_NS_ENOISE_MIC0_TH
-406    0x0020    //TX_MINENOISE_MIC0_TH
-407    0x012C    //TX_MINENOISE_MIC0_S_TH
-408    0x2900    //TX_MIN_G_CTRL_SSNS
-409    0x0800    //TX_METAL_RTO_THR
-410    0x4848    //TX_NS_FP_K_METAL
-411    0x3A98    //TX_NOISEDET_BOOST_TH
-412    0x0FA0    //TX_NSMOOTH_TH
-413    0x0000    //TX_NS_RESRV_8
-414    0x1800    //TX_RHO_UPB
-415    0x0BB8    //TX_N_HOLD_HS
-416    0x0050    //TX_N_RHO_BFR0
-417    0x7FFF    //TX_LAMBDA_ARSP_EST
-418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
-419    0x0CCD    //TX_THR_STD_NSR
-420    0x019A    //TX_THR_STD_PLH
-421    0x2AF8    //TX_N_HOLD_STD
-422    0x0066    //TX_THR_STD_RHO
-423    0x2000    //TX_BF_RESET_THR_HS
-424    0x09C4    //TX_SB_RTO_MEAN_TH
-425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
-426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
-427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
-428    0x0000    //TX_WTA_EN_RTO_TH
-429    0x0000    //TX_TOP_ENER_TH_F
-430    0x0000    //TX_DESIRED_TALK_HOLDT
-431    0x0800    //TX_MIC_BLOCK_FACTOR
-432    0x0000    //TX_NSEST_BFRLRNRDC
-433    0x0000    //TX_THR_POST_FLT_HS
-434    0x0010    //TX_HS_VAD_BIN
-435    0x2666    //TX_THR_VAD_HS
-436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
-437    0x0032    //TX_SILENCE_T
-438    0x0000    //TX_A_POST_FLT_WTA
-439    0x799A    //TX_LAMBDA_PFLT_WTA
-440    0x0000    //TX_SB_RHO_MEAN2_TH
-441    0x0190    //TX_SB_RHO_MEAN3_TH
-442    0x0000    //TX_HS_RESRV_4
-443    0x0000    //TX_HS_RESRV_5
-444    0x003C    //TX_DOA_VAD_THR_1
-445    0x0000    //TX_DOA_VAD_THR_2
-446    0x0028    //TX_DOA_VAD_THR1_0
-447    0x0028    //TX_DOA_VAD_THR1_1
-448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
-449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
-450    0x005A    //TX_DFLT_SRC_DOA_0A
-451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
-452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
-453    0x0000    //TX_DFLT_SRC_DOA_0B
-454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
-455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
-456    0x0000    //TX_DFLT_SRC_DOA_0C
-457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
-458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
-459    0x0000    //TX_DFLT_SRC_DOA_0D
-460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
-461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
-462    0x005A    //TX_DFLT_SRC_DOA_1A
-463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
-464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
-465    0x005A    //TX_DFLT_SRC_DOA_1B
-466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
-467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
-468    0x005A    //TX_DFLT_SRC_DOA_1C
-469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
-470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
-471    0x005A    //TX_DFLT_SRC_DOA_1D
-472    0x0100    //TX_BF_HOLDOFF_T
-473    0x7FFF    //TX_DOA_COST_FACTOR
-474    0x4000    //TX_MAINTOREFR_TH0
-475    0x071C    //TX_DOA_TRK_THR
-476    0x012C    //TX_DOA_TRACK_HT
-477    0x0200    //TX_N1_HOLD_HF
-478    0x0100    //TX_N2_HOLD_HF
-479    0x3000    //TX_BF_RESET_THR_HF
-480    0x7333    //TX_DOA_SMOOTH
-481    0x0800    //TX_MU_BF
-482    0x0800    //TX_BF_MU_LF_B2
-483    0x0040    //TX_BF_FC_END_BIN_B2
-484    0x0020    //TX_BF_FC_END_BIN
-485    0x0000    //TX_HF_RESRV_25
-486    0x0000    //TX_HF_RESRV_26
-487    0x0007    //TX_N_DOA_SEED
-488    0x0001    //TX_FINE_DOA_SEARCH_FLG
-489    0x0000    //TX_HF_RESRV_27
-490    0x038E    //TX_DLT_SRC_DOA_RNG
-491    0x0200    //TX_BF_MU_LF
-492    0x0000    //TX_DFLT_SRC_LOC_0
-493    0x7FFF    //TX_DFLT_SRC_LOC_1
-494    0x0000    //TX_DFLT_SRC_LOC_2
-495    0x038E    //TX_DOA_TRACK_VADTH
-496    0x0000    //TX_DOA_TRACK_NEW
-497    0x01E0    //TX_NOR_OFF_THR
-498    0x7C00    //TX_MORE_ON_700HZ_THR
-499    0x2000    //TX_MU_BF_ADPT_NS
-500    0x0000    //TX_ADAPT_LEN
-501    0x6666    //TX_MORE_SNS
-502    0x0000    //TX_NOR_OFF_TH1
-503    0x0000    //TX_WIDE_MASK_TH
-504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
-505    0x6000    //TX_C_POST_FLT_CUT
-506    0x2000    //TX_RADIODTLV
-507    0x0320    //TX_POWER_LINEIN_TH
-508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
-510    0x0C80    //TX_ECHO_TH
-511    0x6666    //TX_MIC_TO_BFGAIN
-512    0x0000    //TX_MICTOBFGAIN0
-513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
-524    0x0000    //TX_DR_RESRV_5
-525    0x0000    //TX_DR_RESRV_6
-526    0x0000    //TX_DR_RESRV_7
-527    0x0000    //TX_DR_RESRV_8
-528    0x1333    //TX_WIND_MARK_TH
-529    0x399A    //TX_CORR_THR
-530    0x0004    //TX_SNR_THR
-531    0x0010    //TX_ENGY_THR
-532    0x1770    //TX_CORR_HIGH_TH
-533    0x6000    //TX_ENGY_THR_2
-534    0x3400    //TX_MEAN_RTO_THR
-535    0x0028    //TX_WNS_ENOISE_MIC0_TH
-536    0x3000    //TX_RATIOMICL_TH
-537    0x64CD    //TX_CALIG_HS
-538    0x0000    //TX_LVL_CTRL
-539    0x0014    //TX_WIND_SUPRTO
-540    0x000A    //TX_WNS_MIN_G
-541    0x0000    //TX_WNS_B_POST_FLT
-542    0x2800    //TX_RATIOMICH_TH
-543    0xD120    //TX_WIND_INBEAM_L_TH
-544    0x0FA0    //TX_WIND_INBEAM_H_TH
-545    0x2000    //TX_WNS_RESRV_0
-546    0x59D8    //TX_WNS_RESRV_1
-547    0x0000    //TX_WNS_RESRV_2
-548    0x0000    //TX_WNS_RESRV_3
-549    0x0000    //TX_WNS_RESRV_4
-550    0x0000    //TX_WNS_RESRV_5
-551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
-565    0x0000    //TX_PB_RESRV_1
-566    0x0020    //TX_FDEQ_SUBNUM
-567    0x4848    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4848    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4848    //TX_FDEQ_GAIN_9
-577    0x4848    //TX_FDEQ_GAIN_10
-578    0x4848    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
-581    0x4848    //TX_FDEQ_GAIN_14
-582    0x4848    //TX_FDEQ_GAIN_15
-583    0x4848    //TX_FDEQ_GAIN_16
-584    0x4848    //TX_FDEQ_GAIN_17
-585    0x4848    //TX_FDEQ_GAIN_18
-586    0x4848    //TX_FDEQ_GAIN_19
-587    0x4848    //TX_FDEQ_GAIN_20
-588    0x4848    //TX_FDEQ_GAIN_21
-589    0x4848    //TX_FDEQ_GAIN_22
-590    0x4848    //TX_FDEQ_GAIN_23
-591    0x0202    //TX_FDEQ_BIN_0
-592    0x0203    //TX_FDEQ_BIN_1
-593    0x0304    //TX_FDEQ_BIN_2
-594    0x0405    //TX_FDEQ_BIN_3
-595    0x0607    //TX_FDEQ_BIN_4
-596    0x0809    //TX_FDEQ_BIN_5
-597    0x0A0B    //TX_FDEQ_BIN_6
-598    0x0C0D    //TX_FDEQ_BIN_7
-599    0x0E0F    //TX_FDEQ_BIN_8
-600    0x1011    //TX_FDEQ_BIN_9
-601    0x1214    //TX_FDEQ_BIN_10
-602    0x1618    //TX_FDEQ_BIN_11
-603    0x1C1C    //TX_FDEQ_BIN_12
-604    0x2020    //TX_FDEQ_BIN_13
-605    0x2020    //TX_FDEQ_BIN_14
-606    0x2011    //TX_FDEQ_BIN_15
-607    0x0000    //TX_FDEQ_BIN_16
-608    0x0000    //TX_FDEQ_BIN_17
-609    0x0000    //TX_FDEQ_BIN_18
-610    0x0000    //TX_FDEQ_BIN_19
-611    0x0000    //TX_FDEQ_BIN_20
-612    0x0000    //TX_FDEQ_BIN_21
-613    0x0000    //TX_FDEQ_BIN_22
-614    0x0000    //TX_FDEQ_BIN_23
-615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
-617    0x4848    //TX_PREEQ_GAIN_MIC0_0
-618    0x4848    //TX_PREEQ_GAIN_MIC0_1
-619    0x4848    //TX_PREEQ_GAIN_MIC0_2
-620    0x4848    //TX_PREEQ_GAIN_MIC0_3
-621    0x4848    //TX_PREEQ_GAIN_MIC0_4
-622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x4848    //TX_PREEQ_GAIN_MIC0_7
-625    0x4848    //TX_PREEQ_GAIN_MIC0_8
-626    0x4848    //TX_PREEQ_GAIN_MIC0_9
-627    0x4848    //TX_PREEQ_GAIN_MIC0_10
-628    0x4848    //TX_PREEQ_GAIN_MIC0_11
-629    0x4848    //TX_PREEQ_GAIN_MIC0_12
-630    0x4848    //TX_PREEQ_GAIN_MIC0_13
-631    0x4848    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
-634    0x4848    //TX_PREEQ_GAIN_MIC0_17
-635    0x4848    //TX_PREEQ_GAIN_MIC0_18
-636    0x4848    //TX_PREEQ_GAIN_MIC0_19
-637    0x4848    //TX_PREEQ_GAIN_MIC0_20
-638    0x4848    //TX_PREEQ_GAIN_MIC0_21
-639    0x4848    //TX_PREEQ_GAIN_MIC0_22
-640    0x4848    //TX_PREEQ_GAIN_MIC0_23
-641    0x0E10    //TX_PREEQ_BIN_MIC0_0
-642    0x1010    //TX_PREEQ_BIN_MIC0_1
-643    0x1010    //TX_PREEQ_BIN_MIC0_2
-644    0x1010    //TX_PREEQ_BIN_MIC0_3
-645    0x1010    //TX_PREEQ_BIN_MIC0_4
-646    0x1010    //TX_PREEQ_BIN_MIC0_5
-647    0x1010    //TX_PREEQ_BIN_MIC0_6
-648    0x1010    //TX_PREEQ_BIN_MIC0_7
-649    0x1010    //TX_PREEQ_BIN_MIC0_8
-650    0x1010    //TX_PREEQ_BIN_MIC0_9
-651    0x1010    //TX_PREEQ_BIN_MIC0_10
-652    0x1010    //TX_PREEQ_BIN_MIC0_11
-653    0x1010    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
-655    0x1010    //TX_PREEQ_BIN_MIC0_14
-656    0x0200    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
-658    0x0000    //TX_PREEQ_BIN_MIC0_17
-659    0x0000    //TX_PREEQ_BIN_MIC0_18
-660    0x0000    //TX_PREEQ_BIN_MIC0_19
-661    0x0000    //TX_PREEQ_BIN_MIC0_20
-662    0x0000    //TX_PREEQ_BIN_MIC0_21
-663    0x0000    //TX_PREEQ_BIN_MIC0_22
-664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
-666    0x4848    //TX_PREEQ_GAIN_MIC1_0
-667    0x4848    //TX_PREEQ_GAIN_MIC1_1
-668    0x4848    //TX_PREEQ_GAIN_MIC1_2
-669    0x4848    //TX_PREEQ_GAIN_MIC1_3
-670    0x4848    //TX_PREEQ_GAIN_MIC1_4
-671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
-683    0x4848    //TX_PREEQ_GAIN_MIC1_17
-684    0x4848    //TX_PREEQ_GAIN_MIC1_18
-685    0x4848    //TX_PREEQ_GAIN_MIC1_19
-686    0x4848    //TX_PREEQ_GAIN_MIC1_20
-687    0x4848    //TX_PREEQ_GAIN_MIC1_21
-688    0x4848    //TX_PREEQ_GAIN_MIC1_22
-689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x0E10    //TX_PREEQ_BIN_MIC1_0
-691    0x1010    //TX_PREEQ_BIN_MIC1_1
-692    0x1010    //TX_PREEQ_BIN_MIC1_2
-693    0x1010    //TX_PREEQ_BIN_MIC1_3
-694    0x1010    //TX_PREEQ_BIN_MIC1_4
-695    0x1010    //TX_PREEQ_BIN_MIC1_5
-696    0x1010    //TX_PREEQ_BIN_MIC1_6
-697    0x1010    //TX_PREEQ_BIN_MIC1_7
-698    0x1010    //TX_PREEQ_BIN_MIC1_8
-699    0x1010    //TX_PREEQ_BIN_MIC1_9
-700    0x1010    //TX_PREEQ_BIN_MIC1_10
-701    0x1010    //TX_PREEQ_BIN_MIC1_11
-702    0x1010    //TX_PREEQ_BIN_MIC1_12
-703    0x1010    //TX_PREEQ_BIN_MIC1_13
-704    0x1010    //TX_PREEQ_BIN_MIC1_14
-705    0x0200    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
-707    0x0000    //TX_PREEQ_BIN_MIC1_17
-708    0x0000    //TX_PREEQ_BIN_MIC1_18
-709    0x0000    //TX_PREEQ_BIN_MIC1_19
-710    0x0000    //TX_PREEQ_BIN_MIC1_20
-711    0x0000    //TX_PREEQ_BIN_MIC1_21
-712    0x0000    //TX_PREEQ_BIN_MIC1_22
-713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
-715    0x4848    //TX_PREEQ_GAIN_MIC2_0
-716    0x4848    //TX_PREEQ_GAIN_MIC2_1
-717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
-732    0x4848    //TX_PREEQ_GAIN_MIC2_17
-733    0x4848    //TX_PREEQ_GAIN_MIC2_18
-734    0x4848    //TX_PREEQ_GAIN_MIC2_19
-735    0x4848    //TX_PREEQ_GAIN_MIC2_20
-736    0x4848    //TX_PREEQ_GAIN_MIC2_21
-737    0x4848    //TX_PREEQ_GAIN_MIC2_22
-738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0E10    //TX_PREEQ_BIN_MIC2_0
-740    0x1010    //TX_PREEQ_BIN_MIC2_1
-741    0x1010    //TX_PREEQ_BIN_MIC2_2
-742    0x1010    //TX_PREEQ_BIN_MIC2_3
-743    0x1010    //TX_PREEQ_BIN_MIC2_4
-744    0x1010    //TX_PREEQ_BIN_MIC2_5
-745    0x1010    //TX_PREEQ_BIN_MIC2_6
-746    0x1010    //TX_PREEQ_BIN_MIC2_7
-747    0x1010    //TX_PREEQ_BIN_MIC2_8
-748    0x1010    //TX_PREEQ_BIN_MIC2_9
-749    0x1010    //TX_PREEQ_BIN_MIC2_10
-750    0x1010    //TX_PREEQ_BIN_MIC2_11
-751    0x1010    //TX_PREEQ_BIN_MIC2_12
-752    0x1010    //TX_PREEQ_BIN_MIC2_13
-753    0x1010    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
-756    0x0000    //TX_PREEQ_BIN_MIC2_17
-757    0x0000    //TX_PREEQ_BIN_MIC2_18
-758    0x0000    //TX_PREEQ_BIN_MIC2_19
-759    0x0000    //TX_PREEQ_BIN_MIC2_20
-760    0x0000    //TX_PREEQ_BIN_MIC2_21
-761    0x0000    //TX_PREEQ_BIN_MIC2_22
-762    0x0000    //TX_PREEQ_BIN_MIC2_23
-763    0x0006    //TX_MASKING_ABILITY
-764    0x2000    //TX_NND_WEIGHT
-765    0x0060    //TX_MIC_CALIBRATION_0
-766    0x0060    //TX_MIC_CALIBRATION_1
-767    0x0070    //TX_MIC_CALIBRATION_2
-768    0x0070    //TX_MIC_CALIBRATION_3
-769    0x0050    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
-771    0x0040    //TX_MIC_PWR_BIAS_2
-772    0x0040    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
-775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
-777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
-778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
-779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
-780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
-781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
-782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0C00    //TX_TDDRC_ALPHA_UP_01
-784    0x0C00    //TX_TDDRC_ALPHA_UP_02
-785    0x0C00    //TX_TDDRC_ALPHA_UP_03
-786    0x0C00    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
-792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
-793    0x0000    //TX_TDDRC_RESRV_0
-794    0x0000    //TX_TDDRC_RESRV_1
-795    0x0018    //TX_FDDRC_BAND_MARGIN_0
-796    0x0030    //TX_FDDRC_BAND_MARGIN_1
-797    0x0050    //TX_FDDRC_BAND_MARGIN_2
-798    0x0080    //TX_FDDRC_BAND_MARGIN_3
-799    0x0007    //TX_FDDRC_BLOCK_EXP
-800    0x5000    //TX_FDDRC_THRD_2_0
-801    0x5000    //TX_FDDRC_THRD_2_1
-802    0x5000    //TX_FDDRC_THRD_2_2
-803    0x5000    //TX_FDDRC_THRD_2_3
-804    0x6400    //TX_FDDRC_THRD_3_0
-805    0x6400    //TX_FDDRC_THRD_3_1
-806    0x6400    //TX_FDDRC_THRD_3_2
-807    0x6400    //TX_FDDRC_THRD_3_3
-808    0x2000    //TX_FDDRC_SLANT_0_0
-809    0x2000    //TX_FDDRC_SLANT_0_1
-810    0x2000    //TX_FDDRC_SLANT_0_2
-811    0x2000    //TX_FDDRC_SLANT_0_3
-812    0x5333    //TX_FDDRC_SLANT_1_0
-813    0x5333    //TX_FDDRC_SLANT_1_1
-814    0x5333    //TX_FDDRC_SLANT_1_2
-815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0000    //TX_DEADMIC_SILENCE_TH
-817    0x0000    //TX_MIC_DEGRADE_TH
-818    0x0000    //TX_DEADMIC_CNT
-819    0x0000    //TX_MIC_DEGRADE_CNT
-820    0x0000    //TX_FDDRC_RESRV_4
-821    0x0000    //TX_FDDRC_RESRV_5
-822    0x0000    //TX_FDDRC_RESRV_6
-823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
-824    0x0001    //TX_KS_CONFIG
-825    0x7FFF    //TX_KS_GAIN_MIN
-826    0x0000    //TX_KS_RESRV_0
-827    0x0000    //TX_KS_RESRV_1
-828    0x0000    //TX_KS_RESRV_2
-829    0x7C00    //TX_LAMBDA_PKA_FP
-830    0x2000    //TX_TPKA_FP
-831    0x0080    //TX_MIN_G_FP
-832    0x2000    //TX_MAX_G_FP
-833    0x4848    //TX_FFP_FP_K_METAL
-834    0x4000    //TX_A_POST_FLT_FP
-835    0x0F5C    //TX_RTO_OUTBEAM_TH
-836    0x4CCD    //TX_TPKA_FP_THD
-837    0x0000    //TX_MAX_G_FP_BLK
-838    0x0000    //TX_FFP_FADEIN
-839    0x0000    //TX_FFP_FADEOUT
-840    0x0000    //TX_WHISPERCTH
-841    0x0000    //TX_WHISPERHOLDT
-842    0x0000    //TX_WHISP_ENTHH
-843    0x0000    //TX_WHISP_ENTHL
-844    0x0000    //TX_WHISP_RTOTH
-845    0x0000    //TX_WHISP_RTOTH2
-846    0x0000    //TX_MUTE_PERIOD
-847    0x0000    //TX_FADE_IN_PERIOD
-848    0x0100    //TX_FFP_RESRV_2
-849    0x0020    //TX_FFP_RESRV_3
-850    0x0000    //TX_FFP_RESRV_4
-851    0x0000    //TX_FFP_RESRV_5
-852    0x0000    //TX_FFP_RESRV_6
-853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0001    //TX_TDDRC_THRD_1
-856    0x1900    //TX_TDDRC_THRD_2
-857    0x1900    //TX_TDDRC_THRD_3
-858    0x3000    //TX_TDDRC_SLANT_0
-859    0x7B00    //TX_TDDRC_SLANT_1
-860    0x0C00    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
-862    0x0000    //TX_TDDRC_HMNC_FLAG
-863    0x199A    //TX_TDDRC_HMNC_GAIN
-864    0x0000    //TX_TDDRC_SMT_FLAG
-865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x07F2    //TX_TDDRC_DRC_GAIN
-867    0x7FFF    //TX_TDDRC_LMT_THRD
-868    0x0000    //TX_TDDRC_LMT_ALPHA
-869    0x0000    //TX_TFMASKLTH
-870    0x0000    //TX_TFMASKLTHL
-871    0x0CCD    //TX_TFMASKHTH
-872    0x0CCD    //TX_TFMASKLTH_BINVAD
-873    0xF333    //TX_TFMASKLTH_NS_EST
-874    0x2CCD    //TX_TFMASKLTH_DOA
-875    0xECCD    //TX_TFMASKTH_BLESSCUT
-876    0x1000    //TX_B_LESSCUT_RTO_MASK
-877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
-878    0x2000    //TX_B_POST_FLT_MASK
-879    0x0000    //TX_B_POST_FLT_MASK1
-880    0x5333    //TX_GAIN_WIND_MASK
-881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
-882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
-883    0x7333    //TX_FASTNS_OUTIN_TH
-884    0x0CCD    //TX_FASTNS_TFMASK_TH
-885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
-886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
-887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
-888    0x0028    //TX_FASTNS_ARSPC_TH
-889    0xC000    //TX_FASTNS_MASK5_TH
-890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7000    //TX_A_LESSCUT_RTO_MASK
-892    0x1770    //TX_FASTNS_NOISETH
-893    0xC000    //TX_FASTNS_SSA_THLFL
-894    0xC000    //TX_FASTNS_SSA_THHFL
-895    0xCCCC    //TX_FASTNS_SSA_THLFH
-896    0xD999    //TX_FASTNS_SSA_THHFH
-#RX
-0    0x002C    //RX_RECVFUNC_MODE_0
-1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0004    //RX_SAMPLINGFREQ_SIG
-3    0x0004    //RX_SAMPLINGFREQ_PROC
-4    0x000A    //RX_FRAME_SZ
-5    0x0000    //RX_DELAY_OPT
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
-11    0x7B02    //RX_A_HP
-12    0x4000    //RX_B_PE
-13    0x7800    //RX_THR_PITCH_DET_0
-14    0x7000    //RX_THR_PITCH_DET_1
-15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0008    //RX_PITCH_BFR_LEN
-17    0x0003    //RX_SBD_PITCH_DET
-18    0x0100    //RX_PP_RESRV_0
-19    0x0020    //RX_PP_RESRV_1
-20    0x0500    //RX_N_SN_EST
-21    0x000C    //RX_N2_SN_EST
-22    0x000A    //RX_NS_LVL_CTRL
-23    0xF600    //RX_THR_SN_EST
-24    0x7000    //RX_LAMBDA_PFILT
-25    0x000A    //RX_FENS_RESRV_0
-26    0x0190    //RX_FENS_RESRV_1
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-30    0x0002    //RX_EXTRA_NS_L
-31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x199A    //RX_A_POST_FLT
-36    0x0000    //RX_LMT_THRD
-37    0x4000    //RX_LMT_ALPHA
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
-131    0x0000    //RX_MAXLEVEL_CNG
-132    0x3000    //RX_BWE_UV_TH
-133    0x3000    //RX_BWE_UV_TH2
-134    0x1800    //RX_BWE_UV_TH3
-135    0x1000    //RX_BWE_V_TH
-136    0x04CD    //RX_BWE_GAIN1_V_TH1
-137    0x0F33    //RX_BWE_GAIN1_V_TH2
-138    0x7333    //RX_BWE_UV_EQ
-139    0x199A    //RX_BWE_V_EQ
-140    0x7333    //RX_BWE_TONE_TH
-141    0x0004    //RX_BWE_UV_HOLD_T
-142    0x6CCD    //RX_BWE_GAIN2_ALPHA
-143    0x799A    //RX_BWE_GAIN3_ALPHA
-144    0x001E    //RX_BWE_CUTOFF
-145    0x3000    //RX_BWE_GAINFILL
-146    0x3200    //RX_BWE_MAXTH_TONE
-147    0x2000    //RX_BWE_EQ_0
-148    0x2000    //RX_BWE_EQ_1
-149    0x2000    //RX_BWE_EQ_2
-150    0x2000    //RX_BWE_EQ_3
-151    0x2000    //RX_BWE_EQ_4
-152    0x2000    //RX_BWE_EQ_5
-153    0x2000    //RX_BWE_EQ_6
-154    0x0000    //RX_BWE_RESRV_0
-155    0x0000    //RX_BWE_RESRV_1
-156    0x0000    //RX_BWE_RESRV_2
+#RX 2
+157    0x0024    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x000B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0013    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0021    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0036    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0037    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005B    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0099    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7FFF    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x1200    //RX_TDDRC_THRD_2
-115    0x1900    //RX_TDDRC_THRD_3
-116    0x3000    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0240    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0304    //RX_FDEQ_BIN_2
-66    0x0405    //RX_FDEQ_BIN_3
-67    0x0607    //RX_FDEQ_BIN_4
-68    0x0809    //RX_FDEQ_BIN_5
-69    0x0A0B    //RX_FDEQ_BIN_6
-70    0x0C0D    //RX_FDEQ_BIN_7
-71    0x0E0F    //RX_FDEQ_BIN_8
-72    0x1011    //RX_FDEQ_BIN_9
-73    0x1214    //RX_FDEQ_BIN_10
-74    0x1618    //RX_FDEQ_BIN_11
-75    0x1C1C    //RX_FDEQ_BIN_12
-76    0x2020    //RX_FDEQ_BIN_13
-77    0x2020    //RX_FDEQ_BIN_14
-78    0x2011    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0007    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x5333    //RX_FDDRC_SLANT_1_0
-107    0x5333    //RX_FDDRC_SLANT_1_1
-108    0x5333    //RX_FDDRC_SLANT_1_2
-109    0x5333    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_HCO-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -35256,7 +53597,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -35309,7 +53650,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -35318,12 +53659,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -35349,12 +53690,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -35370,10 +53711,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -35382,12 +53723,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -35434,7 +53775,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x003B    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -35446,11 +53787,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -35458,22 +53799,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -35581,16 +53922,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -35619,19 +53960,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -35956,16 +54297,81 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x027C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -35987,9 +54393,9 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
+24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
@@ -36004,16 +54410,16 @@
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x5252    //RX_FDEQ_GAIN_0
+40    0x4E4F    //RX_FDEQ_GAIN_1
+41    0x4743    //RX_FDEQ_GAIN_2
+42    0x454C    //RX_FDEQ_GAIN_3
+43    0x4C49    //RX_FDEQ_GAIN_4
+44    0x584A    //RX_FDEQ_GAIN_5
+45    0x4642    //RX_FDEQ_GAIN_6
+46    0x4043    //RX_FDEQ_GAIN_7
+47    0x454A    //RX_FDEQ_GAIN_8
+48    0x4C53    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36032,8 +54438,8 @@
 64    0x0203    //RX_FDEQ_BIN_1
 65    0x0303    //RX_FDEQ_BIN_2
 66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0107    //RX_FDEQ_BIN_5
 69    0x0708    //RX_FDEQ_BIN_6
 70    0x090A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
@@ -36089,12 +54495,12 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0016    //RX_SPK_VOL
+126    0x10D3    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -36123,9 +54529,9 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36133,30 +54539,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x05E3    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36172,15 +54578,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36219,12 +54625,12 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0016    //RX_SPK_VOL
+129    0x000C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36232,30 +54638,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36271,15 +54677,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36318,12 +54724,12 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0020    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36331,30 +54737,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x062A    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36370,15 +54776,114 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x0060    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x0600    //RX_FDDRC_THRD_2_0
+95    0x0600    //RX_FDDRC_THRD_2_1
+96    0x0600    //RX_FDDRC_THRD_2_2
+97    0x0600    //RX_FDDRC_THRD_2_3
+98    0x0800    //RX_FDDRC_THRD_3_0
+99    0x0800    //RX_FDDRC_THRD_3_1
+100    0x0800    //RX_FDDRC_THRD_3_2
+101    0x0800    //RX_FDDRC_THRD_3_3
+102    0x0000    //RX_FDDRC_SLANT_0_0
+103    0x0000    //RX_FDDRC_SLANT_0_1
+104    0x0000    //RX_FDDRC_SLANT_0_2
+105    0x0000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0607    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6054    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36419,109 +54924,10 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x002E    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-#VOL    3
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x4000    //RX_TDDRC_ALPHA_DWN_2
-29    0x4000    //RX_TDDRC_ALPHA_DWN_3
-32    0x4000    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
-38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0035    //RX_FDDRC_BAND_MARGIN_1
-91    0x0060    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x0600    //RX_FDDRC_THRD_2_0
-95    0x0600    //RX_FDDRC_THRD_2_1
-96    0x0600    //RX_FDDRC_THRD_2_2
-97    0x0600    //RX_FDDRC_THRD_2_3
-98    0x0800    //RX_FDDRC_THRD_3_0
-99    0x0800    //RX_FDDRC_THRD_3_1
-100    0x0800    //RX_FDDRC_THRD_3_2
-101    0x0800    //RX_FDDRC_THRD_3_3
-102    0x0000    //RX_FDDRC_SLANT_0_0
-103    0x0000    //RX_FDDRC_SLANT_0_1
-104    0x0000    //RX_FDDRC_SLANT_0_2
-105    0x0000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0041    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36529,30 +54935,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36568,15 +54974,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36615,12 +55021,12 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x005C    //RX_SPK_VOL
+129    0x004A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36628,30 +55034,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36667,15 +55073,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36714,12 +55120,12 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x008A    //RX_SPK_VOL
+129    0x0082    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x1000    //RX_TDDRC_ALPHA_UP_1
-7    0x1000    //RX_TDDRC_ALPHA_UP_2
-8    0x1000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x4000    //RX_TDDRC_ALPHA_DWN_2
@@ -36727,30 +55133,30 @@
 32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x1000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x0700    //RX_TDDRC_DRC_GAIN
+124    0x0618    //RX_TDDRC_DRC_GAIN
 38    0x0014    //RX_FDEQ_SUBNUM
-39    0x8080    //RX_FDEQ_GAIN_0
-40    0x8058    //RX_FDEQ_GAIN_1
-41    0x5454    //RX_FDEQ_GAIN_2
-42    0x545C    //RX_FDEQ_GAIN_3
-43    0x6448    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x5848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x485A    //RX_FDEQ_GAIN_8
-48    0x5A58    //RX_FDEQ_GAIN_9
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C64    //RX_FDEQ_GAIN_3
+43    0x6056    //RX_FDEQ_GAIN_4
+44    0x5A5A    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x484A    //RX_FDEQ_GAIN_7
+47    0x4E52    //RX_FDEQ_GAIN_8
+48    0x584E    //RX_FDEQ_GAIN_9
 49    0x4848    //RX_FDEQ_GAIN_10
 50    0x4848    //RX_FDEQ_GAIN_11
 51    0x4848    //RX_FDEQ_GAIN_12
@@ -36766,15 +55172,15 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0405    //RX_FDEQ_BIN_4
-68    0x0506    //RX_FDEQ_BIN_5
-69    0x0708    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D08    //RX_FDEQ_BIN_9
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0502    //RX_FDEQ_BIN_3
+67    0x0503    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x0A0A    //RX_FDEQ_BIN_7
+71    0x0A09    //RX_FDEQ_BIN_8
+72    0x0C13    //RX_FDEQ_BIN_9
 73    0x0000    //RX_FDEQ_BIN_10
 74    0x0000    //RX_FDEQ_BIN_11
 75    0x0000    //RX_FDEQ_BIN_12
@@ -36815,10 +55221,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0005    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0015    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x003C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0082    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0780    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x8080    //RX_FDEQ_GAIN_0
+197    0x8054    //RX_FDEQ_GAIN_1
+198    0x5050    //RX_FDEQ_GAIN_2
+199    0x5058    //RX_FDEQ_GAIN_3
+200    0x5C70    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x484C    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x485A    //RX_FDEQ_GAIN_8
+205    0x5A58    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0604    //RX_FDEQ_BIN_4
+225    0x0406    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x0060    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x0600    //RX_FDDRC_THRD_2_0
+252    0x0600    //RX_FDDRC_THRD_2_1
+253    0x0600    //RX_FDDRC_THRD_2_2
+254    0x0600    //RX_FDDRC_THRD_2_3
+255    0x0800    //RX_FDDRC_THRD_3_0
+256    0x0800    //RX_FDDRC_THRD_3_1
+257    0x0800    //RX_FDDRC_THRD_3_2
+258    0x0800    //RX_FDDRC_THRD_3_3
+259    0x0000    //RX_FDDRC_SLANT_0_0
+260    0x0000    //RX_FDDRC_SLANT_0_1
+261    0x0000    //RX_FDDRC_SLANT_0_2
+262    0x0000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_HCO-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -37009,7 +56267,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -37062,7 +56320,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -37071,12 +56329,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -37102,12 +56360,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -37123,10 +56381,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -37135,12 +56393,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -37187,7 +56445,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x0102    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -37199,11 +56457,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -37211,22 +56469,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -37334,16 +56592,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -37372,19 +56630,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -37709,23 +56967,88 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x027C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0001    //RX_SAMPLINGFREQ_SIG
 3    0x0001    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
 6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
 8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
@@ -37740,37 +57063,37 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
+24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x6868    //RX_FDEQ_GAIN_0
-40    0x6858    //RX_FDEQ_GAIN_1
-41    0x5858    //RX_FDEQ_GAIN_2
-42    0x5858    //RX_FDEQ_GAIN_3
-43    0x5C5C    //RX_FDEQ_GAIN_4
-44    0x5854    //RX_FDEQ_GAIN_5
-45    0x544C    //RX_FDEQ_GAIN_6
-46    0x4C4C    //RX_FDEQ_GAIN_7
-47    0x4C60    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+39    0x847A    //RX_FDEQ_GAIN_0
+40    0x6C66    //RX_FDEQ_GAIN_1
+41    0x6868    //RX_FDEQ_GAIN_2
+42    0x7084    //RX_FDEQ_GAIN_3
+43    0x7E82    //RX_FDEQ_GAIN_4
+44    0x7874    //RX_FDEQ_GAIN_5
+45    0x5864    //RX_FDEQ_GAIN_6
+46    0x625C    //RX_FDEQ_GAIN_7
+47    0x5C50    //RX_FDEQ_GAIN_8
+48    0x545A    //RX_FDEQ_GAIN_9
+49    0x5C58    //RX_FDEQ_GAIN_10
+50    0x5858    //RX_FDEQ_GAIN_11
+51    0x6460    //RX_FDEQ_GAIN_12
+52    0x5048    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -37781,20 +57104,20 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
+63    0x0401    //RX_FDEQ_BIN_0
+64    0x0104    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0202    //RX_FDEQ_BIN_3
+67    0x0704    //RX_FDEQ_BIN_4
+68    0x0605    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
 71    0x0B0C    //RX_FDEQ_BIN_8
 72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+73    0x1006    //RX_FDEQ_BIN_10
+74    0x1614    //RX_FDEQ_BIN_11
+75    0x1414    //RX_FDEQ_BIN_12
+76    0x1404    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -37829,12 +57152,12 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
 117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x6000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
@@ -37842,12 +57165,12 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x03FC    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0014    //RX_SPK_VOL
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -37876,44 +57199,44 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x0607    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x6868    //RX_FDEQ_GAIN_0
-40    0x6858    //RX_FDEQ_GAIN_1
-41    0x5858    //RX_FDEQ_GAIN_2
-42    0x5858    //RX_FDEQ_GAIN_3
-43    0x5C5C    //RX_FDEQ_GAIN_4
-44    0x5854    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
 45    0x544C    //RX_FDEQ_GAIN_6
-46    0x4C4C    //RX_FDEQ_GAIN_7
-47    0x4C60    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -37925,19 +57248,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -37972,47 +57295,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0014    //RX_SPK_VOL
+129    0x000B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x05D2    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x6868    //RX_FDEQ_GAIN_0
-40    0x6858    //RX_FDEQ_GAIN_1
-41    0x5858    //RX_FDEQ_GAIN_2
-42    0x5858    //RX_FDEQ_GAIN_3
-43    0x5C5C    //RX_FDEQ_GAIN_4
-44    0x5854    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
 45    0x544C    //RX_FDEQ_GAIN_6
-46    0x4C4C    //RX_FDEQ_GAIN_7
-47    0x4C60    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38024,19 +57347,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38071,47 +57394,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001A    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x05F5    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x6868    //RX_FDEQ_GAIN_0
-40    0x6858    //RX_FDEQ_GAIN_1
-41    0x5858    //RX_FDEQ_GAIN_2
-42    0x5858    //RX_FDEQ_GAIN_3
-43    0x5C5C    //RX_FDEQ_GAIN_4
-44    0x5854    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
 45    0x544C    //RX_FDEQ_GAIN_6
-46    0x4C4C    //RX_FDEQ_GAIN_7
-47    0x4C60    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38123,19 +57446,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38170,47 +57493,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0026    //RX_SPK_VOL
+129    0x001C    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x0607    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x6868    //RX_FDEQ_GAIN_0
-40    0x6858    //RX_FDEQ_GAIN_1
-41    0x5858    //RX_FDEQ_GAIN_2
-42    0x5858    //RX_FDEQ_GAIN_3
-43    0x5C5C    //RX_FDEQ_GAIN_4
-44    0x5854    //RX_FDEQ_GAIN_5
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5A59    //RX_FDEQ_GAIN_5
 45    0x544C    //RX_FDEQ_GAIN_6
-46    0x4C4C    //RX_FDEQ_GAIN_7
-47    0x4C60    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38222,19 +57545,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38269,47 +57592,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0035    //RX_SPK_VOL
+129    0x002D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x05F5    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x7878    //RX_FDEQ_GAIN_0
-40    0x786C    //RX_FDEQ_GAIN_1
-41    0x6C6C    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5A60    //RX_FDEQ_GAIN_4
-44    0x7A54    //RX_FDEQ_GAIN_5
-45    0x5448    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x585E    //RX_FDEQ_GAIN_7
+47    0x6274    //RX_FDEQ_GAIN_8
+48    0x7E76    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38321,19 +57644,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38368,47 +57691,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0058    //RX_SPK_VOL
+129    0x004B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x05F5    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x7878    //RX_FDEQ_GAIN_0
-40    0x786C    //RX_FDEQ_GAIN_1
-41    0x6C6C    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5A60    //RX_FDEQ_GAIN_4
-44    0x7A54    //RX_FDEQ_GAIN_5
-45    0x5448    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x5860    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x8076    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38420,19 +57743,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38467,47 +57790,47 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0085    //RX_SPK_VOL
+129    0x0084    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1C00    //RX_TDDRC_THRD_2
-115    0x1C00    //RX_TDDRC_THRD_3
-116    0x7FFF    //RX_TDDRC_SLANT_0
-117    0x7FFF    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x06AF    //RX_TDDRC_DRC_GAIN
+124    0x05F5    //RX_TDDRC_DRC_GAIN
 38    0x001C    //RX_FDEQ_SUBNUM
-39    0x7878    //RX_FDEQ_GAIN_0
-40    0x786C    //RX_FDEQ_GAIN_1
-41    0x6C6C    //RX_FDEQ_GAIN_2
-42    0x6262    //RX_FDEQ_GAIN_3
-43    0x5A60    //RX_FDEQ_GAIN_4
-44    0x7A54    //RX_FDEQ_GAIN_5
-45    0x5448    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x6068    //RX_FDEQ_GAIN_9
-49    0x7070    //RX_FDEQ_GAIN_10
-50    0x8070    //RX_FDEQ_GAIN_11
-51    0x6060    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x705A    //RX_FDEQ_GAIN_1
+41    0x5C68    //RX_FDEQ_GAIN_2
+42    0x6C67    //RX_FDEQ_GAIN_3
+43    0x6462    //RX_FDEQ_GAIN_4
+44    0x5C59    //RX_FDEQ_GAIN_5
+45    0x544C    //RX_FDEQ_GAIN_6
+46    0x5860    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x8076    //RX_FDEQ_GAIN_9
+49    0x8084    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x4C4C    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
 53    0x4848    //RX_FDEQ_GAIN_14
 54    0x4848    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
@@ -38519,19 +57842,19 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0204    //RX_FDEQ_BIN_5
-69    0x0A0A    //RX_FDEQ_BIN_6
-70    0x0A0A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x0E0F    //RX_FDEQ_BIN_10
-74    0x0F10    //RX_FDEQ_BIN_11
-75    0x1011    //RX_FDEQ_BIN_12
-76    0x1104    //RX_FDEQ_BIN_13
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0503    //RX_FDEQ_BIN_3
+67    0x0403    //RX_FDEQ_BIN_4
+68    0x0504    //RX_FDEQ_BIN_5
+69    0x0D04    //RX_FDEQ_BIN_6
+70    0x210A    //RX_FDEQ_BIN_7
+71    0x0E0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x0F23    //RX_FDEQ_BIN_13
 77    0x0000    //RX_FDEQ_BIN_14
 78    0x0000    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
@@ -38568,10 +57891,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0019    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0024    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x5C54    //RX_FDEQ_GAIN_5
+202    0x544C    //RX_FDEQ_GAIN_6
+203    0x4A48    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x6C6C    //RX_FDEQ_GAIN_10
+207    0x6C68    //RX_FDEQ_GAIN_11
+208    0x5A5A    //RX_FDEQ_GAIN_12
+209    0x5A5C    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0033    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0049    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6858    //RX_FDEQ_GAIN_1
+198    0x5858    //RX_FDEQ_GAIN_2
+199    0x5858    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1C00    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x7FFF    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0715    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x6868    //RX_FDEQ_GAIN_0
+197    0x6864    //RX_FDEQ_GAIN_1
+198    0x7070    //RX_FDEQ_GAIN_2
+199    0x6058    //RX_FDEQ_GAIN_3
+200    0x5C5C    //RX_FDEQ_GAIN_4
+201    0x8854    //RX_FDEQ_GAIN_5
+202    0x5448    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x6068    //RX_FDEQ_GAIN_9
+206    0x7070    //RX_FDEQ_GAIN_10
+207    0x8070    //RX_FDEQ_GAIN_11
+208    0x6060    //RX_FDEQ_GAIN_12
+209    0x7070    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0204    //RX_FDEQ_BIN_5
+226    0x0A0A    //RX_FDEQ_BIN_6
+227    0x0A0A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_HCO-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -38762,7 +58937,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -38815,7 +58990,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -38824,12 +58999,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -38855,12 +59030,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -38876,10 +59051,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -38888,12 +59063,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -38940,7 +59115,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x0383    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -38952,11 +59127,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -38964,22 +59139,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -39087,16 +59262,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -39125,19 +59300,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -39462,27 +59637,92 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x027C    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0003    //RX_SAMPLINGFREQ_SIG
 3    0x0003    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
 6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
 8    0x6000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 10    0x0800    //RX_PGA
-11    0x7652    //RX_A_HP
+11    0x7D83    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x7800    //RX_THR_PITCH_DET_0
 14    0x7000    //RX_THR_PITCH_DET_1
@@ -39493,39 +59733,39 @@
 19    0x0020    //RX_PP_RESRV_1
 20    0x0400    //RX_N_SN_EST
 21    0x000C    //RX_N2_SN_EST
-22    0x0010    //RX_NS_LVL_CTRL
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
+24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
 26    0x0190    //RX_FENS_RESRV_1
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
 28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
 30    0x0002    //RX_EXTRA_NS_L
 31    0x0800    //RX_EXTRA_NS_A
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -39534,22 +59774,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
 67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -39582,25 +59822,25 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0002    //RX_FILTINDX
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
 118    0x6000    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
+124    0x03FC    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x2000    //RX_MIN_G_FP
-128    0x0080    //RX_MAX_G_FP
-129    0x0019    //RX_SPK_VOL
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -39629,46 +59869,46 @@
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -39678,21 +59918,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -39725,49 +59965,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0019    //RX_SPK_VOL
+129    0x000A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -39777,21 +60017,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -39824,49 +60064,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0023    //RX_SPK_VOL
+129    0x0011    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -39876,21 +60116,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -39923,49 +60163,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0032    //RX_SPK_VOL
+129    0x001B    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -39975,21 +60215,120 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -40024,146 +60363,47 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0048    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-#VOL    4
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
-9    0x1000    //RX_TDDRC_ALPHA_UP_4
-27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
-33    0x7214    //RX_TDDRC_LIMITER_THRD
-34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
-119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
-120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x199A    //RX_TDDRC_HMNC_GAIN
-122    0x0001    //RX_TDDRC_SMT_FLAG
-123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
-55    0x4848    //RX_FDEQ_GAIN_16
-56    0x4848    //RX_FDEQ_GAIN_17
-57    0x4848    //RX_FDEQ_GAIN_18
-58    0x4848    //RX_FDEQ_GAIN_19
-59    0x4848    //RX_FDEQ_GAIN_20
-60    0x4848    //RX_FDEQ_GAIN_21
-61    0x4848    //RX_FDEQ_GAIN_22
-62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
-79    0x0000    //RX_FDEQ_BIN_16
-80    0x0000    //RX_FDEQ_BIN_17
-81    0x0000    //RX_FDEQ_BIN_18
-82    0x0000    //RX_FDEQ_BIN_19
-83    0x0000    //RX_FDEQ_BIN_20
-84    0x0000    //RX_FDEQ_BIN_21
-85    0x0000    //RX_FDEQ_BIN_22
-86    0x0000    //RX_FDEQ_BIN_23
-87    0x4000    //RX_FDEQ_RESRV_0
-88    0x0320    //RX_FDEQ_RESRV_1
-89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0035    //RX_FDDRC_BAND_MARGIN_1
-91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
-92    0x0120    //RX_FDDRC_BAND_MARGIN_3
-93    0x0004    //RX_FDDRC_BLOCK_EXP
-94    0x5000    //RX_FDDRC_THRD_2_0
-95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x2000    //RX_FDDRC_THRD_2_2
-97    0x5000    //RX_FDDRC_THRD_2_3
-98    0x6400    //RX_FDDRC_THRD_3_0
-99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x2000    //RX_FDDRC_THRD_3_2
-101    0x5000    //RX_FDDRC_THRD_3_3
-102    0x4000    //RX_FDDRC_SLANT_0_0
-103    0x4000    //RX_FDDRC_SLANT_0_1
-104    0x4000    //RX_FDDRC_SLANT_0_2
-105    0x4000    //RX_FDDRC_SLANT_0_3
-106    0x7FFF    //RX_FDDRC_SLANT_1_0
-107    0x7FFF    //RX_FDDRC_SLANT_1_1
-108    0x7FFF    //RX_FDDRC_SLANT_1_2
-109    0x7FFF    //RX_FDDRC_SLANT_1_3
-110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0068    //RX_SPK_VOL
-130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -40173,21 +60413,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -40220,49 +60460,49 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0097    //RX_SPK_VOL
+129    0x007E    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x6000    //RX_TDDRC_ALPHA_UP_1
-7    0x6000    //RX_TDDRC_ALPHA_UP_2
-8    0x6000    //RX_TDDRC_ALPHA_UP_3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
 9    0x1000    //RX_TDDRC_ALPHA_UP_4
 27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
-28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
-29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
-32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
 33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0002    //RX_TDDRC_THRD_0
-113    0x0004    //RX_TDDRC_THRD_1
-114    0x1A00    //RX_TDDRC_THRD_2
-115    0x1A00    //RX_TDDRC_THRD_3
-116    0x7EB8    //RX_TDDRC_SLANT_0
-117    0x2500    //RX_TDDRC_SLANT_1
-118    0x6000    //RX_TDDRC_ALPHA_UP_0
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
 119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x04BC    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x484E    //RX_FDEQ_GAIN_0
-40    0x4E4E    //RX_FDEQ_GAIN_1
-41    0x4E4E    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x484E    //RX_FDEQ_GAIN_4
-44    0x6E4E    //RX_FDEQ_GAIN_5
-45    0x4850    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4860    //RX_FDEQ_GAIN_8
-48    0x7468    //RX_FDEQ_GAIN_9
-49    0x6060    //RX_FDEQ_GAIN_10
-50    0x6666    //RX_FDEQ_GAIN_11
-51    0x6666    //RX_FDEQ_GAIN_12
-52    0x6666    //RX_FDEQ_GAIN_13
-53    0x6060    //RX_FDEQ_GAIN_14
-54    0x6060    //RX_FDEQ_GAIN_15
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -40272,21 +60512,21 @@
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
 63    0x0202    //RX_FDEQ_BIN_0
-64    0x0203    //RX_FDEQ_BIN_1
-65    0x0303    //RX_FDEQ_BIN_2
-66    0x0304    //RX_FDEQ_BIN_3
-67    0x0404    //RX_FDEQ_BIN_4
-68    0x0209    //RX_FDEQ_BIN_5
-69    0x0808    //RX_FDEQ_BIN_6
-70    0x090A    //RX_FDEQ_BIN_7
-71    0x0B0C    //RX_FDEQ_BIN_8
-72    0x0D0E    //RX_FDEQ_BIN_9
-73    0x1013    //RX_FDEQ_BIN_10
-74    0x1719    //RX_FDEQ_BIN_11
-75    0x1B1E    //RX_FDEQ_BIN_12
-76    0x1E1E    //RX_FDEQ_BIN_13
-77    0x1E28    //RX_FDEQ_BIN_14
-78    0x282C    //RX_FDEQ_BIN_15
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -40321,10 +60561,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1104    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x069B    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x06AF    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x069B    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0688    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0688    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0049    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x06AF    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5054    //RX_FDEQ_GAIN_1
+198    0x505C    //RX_FDEQ_GAIN_2
+199    0x5C60    //RX_FDEQ_GAIN_3
+200    0x5C62    //RX_FDEQ_GAIN_4
+201    0x5860    //RX_FDEQ_GAIN_5
+202    0x4C4E    //RX_FDEQ_GAIN_6
+203    0x6074    //RX_FDEQ_GAIN_7
+204    0x748A    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x9498    //RX_FDEQ_GAIN_10
+207    0x8678    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0080    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x064F    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x5858    //RX_FDEQ_GAIN_1
+198    0x5862    //RX_FDEQ_GAIN_2
+199    0x666A    //RX_FDEQ_GAIN_3
+200    0x6668    //RX_FDEQ_GAIN_4
+201    0x5C60    //RX_FDEQ_GAIN_5
+202    0x4C4C    //RX_FDEQ_GAIN_6
+203    0x5C72    //RX_FDEQ_GAIN_7
+204    0x6C80    //RX_FDEQ_GAIN_8
+205    0x8C8C    //RX_FDEQ_GAIN_9
+206    0x8C90    //RX_FDEQ_GAIN_10
+207    0x7E78    //RX_FDEQ_GAIN_11
+208    0x666E    //RX_FDEQ_GAIN_12
+209    0x5A48    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x6484    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x220E    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_HCO-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -40515,7 +61607,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -40568,7 +61660,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xF700    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -40577,12 +61669,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -40608,12 +61700,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -40629,10 +61721,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -40641,12 +61733,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -40693,7 +61785,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x04E8    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -40705,11 +61797,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -40717,22 +61809,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -40840,16 +61932,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -40878,19 +61970,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -41215,14 +62307,79 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x7000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
 0    0x006C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
@@ -41234,7 +62391,7 @@
 7    0x4000    //RX_TDDRC_ALPHA_UP_2
 8    0x4000    //RX_TDDRC_ALPHA_UP_3
 9    0x4000    //RX_TDDRC_ALPHA_UP_4
-10    0x0800    //RX_PGA
+10    0x065B    //RX_PGA
 11    0x7E56    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x7800    //RX_THR_PITCH_DET_0
@@ -41266,18 +62423,18 @@
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4850    //RX_FDEQ_GAIN_3
+42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41348,12 +62505,12 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
 126    0x2000    //RX_TPKA_FP
 127    0x2000    //RX_MIN_G_FP
 128    0x0080    //RX_MAX_G_FP
-129    0x0013    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 131    0x0000    //RX_MAXLEVEL_CNG
 132    0x3000    //RX_BWE_UV_TH
@@ -41404,23 +62561,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4850    //RX_FDEQ_GAIN_3
+42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41478,7 +62635,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0013    //RX_SPK_VOL
+129    0x0012    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41503,23 +62660,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4850    //RX_FDEQ_GAIN_3
+42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41577,7 +62734,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x001C    //RX_SPK_VOL
+129    0x001A    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41602,23 +62759,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4850    //RX_FDEQ_GAIN_3
+42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41676,7 +62833,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0028    //RX_SPK_VOL
+129    0x0025    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41701,23 +62858,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
 39    0x4848    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4850    //RX_FDEQ_GAIN_3
+42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41775,7 +62932,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0035    //RX_SPK_VOL
+129    0x0034    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41800,23 +62957,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4C4C    //RX_FDEQ_GAIN_0
-40    0x4C4C    //RX_FDEQ_GAIN_1
-41    0x4C48    //RX_FDEQ_GAIN_2
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
 42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41874,7 +63031,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0052    //RX_SPK_VOL
+129    0x004D    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41899,23 +63056,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4C4C    //RX_FDEQ_GAIN_0
-40    0x4C4C    //RX_FDEQ_GAIN_1
-41    0x4C48    //RX_FDEQ_GAIN_2
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
 42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -41973,7 +63130,7 @@
 108    0x7FFF    //RX_FDDRC_SLANT_1_2
 109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0078    //RX_SPK_VOL
+129    0x0074    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
 6    0x4000    //RX_TDDRC_ALPHA_UP_1
@@ -41998,23 +63155,23 @@
 121    0x199A    //RX_TDDRC_HMNC_GAIN
 122    0x0001    //RX_TDDRC_SMT_FLAG
 123    0x0CCD    //RX_TDDRC_SMT_W
-124    0x02D2    //RX_TDDRC_DRC_GAIN
+124    0x03C3    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4C4C    //RX_FDEQ_GAIN_0
-40    0x4C4C    //RX_FDEQ_GAIN_1
-41    0x4C48    //RX_FDEQ_GAIN_2
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
 42    0x4870    //RX_FDEQ_GAIN_3
 43    0x4848    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4568    //RX_FDEQ_GAIN_6
+45    0x4850    //RX_FDEQ_GAIN_6
 46    0x485C    //RX_FDEQ_GAIN_7
 47    0x5C60    //RX_FDEQ_GAIN_8
 48    0x685C    //RX_FDEQ_GAIN_9
-49    0x5648    //RX_FDEQ_GAIN_10
-50    0x484C    //RX_FDEQ_GAIN_11
-51    0x706C    //RX_FDEQ_GAIN_12
-52    0x7070    //RX_FDEQ_GAIN_13
-53    0x6868    //RX_FDEQ_GAIN_14
+49    0x5640    //RX_FDEQ_GAIN_10
+50    0x4040    //RX_FDEQ_GAIN_11
+51    0x5C58    //RX_FDEQ_GAIN_12
+52    0x5C60    //RX_FDEQ_GAIN_13
+53    0x6060    //RX_FDEQ_GAIN_14
 54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
@@ -42074,16 +63231,3538 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x006C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+167    0x065B    //RX_PGA
+168    0x7E56    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0014    //RX_NS_LVL_CTRL
+180    0xF400    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0012    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0025    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0034    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x004D    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0074    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x4000    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x4000    //RX_TDDRC_ALPHA_UP_3
+166    0x4000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0001    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x1800    //RX_TDDRC_THRD_2
+272    0x1800    //RX_TDDRC_THRD_3
+273    0x6000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x4000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03C3    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4870    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x485C    //RX_FDEQ_GAIN_7
+204    0x5C60    //RX_FDEQ_GAIN_8
+205    0x685C    //RX_FDEQ_GAIN_9
+206    0x5640    //RX_FDEQ_GAIN_10
+207    0x4040    //RX_FDEQ_GAIN_11
+208    0x5C58    //RX_FDEQ_GAIN_12
+209    0x5C60    //RX_FDEQ_GAIN_13
+210    0x6060    //RX_FDEQ_GAIN_14
+211    0x6060    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0402    //RX_FDEQ_BIN_3
+224    0x0504    //RX_FDEQ_BIN_4
+225    0x0209    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-TTY_HCO-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0000    //TX_PATCH_REG
+3    0x0200    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x0078    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0302    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0000    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0000    //TX_MICS_OF_PAIR0
+38    0x0000    //TX_MICS_OF_PAIR1
+39    0x0000    //TX_MICS_OF_PAIR2
+40    0x0000    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0003    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x0000    //TX_HD_BIN_MASK
+53    0x0000    //TX_HD_SUBAND_MASK
+54    0x0000    //TX_HD_FRAME_AVG_MASK
+55    0x0000    //TX_HD_MIN_FRQ
+56    0x0000    //TX_HD_ALPHA_PSD
+57    0x0000    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0x0000    //TX_T_PSDVAT
+63    0x0000    //TX_CNT
+64    0x0000    //TX_ANTI_HOWL_GAIN
+65    0x0000    //TX_MICFORBFMARK_0
+66    0x0000    //TX_MICFORBFMARK_1
+67    0x0000    //TX_MICFORBFMARK_2
+68    0x0000    //TX_MICFORBFMARK_3
+69    0x0000    //TX_MICFORBFMARK_4
+70    0x0000    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x0000    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x0000    //TX_ADCS_GAIN
+112    0x0000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x7FFF    //TX_BLMIC_BLKFACTOR
+116    0x7FFF    //TX_BRMIC_BLKFACTOR
+117    0x000A    //TX_MICBLK_START_BIN
+118    0x0041    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x0000    //TX_FE_ENER_TH_MTS
+124    0x0000    //TX_FE_ENER_TH_EXP
+125    0x0000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x0000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0020    //TX_MIC_BLOCK_N
+128    0x7652    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x7800    //TX_THR_PITCH_DET_0
+131    0x7000    //TX_THR_PITCH_DET_1
+132    0x6000    //TX_THR_PITCH_DET_2
+133    0x0000    //TX_PITCH_BFR_LEN
+134    0x0000    //TX_SBD_PITCH_DET
+135    0x0000    //TX_TD_AEC_L
+136    0x0000    //TX_MU0_UNP_TD_AEC
+137    0x0000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x2000    //TX_AEC_REF_GAIN_0
+148    0x2000    //TX_AEC_REF_GAIN_1
+149    0x2000    //TX_AEC_REF_GAIN_2
+150    0x4000    //TX_EAD_THR
+151    0x0200    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0100    //TX_MIN_EQ_RE_EST_3
+156    0x0100    //TX_MIN_EQ_RE_EST_4
+157    0x0100    //TX_MIN_EQ_RE_EST_5
+158    0x0100    //TX_MIN_EQ_RE_EST_6
+159    0x0100    //TX_MIN_EQ_RE_EST_7
+160    0x0100    //TX_MIN_EQ_RE_EST_8
+161    0x0100    //TX_MIN_EQ_RE_EST_9
+162    0x0100    //TX_MIN_EQ_RE_EST_10
+163    0x0100    //TX_MIN_EQ_RE_EST_11
+164    0x0100    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x0000    //TX_LAMBDA_CB_NLE
+167    0x0000    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0008    //TX_SE_HOLD_N
+170    0x0050    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x0000    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x0000    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0000    //TX_FRQ_LIN_LEN
+184    0x0000    //TX_FRQ_AEC_LEN_RHO
+185    0x0000    //TX_MU0_UNP_FRQ_AEC
+186    0x0000    //TX_MU0_PTD_FRQ_AEC
+187    0x0000    //TX_MINENOISETH
+188    0x0000    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x0000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7333    //TX_DTD_THR1_0
+198    0x7333    //TX_DTD_THR1_1
+199    0x7333    //TX_DTD_THR1_2
+200    0x7333    //TX_DTD_THR1_3
+201    0x7333    //TX_DTD_THR1_4
+202    0x7333    //TX_DTD_THR1_5
+203    0x7333    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0400    //TX_DT_CUT_K
+214    0x0000    //TX_DT_CUT_THR
+215    0x0000    //TX_COMFORT_G
+216    0x0000    //TX_POWER_YOUT_TH
+217    0x0000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x0800    //TX_B_POST_FILT_ECHO_H
+230    0x0000    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x0000    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0000    //TX_DT_RESRV_7
+240    0x0000    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF800    //TX_THR_SN_EST_2
+245    0xF600    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0A00    //TX_N_SN_EST
+267    0x0000    //TX_INBEAM_T
+268    0x0000    //TX_INBEAMHOLDT
+269    0x1FFF    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x0000    //TX_B_POST_FLT_0
+280    0x0000    //TX_B_POST_FLT_1
+281    0x001A    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0014    //TX_NS_LVL_CTRL_2
+284    0x000C    //TX_NS_LVL_CTRL_3
+285    0x000C    //TX_NS_LVL_CTRL_4
+286    0x000C    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x000C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0014    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0014    //TX_MIN_GAIN_S_3
+293    0x0014    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x0014    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x0000    //TX_NMOS_SUP
+298    0x0064    //TX_NS_MAX_PRI_SNR_TH
+299    0x7FFF    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x1200    //TX_THR_LFNS
+309    0x0147    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x7FFF    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x7FFF    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x1000    //TX_A_POST_FILT_S_2
+317    0x6666    //TX_A_POST_FILT_S_3
+318    0x6666    //TX_A_POST_FILT_S_4
+319    0x6666    //TX_A_POST_FILT_S_5
+320    0x199A    //TX_A_POST_FILT_S_6
+321    0x6666    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x2000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7E00    //TX_LAMBDA_PFILT
+339    0x7E00    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7E00    //TX_LAMBDA_PFILT_S_4
+344    0x7E00    //TX_LAMBDA_PFILT_S_5
+345    0x7E00    //TX_LAMBDA_PFILT_S_6
+346    0x7E00    //TX_LAMBDA_PFILT_S_7
+347    0x0010    //TX_K_PEPPER
+348    0x0400    //TX_A_PEPPER
+349    0x0000    //TX_K_PEPPER_HF
+350    0x0000    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0000    //TX_DT_BINVAD_TH_0
+354    0x0000    //TX_DT_BINVAD_TH_1
+355    0x0000    //TX_DT_BINVAD_TH_2
+356    0x0000    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0001    //TX_BF_SGRAD_FLG
+362    0x0000    //TX_BF_DVG_TH
+363    0x0000    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x05A0    //TX_NDETCT
+367    0x0383    //TX_NOISE_TH_0
+368    0x1388    //TX_NOISE_TH_0_2
+369    0x3A98    //TX_NOISE_TH_0_3
+370    0x0C80    //TX_NOISE_TH_1
+371    0x0032    //TX_NOISE_TH_2
+372    0x3D54    //TX_NOISE_TH_3
+373    0x012C    //TX_NOISE_TH_4
+374    0x07D0    //TX_NOISE_TH_5
+375    0x6590    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x00C8    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
+385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x6400    //TX_OUT_ENER_S_TH_NOISY
+387    0x6400    //TX_OUT_ENER_TH_NOISE
+388    0x7D00    //TX_OUT_ENER_TH_SPEECH
+389    0x0000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0000    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0000    //TX_MIN_G_LOW300HZ
+401    0x0010    //TX_MAXLEVEL_CNG
+402    0x0000    //TX_STN_NOISE_TH
+403    0x0000    //TX_POST_MASK_SUP
+404    0x0000    //TX_POST_MASK_ADJUST
+405    0x0014    //TX_NS_ENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
+407    0x0226    //TX_MINENOISE_MIC0_S_TH
+408    0x2879    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x2000    //TX_RHO_UPB
+415    0x0020    //TX_N_HOLD_HS
+416    0x0009    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0000    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x0219    //TX_THR_STD_PLH
+421    0x09C4    //TX_N_HOLD_STD
+422    0x0166    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0800    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x0000    //TX_SB_RTO_MEAN_TH_RUB
+428    0x2000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0064    //TX_DESIRED_TALK_HOLDT
+431    0x1000    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0000    //TX_HS_VAD_BIN
+435    0x0000    //TX_THR_VAD_HS
+436    0x0000    //TX_MEAN_RTO_MIN_TH2
+437    0x0000    //TX_SILENCE_T
+438    0x4000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x001E    //TX_DOA_VAD_THR_1
+445    0x001E    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x00B4    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x005A    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x00B4    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x005A    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x00B4    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x005A    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0172    //TX_BF_HOLDOFF_T
+473    0x8000    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x071C    //TX_DOA_TRACK_HT
+477    0x0280    //TX_N1_HOLD_HF
+478    0x0140    //TX_N2_HOLD_HF
+479    0x2AAB    //TX_BF_RESET_THR_HF
+480    0x4000    //TX_DOA_SMOOTH
+481    0x0000    //TX_MU_BF
+482    0x0200    //TX_BF_MU_LF_B2
+483    0x0000    //TX_BF_FC_END_BIN_B2
+484    0x0000    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0000    //TX_N_DOA_SEED
+488    0x0000    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x0000    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x0000    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x0000    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0168    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0004    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0230    //TX_NOR_OFF_TH1
+503    0xD333    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x6666    //TX_MICTOBFGAIN0
+513    0x0014    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x0000    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0028    //TX_SNR_THR
+531    0x03E8    //TX_ENGY_THR
+532    0x0000    //TX_CORR_HIGH_TH
+533    0x0000    //TX_ENGY_THR_2
+534    0x0000    //TX_MEAN_RTO_THR
+535    0x0000    //TX_WNS_ENOISE_MIC0_TH
+536    0x0000    //TX_RATIOMICL_TH
+537    0x0000    //TX_CALIG_HS
+538    0x000A    //TX_LVL_CTRL
+539    0x0000    //TX_WIND_SUPRTO
+540    0x0000    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x0000    //TX_RATIOMICH_TH
+543    0x0000    //TX_WIND_INBEAM_L_TH
+544    0x0000    //TX_WIND_INBEAM_H_TH
+545    0x0000    //TX_WNS_RESRV_0
+546    0x0000    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0000    //TX_FDEQ_BIN_0
+592    0x0000    //TX_FDEQ_BIN_1
+593    0x0000    //TX_FDEQ_BIN_2
+594    0x0000    //TX_FDEQ_BIN_3
+595    0x0000    //TX_FDEQ_BIN_4
+596    0x0000    //TX_FDEQ_BIN_5
+597    0x0000    //TX_FDEQ_BIN_6
+598    0x0000    //TX_FDEQ_BIN_7
+599    0x0000    //TX_FDEQ_BIN_8
+600    0x0000    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0000    //TX_PREEQ_BIN_MIC0_0
+642    0x0000    //TX_PREEQ_BIN_MIC0_1
+643    0x0000    //TX_PREEQ_BIN_MIC0_2
+644    0x0000    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0000    //TX_PREEQ_BIN_MIC1_0
+691    0x0000    //TX_PREEQ_BIN_MIC1_1
+692    0x0000    //TX_PREEQ_BIN_MIC1_2
+693    0x0000    //TX_PREEQ_BIN_MIC1_3
+694    0x0000    //TX_PREEQ_BIN_MIC1_4
+695    0x0000    //TX_PREEQ_BIN_MIC1_5
+696    0x0000    //TX_PREEQ_BIN_MIC1_6
+697    0x0000    //TX_PREEQ_BIN_MIC1_7
+698    0x0000    //TX_PREEQ_BIN_MIC1_8
+699    0x0000    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0000    //TX_PREEQ_BIN_MIC2_0
+740    0x0000    //TX_PREEQ_BIN_MIC2_1
+741    0x0000    //TX_PREEQ_BIN_MIC2_2
+742    0x0000    //TX_PREEQ_BIN_MIC2_3
+743    0x0000    //TX_PREEQ_BIN_MIC2_4
+744    0x0000    //TX_PREEQ_BIN_MIC2_5
+745    0x0000    //TX_PREEQ_BIN_MIC2_6
+746    0x0000    //TX_PREEQ_BIN_MIC2_7
+747    0x0000    //TX_PREEQ_BIN_MIC2_8
+748    0x0000    //TX_PREEQ_BIN_MIC2_9
+749    0x0000    //TX_PREEQ_BIN_MIC2_10
+750    0x0000    //TX_PREEQ_BIN_MIC2_11
+751    0x0000    //TX_PREEQ_BIN_MIC2_12
+752    0x0000    //TX_PREEQ_BIN_MIC2_13
+753    0x0000    //TX_PREEQ_BIN_MIC2_14
+754    0x0000    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0064    //TX_MIC_CALIBRATION_0
+766    0x006A    //TX_MIC_CALIBRATION_1
+767    0x006A    //TX_MIC_CALIBRATION_2
+768    0x006B    //TX_MIC_CALIBRATION_3
+769    0x0048    //TX_MIC_PWR_BIAS_0
+770    0x003C    //TX_MIC_PWR_BIAS_1
+771    0x003C    //TX_MIC_PWR_BIAS_2
+772    0x003C    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0009    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F3D    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7FB0    //TX_TDDRC_ALPHA_DWN_01
+788    0x7FB0    //TX_TDDRC_ALPHA_DWN_02
+789    0x7FB0    //TX_TDDRC_ALPHA_DWN_03
+790    0x7FB0    //TX_TDDRC_ALPHA_DWN_04
+791    0x65AD    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0002    //TX_DEADMIC_SILENCE_TH
+817    0x0147    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x0000    //TX_KS_NOISEPASTE_FACTOR
+824    0x0000    //TX_KS_CONFIG
+825    0x0000    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0000    //TX_FFP_FP_K_METAL
+834    0x0000    //TX_A_POST_FLT_FP
+835    0x0000    //TX_RTO_OUTBEAM_TH
+836    0x0000    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0000    //TX_FFP_RESRV_2
+849    0x0000    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x0E80    //TX_TDDRC_THRD_2
+857    0x3800    //TX_TDDRC_THRD_3
+858    0x2A00    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7FB0    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x0000    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0000    //TX_TDDRC_SMT_W
+866    0x0100    //TX_TDDRC_DRC_GAIN
+867    0x0000    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x1EB8    //TX_TFMASKLTH
+870    0x170A    //TX_TFMASKLTHL
+871    0x7FFF    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x4000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x0000    //TX_FASTNS_OUTIN_TH
+884    0x0000    //TX_FASTNS_TFMASK_TH
+885    0x0000    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x047C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x1134    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0CAD    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0662    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000A    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0011    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x001B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05D2    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x002C    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05E3    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x545E    //RX_FDEQ_GAIN_7
+47    0x6476    //RX_FDEQ_GAIN_8
+48    0x7C78    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C6E    //RX_FDEQ_GAIN_11
+51    0x606C    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0B18    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0048    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x007E    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+7    0x4000    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x4000    //RX_TDDRC_ALPHA_DWN_2
+29    0x4000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0008    //RX_TDDRC_THRD_1
+114    0x0160    //RX_TDDRC_THRD_2
+115    0x2A00    //RX_TDDRC_THRD_3
+116    0x0500    //RX_TDDRC_SLANT_0
+117    0x5000    //RX_TDDRC_SLANT_1
+118    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x05F5    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x7070    //RX_FDEQ_GAIN_0
+40    0x6258    //RX_FDEQ_GAIN_1
+41    0x5860    //RX_FDEQ_GAIN_2
+42    0x6464    //RX_FDEQ_GAIN_3
+43    0x5C5A    //RX_FDEQ_GAIN_4
+44    0x6054    //RX_FDEQ_GAIN_5
+45    0x4C54    //RX_FDEQ_GAIN_6
+46    0x5464    //RX_FDEQ_GAIN_7
+47    0x6C7E    //RX_FDEQ_GAIN_8
+48    0x847E    //RX_FDEQ_GAIN_9
+49    0x8286    //RX_FDEQ_GAIN_10
+50    0x7C7A    //RX_FDEQ_GAIN_11
+51    0x6C78    //RX_FDEQ_GAIN_12
+52    0x5448    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4884    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0306    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0604    //RX_FDEQ_BIN_5
+69    0x0A19    //RX_FDEQ_BIN_6
+70    0x0914    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x047C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7D83    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x847C    //RX_FDEQ_GAIN_0
+197    0x5A56    //RX_FDEQ_GAIN_1
+198    0x6266    //RX_FDEQ_GAIN_2
+199    0x6E7A    //RX_FDEQ_GAIN_3
+200    0x8678    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x706E    //RX_FDEQ_GAIN_6
+203    0x6C64    //RX_FDEQ_GAIN_7
+204    0x5C6A    //RX_FDEQ_GAIN_8
+205    0x6268    //RX_FDEQ_GAIN_9
+206    0x6462    //RX_FDEQ_GAIN_10
+207    0x646E    //RX_FDEQ_GAIN_11
+208    0x6860    //RX_FDEQ_GAIN_12
+209    0x646A    //RX_FDEQ_GAIN_13
+210    0x7478    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0105    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0004    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x0CE0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03FC    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x1134    //RX_TPKA_FP
+284    0x0400    //RX_MIN_G_FP
+285    0x0CAD    //RX_MAX_G_FP
+286    0x0058    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0662    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000A    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0011    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x001B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05D2    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x002C    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05E3    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C50    //RX_FDEQ_GAIN_6
+203    0x545E    //RX_FDEQ_GAIN_7
+204    0x6476    //RX_FDEQ_GAIN_8
+205    0x7C78    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C6E    //RX_FDEQ_GAIN_11
+208    0x606C    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0B18    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0048    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x007E    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x7EB8    //RX_TDDRC_ALPHA_UP_1
+164    0x4000    //RX_TDDRC_ALPHA_UP_2
+165    0x2000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x4000    //RX_TDDRC_ALPHA_DWN_2
+186    0x4000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0008    //RX_TDDRC_THRD_1
+271    0x0160    //RX_TDDRC_THRD_2
+272    0x2A00    //RX_TDDRC_THRD_3
+273    0x0500    //RX_TDDRC_SLANT_0
+274    0x5000    //RX_TDDRC_SLANT_1
+275    0x7EB8    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x05F5    //RX_TDDRC_DRC_GAIN
+195    0x0025    //RX_FDEQ_SUBNUM
+196    0x7070    //RX_FDEQ_GAIN_0
+197    0x6258    //RX_FDEQ_GAIN_1
+198    0x5860    //RX_FDEQ_GAIN_2
+199    0x6464    //RX_FDEQ_GAIN_3
+200    0x5C5A    //RX_FDEQ_GAIN_4
+201    0x6054    //RX_FDEQ_GAIN_5
+202    0x4C54    //RX_FDEQ_GAIN_6
+203    0x5464    //RX_FDEQ_GAIN_7
+204    0x6C7E    //RX_FDEQ_GAIN_8
+205    0x847E    //RX_FDEQ_GAIN_9
+206    0x8286    //RX_FDEQ_GAIN_10
+207    0x7C7A    //RX_FDEQ_GAIN_11
+208    0x6C78    //RX_FDEQ_GAIN_12
+209    0x5448    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4884    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0102    //RX_FDEQ_BIN_1
+222    0x0306    //RX_FDEQ_BIN_2
+223    0x0505    //RX_FDEQ_BIN_3
+224    0x0203    //RX_FDEQ_BIN_4
+225    0x0604    //RX_FDEQ_BIN_5
+226    0x0A19    //RX_FDEQ_BIN_6
+227    0x0914    //RX_FDEQ_BIN_7
+228    0x0A0A    //RX_FDEQ_BIN_8
+229    0x0A0A    //RX_FDEQ_BIN_9
+230    0x0A0A    //RX_FDEQ_BIN_10
+231    0x0A0A    //RX_FDEQ_BIN_11
+232    0x0A0A    //RX_FDEQ_BIN_12
+233    0x1E1A    //RX_FDEQ_BIN_13
+234    0x0F37    //RX_FDEQ_BIN_14
+235    0x5360    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_VCO-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0000    //TX_SAMPLINGFREQ_SIG
 7    0x0000    //TX_SAMPLINGFREQ_PROC
@@ -42100,8 +66779,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -42229,7 +66908,7 @@
 147    0x0100    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7500    //TX_EAD_THR
+150    0x7E00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
 153    0x0200    //TX_MIN_EQ_RE_EST_1
@@ -42244,13 +66923,13 @@
 162    0x4000    //TX_MIN_EQ_RE_EST_10
 163    0x6000    //TX_MIN_EQ_RE_EST_11
 164    0x7FFF    //TX_MIN_EQ_RE_EST_12
-165    0x2000    //TX_LAMBDA_RE_EST
+165    0x4000    //TX_LAMBDA_RE_EST
 166    0x0000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x2000    //TX_GAIN_NP
 169    0x0180    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0080    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -42276,10 +66955,10 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
-200    0x7FF0    //TX_DTD_THR1_3
+197    0x7FF0    //TX_DTD_THR1_0
+198    0x79E0    //TX_DTD_THR1_1
+199    0x6D60    //TX_DTD_THR1_2
+200    0x73A0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
@@ -42292,7 +66971,7 @@
 210    0x0CCD    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x157C    //TX_DT_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
 214    0x0100    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
@@ -42302,18 +66981,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x1000    //TX_ADPT_STRICT_L
 222    0x1000    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
 224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+225    0x028A    //TX_RATIO_DT_L_TH_HIGH
 226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x0800    //TX_B_POST_FILT_ECHO_L
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x1000    //TX_B_POST_FILT_ECHO_L
 229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+234    0x01F4    //TX_RATIO_DT_L0_TH_HIGH
 235    0x3A98    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -42330,12 +67009,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0050    //TX_DELTA_THR_SN_EST_0
-251    0x01A0    //TX_DELTA_THR_SN_EST_1
+251    0x0200    //TX_DELTA_THR_SN_EST_1
 252    0x0200    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
-254    0x0100    //TX_DELTA_THR_SN_EST_4
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x01A0    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -42361,31 +67040,31 @@
 279    0x1000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x0012    //TX_NS_LVL_CTRL_1
-283    0x0017    //TX_NS_LVL_CTRL_2
-284    0x0015    //TX_NS_LVL_CTRL_3
+282    0x0017    //TX_NS_LVL_CTRL_1
+283    0x001A    //TX_NS_LVL_CTRL_2
+284    0x0012    //TX_NS_LVL_CTRL_3
 285    0x0012    //TX_NS_LVL_CTRL_4
-286    0x0012    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0012    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
-290    0x000F    //TX_MIN_GAIN_S_1
-291    0x000D    //TX_MIN_GAIN_S_2
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000F    //TX_MIN_GAIN_S_2
 292    0x000F    //TX_MIN_GAIN_S_3
 293    0x000F    //TX_MIN_GAIN_S_4
-294    0x000F    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
+294    0x0010    //TX_MIN_GAIN_S_5
+295    0x000F    //TX_MIN_GAIN_S_6
 296    0x000F    //TX_MIN_GAIN_S_7
-297    0x4000    //TX_NMOS_SUP
+297    0x3C00    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x4000    //TX_SNRI_SUP_1
-302    0x1000    //TX_SNRI_SUP_2
+301    0x1000    //TX_SNRI_SUP_1
+302    0x3000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
-304    0x2400    //TX_SNRI_SUP_4
+304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x3000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -42394,19 +67073,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x5000    //TX_A_POST_FILT_S_1
-316    0x2000    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x1000    //TX_A_POST_FILT_S_4
-319    0x3000    //TX_A_POST_FILT_S_5
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x1000    //TX_A_POST_FILT_S_2
+317    0x1000    //TX_A_POST_FILT_S_3
+318    0x3000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
 320    0x5000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x1000    //TX_B_POST_FILT_0
 323    0x1000    //TX_B_POST_FILT_1
 324    0x1000    //TX_B_POST_FILT_2
-325    0x1000    //TX_B_POST_FILT_3
-326    0x5000    //TX_B_POST_FILT_4
-327    0x3000    //TX_B_POST_FILT_5
+325    0x3000    //TX_B_POST_FILT_3
+326    0x3000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -42419,12 +67098,12 @@
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7E00    //TX_LAMBDA_PFILT
 339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7900    //TX_LAMBDA_PFILT_S_1
-341    0x7400    //TX_LAMBDA_PFILT_S_2
-342    0x7900    //TX_LAMBDA_PFILT_S_3
-343    0x7000    //TX_LAMBDA_PFILT_S_4
+340    0x7400    //TX_LAMBDA_PFILT_S_1
+341    0x7D00    //TX_LAMBDA_PFILT_S_2
+342    0x7000    //TX_LAMBDA_PFILT_S_3
+343    0x7D00    //TX_LAMBDA_PFILT_S_4
 344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
+345    0x7900    //TX_LAMBDA_PFILT_S_6
 346    0x7D00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
 348    0x0800    //TX_A_PEPPER
@@ -42436,7 +67115,7 @@
 354    0x0800    //TX_DT_BINVAD_TH_1
 355    0x0800    //TX_DT_BINVAD_TH_2
 356    0x0800    //TX_DT_BINVAD_TH_3
-357    0x0FA0    //TX_DT_BINVAD_ENDF
+357    0x0BB8    //TX_DT_BINVAD_ENDF
 358    0x0400    //TX_C_POST_FLT_DT
 359    0x4000    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0100    //TX_DT_BOOST
@@ -42446,23 +67125,23 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x0064    //TX_NDETCT
-367    0x0050    //TX_NOISE_TH_0
+367    0x0019    //TX_NOISE_TH_0
 368    0x7FFF    //TX_NOISE_TH_0_2
 369    0x7FFF    //TX_NOISE_TH_0_3
-370    0x07D0    //TX_NOISE_TH_1
+370    0x1388    //TX_NOISE_TH_1
 371    0x03ED    //TX_NOISE_TH_2
-372    0x2EE0    //TX_NOISE_TH_3
-373    0x5528    //TX_NOISE_TH_4
+372    0x59D8    //TX_NOISE_TH_3
+373    0x61A8    //TX_NOISE_TH_4
 374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
-378    0x0FA0    //TX_NOISE_TH_6
+378    0x4650    //TX_NOISE_TH_6
 379    0x000A    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -42470,17 +67149,17 @@
 388    0x1000    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7000    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -42588,21 +67267,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -42631,31 +67310,31 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0014    //TX_FDEQ_SUBNUM
-567    0x5858    //TX_FDEQ_GAIN_0
-568    0x5850    //TX_FDEQ_GAIN_1
-569    0x5050    //TX_FDEQ_GAIN_2
-570    0x5048    //TX_FDEQ_GAIN_3
-571    0x3C48    //TX_FDEQ_GAIN_4
-572    0x3C48    //TX_FDEQ_GAIN_5
-573    0x4848    //TX_FDEQ_GAIN_6
-574    0x4842    //TX_FDEQ_GAIN_7
-575    0x3030    //TX_FDEQ_GAIN_8
-576    0x3030    //TX_FDEQ_GAIN_9
+567    0x5854    //TX_FDEQ_GAIN_0
+568    0x4C48    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4A43    //TX_FDEQ_GAIN_3
+571    0x374B    //TX_FDEQ_GAIN_4
+572    0x3444    //TX_FDEQ_GAIN_5
+573    0x433C    //TX_FDEQ_GAIN_6
+574    0x3436    //TX_FDEQ_GAIN_7
+575    0x2C2E    //TX_FDEQ_GAIN_8
+576    0x3234    //TX_FDEQ_GAIN_9
 577    0x4848    //TX_FDEQ_GAIN_10
 578    0x4848    //TX_FDEQ_GAIN_11
 579    0x4848    //TX_FDEQ_GAIN_12
@@ -42676,10 +67355,10 @@
 594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
+597    0x0906    //TX_FDEQ_BIN_6
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
-600    0x0D08    //TX_FDEQ_BIN_9
+600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x0000    //TX_FDEQ_BIN_10
 602    0x0000    //TX_FDEQ_BIN_11
 603    0x0000    //TX_FDEQ_BIN_12
@@ -42703,9 +67382,9 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4B4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
 627    0x4848    //TX_PREEQ_GAIN_MIC0_10
 628    0x4848    //TX_PREEQ_GAIN_MIC0_11
 629    0x4848    //TX_PREEQ_GAIN_MIC0_12
@@ -42729,7 +67408,7 @@
 647    0x0708    //TX_PREEQ_BIN_MIC0_6
 648    0x090A    //TX_PREEQ_BIN_MIC0_7
 649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D08    //TX_PREEQ_BIN_MIC0_9
+650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0000    //TX_PREEQ_BIN_MIC0_10
 652    0x0000    //TX_PREEQ_BIN_MIC0_11
 653    0x0000    //TX_PREEQ_BIN_MIC0_12
@@ -42752,9 +67431,9 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+673    0x4A4A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4B4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4D4E    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
 678    0x4848    //TX_PREEQ_GAIN_MIC1_12
@@ -42769,16 +67448,16 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C08    //TX_PREEQ_BIN_MIC1_2
-693    0x0700    //TX_PREEQ_BIN_MIC1_3
-694    0x0000    //TX_PREEQ_BIN_MIC1_4
-695    0x0000    //TX_PREEQ_BIN_MIC1_5
-696    0x0000    //TX_PREEQ_BIN_MIC1_6
-697    0x0000    //TX_PREEQ_BIN_MIC1_7
-698    0x0000    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
 700    0x0000    //TX_PREEQ_BIN_MIC1_10
 701    0x0000    //TX_PREEQ_BIN_MIC1_11
 702    0x0000    //TX_PREEQ_BIN_MIC1_12
@@ -42800,10 +67479,10 @@
 718    0x4848    //TX_PREEQ_GAIN_MIC2_3
 719    0x4848    //TX_PREEQ_GAIN_MIC2_4
 720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+721    0x484A    //TX_PREEQ_GAIN_MIC2_6
+722    0x4B4B    //TX_PREEQ_GAIN_MIC2_7
+723    0x4B4C    //TX_PREEQ_GAIN_MIC2_8
+724    0x4D50    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
 727    0x4848    //TX_PREEQ_GAIN_MIC2_12
@@ -42818,16 +67497,16 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x7800    //TX_PREEQ_BIN_MIC2_0
-740    0x0000    //TX_PREEQ_BIN_MIC2_1
-741    0x0000    //TX_PREEQ_BIN_MIC2_2
-742    0x0000    //TX_PREEQ_BIN_MIC2_3
-743    0x0000    //TX_PREEQ_BIN_MIC2_4
-744    0x0000    //TX_PREEQ_BIN_MIC2_5
-745    0x0000    //TX_PREEQ_BIN_MIC2_6
-746    0x0000    //TX_PREEQ_BIN_MIC2_7
-747    0x0000    //TX_PREEQ_BIN_MIC2_8
-748    0x0000    //TX_PREEQ_BIN_MIC2_9
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0708    //TX_PREEQ_BIN_MIC2_6
+746    0x090A    //TX_PREEQ_BIN_MIC2_7
+747    0x0B0C    //TX_PREEQ_BIN_MIC2_8
+748    0x0D0E    //TX_PREEQ_BIN_MIC2_9
 749    0x0000    //TX_PREEQ_BIN_MIC2_10
 750    0x0000    //TX_PREEQ_BIN_MIC2_11
 751    0x0000    //TX_PREEQ_BIN_MIC2_12
@@ -42844,16 +67523,16 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0065    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0065    //TX_MIC_CALIBRATION_2
-768    0x0065    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0044    //TX_MIC_PWR_BIAS_0
 770    0x0044    //TX_MIC_PWR_BIAS_1
 771    0x0044    //TX_MIC_PWR_BIAS_2
 772    0x0044    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
 776    0x000F    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
@@ -42862,15 +67541,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x4000    //TX_TDDRC_ALPHA_UP_01
-784    0x4000    //TX_TDDRC_ALPHA_UP_02
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x6000    //TX_TDDRC_ALPHA_UP_02
 785    0x4000    //TX_TDDRC_ALPHA_UP_03
-786    0x4000    //TX_TDDRC_ALPHA_UP_04
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
 787    0x6000    //TX_TDDRC_ALPHA_DWN_01
-788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
-789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+788    0x6000    //TX_TDDRC_ALPHA_DWN_02
+789    0x4000    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -42895,8 +67574,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -42935,17 +67614,17 @@
 853    0x0002    //TX_FILTINDX
 854    0x0004    //TX_TDDRC_THRD_0
 855    0x0010    //TX_TDDRC_THRD_1
-856    0x1800    //TX_TDDRC_THRD_2
+856    0x1000    //TX_TDDRC_THRD_2
 857    0x1800    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x4000    //TX_TDDRC_ALPHA_UP_00
+860    0x7EB8    //TX_TDDRC_ALPHA_UP_00
 861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0C60    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -42970,14 +67649,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x1000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0320    //TX_MICMUTE_RATIO_THR
+900    0x0217    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7E90    //TX_DTD_THR1_MICMUTE_0
+912    0x7918    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xCD38    //TX_AMS_RESRV_02
+945    0x2710    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -43827,16 +68571,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_VCO-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x0073    //TX_PATCH_REG
+3    0x6F79    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0001    //TX_SAMPLINGFREQ_SIG
 7    0x0001    //TX_SAMPLINGFREQ_PROC
@@ -43853,8 +69449,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -43982,28 +69578,28 @@
 147    0x0300    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x6800    //TX_EAD_THR
+150    0x6C00    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x0200    //TX_MIN_EQ_RE_EST_0
-153    0x0100    //TX_MIN_EQ_RE_EST_1
-154    0x0200    //TX_MIN_EQ_RE_EST_2
-155    0x0200    //TX_MIN_EQ_RE_EST_3
-156    0x0200    //TX_MIN_EQ_RE_EST_4
-157    0x0200    //TX_MIN_EQ_RE_EST_5
-158    0x0200    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
-160    0x1000    //TX_MIN_EQ_RE_EST_8
-161    0x1000    //TX_MIN_EQ_RE_EST_9
-162    0x1000    //TX_MIN_EQ_RE_EST_10
-163    0x1000    //TX_MIN_EQ_RE_EST_11
-164    0x1000    //TX_MIN_EQ_RE_EST_12
+153    0x2000    //TX_MIN_EQ_RE_EST_1
+154    0x2000    //TX_MIN_EQ_RE_EST_2
+155    0x2000    //TX_MIN_EQ_RE_EST_3
+156    0x2000    //TX_MIN_EQ_RE_EST_4
+157    0x2000    //TX_MIN_EQ_RE_EST_5
+158    0x4000    //TX_MIN_EQ_RE_EST_6
+159    0x4000    //TX_MIN_EQ_RE_EST_7
+160    0x4000    //TX_MIN_EQ_RE_EST_8
+161    0x4000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x4000    //TX_MIN_EQ_RE_EST_11
+164    0x4000    //TX_MIN_EQ_RE_EST_12
 165    0x4000    //TX_LAMBDA_RE_EST
 166    0x4000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x5000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
-170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+169    0x02A0    //TX_SE_HOLD_N
+170    0x0060    //TX_DT_HOLD_N
+171    0x00C0    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -44029,9 +69625,9 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x6590    //TX_DTD_THR1_0
-198    0x6590    //TX_DTD_THR1_1
-199    0x6590    //TX_DTD_THR1_2
+197    0x79E0    //TX_DTD_THR1_0
+198    0x7C38    //TX_DTD_THR1_1
+199    0x7FF0    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
 202    0x7FF0    //TX_DTD_THR1_5
@@ -44045,8 +69641,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x07D0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
+213    0x0FA0    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -44055,18 +69651,18 @@
 220    0x0000    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1770    //TX_RATIO_DT_L_TH_HIGH
-226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x0A98    //TX_RATIO_DT_H_TH_LOW
+225    0x0320    //TX_RATIO_DT_L_TH_HIGH
+226    0x1388    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x6000    //TX_B_POST_FILT_ECHO_L
 229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+234    0x012C    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -44083,11 +69679,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -44115,11 +69711,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -44137,8 +69733,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -44147,19 +69743,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -44167,14 +69763,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -44186,11 +69782,11 @@
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0200    //TX_DT_BINVAD_TH_0
-354    0x0200    //TX_DT_BINVAD_TH_1
-355    0x0200    //TX_DT_BINVAD_TH_2
-356    0x0200    //TX_DT_BINVAD_TH_3
-357    0x1D4C    //TX_DT_BINVAD_ENDF
-358    0x0800    //TX_C_POST_FLT_DT
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x0BB8    //TX_DT_BINVAD_ENDF
+358    0x2000    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
 360    0x0140    //TX_DT_BOOST
 361    0x0000    //TX_BF_SGRAD_FLG
@@ -44212,10 +69808,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0F0A    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -44223,17 +69819,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x7FFF    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0005    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -44341,21 +69937,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -44384,35 +69980,35 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
-566    0x001C    //TX_FDEQ_SUBNUM
-567    0x5050    //TX_FDEQ_GAIN_0
-568    0x5048    //TX_FDEQ_GAIN_1
-569    0x4848    //TX_FDEQ_GAIN_2
-570    0x4848    //TX_FDEQ_GAIN_3
-571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4850    //TX_FDEQ_GAIN_5
-573    0x5050    //TX_FDEQ_GAIN_6
-574    0x5048    //TX_FDEQ_GAIN_7
-575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4844    //TX_FDEQ_GAIN_9
-577    0x3C36    //TX_FDEQ_GAIN_10
-578    0x3A3A    //TX_FDEQ_GAIN_11
-579    0x4848    //TX_FDEQ_GAIN_12
-580    0x4848    //TX_FDEQ_GAIN_13
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x5048    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4A4F    //TX_FDEQ_GAIN_2
+570    0x4E48    //TX_FDEQ_GAIN_3
+571    0x4444    //TX_FDEQ_GAIN_4
+572    0x4450    //TX_FDEQ_GAIN_5
+573    0x5452    //TX_FDEQ_GAIN_6
+574    0x4E4C    //TX_FDEQ_GAIN_7
+575    0x4A4C    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4850    //TX_FDEQ_GAIN_10
+578    0x5454    //TX_FDEQ_GAIN_11
+579    0x5454    //TX_FDEQ_GAIN_12
+580    0x5454    //TX_FDEQ_GAIN_13
 581    0x4848    //TX_FDEQ_GAIN_14
 582    0x4848    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
@@ -44433,10 +70029,10 @@
 598    0x090A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
 600    0x0D0E    //TX_FDEQ_BIN_9
-601    0x0E0F    //TX_FDEQ_BIN_10
-602    0x0F10    //TX_FDEQ_BIN_11
-603    0x1011    //TX_FDEQ_BIN_12
-604    0x1104    //TX_FDEQ_BIN_13
+601    0x0F10    //TX_FDEQ_BIN_10
+602    0x1011    //TX_FDEQ_BIN_11
+603    0x1112    //TX_FDEQ_BIN_12
+604    0x120B    //TX_FDEQ_BIN_13
 605    0x0000    //TX_FDEQ_BIN_14
 606    0x0000    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
@@ -44456,13 +70052,13 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x5E64    //TX_PREEQ_GAIN_MIC0_12
-630    0x6464    //TX_PREEQ_GAIN_MIC0_13
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
 631    0x4848    //TX_PREEQ_GAIN_MIC0_14
 632    0x4848    //TX_PREEQ_GAIN_MIC0_15
 633    0x4848    //TX_PREEQ_GAIN_MIC0_16
@@ -44485,8 +70081,8 @@
 650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
 651    0x0F10    //TX_PREEQ_BIN_MIC0_10
 652    0x1011    //TX_PREEQ_BIN_MIC0_11
-653    0x1104    //TX_PREEQ_BIN_MIC0_12
-654    0x1010    //TX_PREEQ_BIN_MIC0_13
+653    0x1112    //TX_PREEQ_BIN_MIC0_12
+654    0x120B    //TX_PREEQ_BIN_MIC0_13
 655    0x0000    //TX_PREEQ_BIN_MIC0_14
 656    0x0000    //TX_PREEQ_BIN_MIC0_15
 657    0x0000    //TX_PREEQ_BIN_MIC0_16
@@ -44505,13 +70101,13 @@
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
 672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+673    0x484A    //TX_PREEQ_GAIN_MIC1_7
+674    0x4A4B    //TX_PREEQ_GAIN_MIC1_8
+675    0x4C4E    //TX_PREEQ_GAIN_MIC1_9
+676    0x4E4F    //TX_PREEQ_GAIN_MIC1_10
+677    0x5052    //TX_PREEQ_GAIN_MIC1_11
+678    0x5454    //TX_PREEQ_GAIN_MIC1_12
+679    0x5454    //TX_PREEQ_GAIN_MIC1_13
 680    0x4848    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
@@ -44522,20 +70118,20 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x0700    //TX_PREEQ_BIN_MIC1_8
-699    0x0000    //TX_PREEQ_BIN_MIC1_9
-700    0x0000    //TX_PREEQ_BIN_MIC1_10
-701    0x0000    //TX_PREEQ_BIN_MIC1_11
-702    0x0000    //TX_PREEQ_BIN_MIC1_12
-703    0x0000    //TX_PREEQ_BIN_MIC1_13
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0708    //TX_PREEQ_BIN_MIC1_6
+697    0x090A    //TX_PREEQ_BIN_MIC1_7
+698    0x0B0C    //TX_PREEQ_BIN_MIC1_8
+699    0x0D0E    //TX_PREEQ_BIN_MIC1_9
+700    0x0F10    //TX_PREEQ_BIN_MIC1_10
+701    0x1011    //TX_PREEQ_BIN_MIC1_11
+702    0x1112    //TX_PREEQ_BIN_MIC1_12
+703    0x120B    //TX_PREEQ_BIN_MIC1_13
 704    0x0000    //TX_PREEQ_BIN_MIC1_14
 705    0x0000    //TX_PREEQ_BIN_MIC1_15
 706    0x0000    //TX_PREEQ_BIN_MIC1_16
@@ -44550,19 +70146,19 @@
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
-718    0x4848    //TX_PREEQ_GAIN_MIC2_3
-719    0x4848    //TX_PREEQ_GAIN_MIC2_4
-720    0x4848    //TX_PREEQ_GAIN_MIC2_5
-721    0x4848    //TX_PREEQ_GAIN_MIC2_6
-722    0x4848    //TX_PREEQ_GAIN_MIC2_7
-723    0x4848    //TX_PREEQ_GAIN_MIC2_8
-724    0x4848    //TX_PREEQ_GAIN_MIC2_9
-725    0x4848    //TX_PREEQ_GAIN_MIC2_10
-726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+718    0x484A    //TX_PREEQ_GAIN_MIC2_3
+719    0x4B4A    //TX_PREEQ_GAIN_MIC2_4
+720    0x4B4C    //TX_PREEQ_GAIN_MIC2_5
+721    0x4C4D    //TX_PREEQ_GAIN_MIC2_6
+722    0x4F50    //TX_PREEQ_GAIN_MIC2_7
+723    0x5050    //TX_PREEQ_GAIN_MIC2_8
+724    0x5051    //TX_PREEQ_GAIN_MIC2_9
+725    0x5252    //TX_PREEQ_GAIN_MIC2_10
+726    0x5253    //TX_PREEQ_GAIN_MIC2_11
+727    0x5454    //TX_PREEQ_GAIN_MIC2_12
+728    0x5454    //TX_PREEQ_GAIN_MIC2_13
+729    0x5455    //TX_PREEQ_GAIN_MIC2_14
+730    0x5555    //TX_PREEQ_GAIN_MIC2_15
 731    0x4848    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
@@ -44586,7 +70182,7 @@
 751    0x0808    //TX_PREEQ_BIN_MIC2_12
 752    0x0808    //TX_PREEQ_BIN_MIC2_13
 753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0x0200    //TX_PREEQ_BIN_MIC2_15
+754    0x0808    //TX_PREEQ_BIN_MIC2_15
 755    0x0000    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
@@ -44597,33 +70193,33 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0062    //TX_MIC_CALIBRATION_0
-766    0x0062    //TX_MIC_CALIBRATION_1
-767    0x0062    //TX_MIC_CALIBRATION_2
-768    0x0062    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
 770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
-773    0x0009    //TX_GAIN_LIMIT_0
-774    0x000F    //TX_GAIN_LIMIT_1
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0003    //TX_GAIN_LIMIT_1
 775    0x000F    //TX_GAIN_LIMIT_2
-776    0x000F    //TX_GAIN_LIMIT_3
+776    0x0009    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
 779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0800    //TX_TDDRC_ALPHA_UP_01
-784    0x0800    //TX_TDDRC_ALPHA_UP_02
-785    0x0800    //TX_TDDRC_ALPHA_UP_03
-786    0x0800    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
 788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
 789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -44648,8 +70244,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -44686,19 +70282,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0002    //TX_TDDRC_THRD_1
-856    0x1800    //TX_TDDRC_THRD_2
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
 857    0x1800    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x0800    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0BE3    //TX_TDDRC_DRC_GAIN
+866    0x0F23    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -44723,14 +70319,79 @@
 888    0x0028    //TX_FASTNS_ARSPC_TH
 889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x1000    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0384    //TX_MICMUTE_RATIO_THR
+900    0x0230    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0C00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7DC8    //TX_DTD_THR1_MICMUTE_0
+912    0x733C    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0100    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0100    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xD8F0    //TX_AMS_RESRV_02
+945    0x2EE0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -45580,16 +71241,868 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_VCO-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
-2    0x0033    //TX_PATCH_REG
-3    0x2F7C    //TX_SENDFUNC_MODE_0
-4    0x0001    //TX_SENDFUNC_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
 5    0x0003    //TX_NUM_MIC
 6    0x0003    //TX_SAMPLINGFREQ_SIG
 7    0x0003    //TX_SAMPLINGFREQ_PROC
@@ -45606,8 +72119,8 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
@@ -45735,28 +72248,28 @@
 147    0x0400    //TX_AEC_REF_GAIN_0
 148    0x0800    //TX_AEC_REF_GAIN_1
 149    0x0800    //TX_AEC_REF_GAIN_2
-150    0x7600    //TX_EAD_THR
+150    0x7000    //TX_EAD_THR
 151    0x1000    //TX_THR_RE_EST
 152    0x2000    //TX_MIN_EQ_RE_EST_0
 153    0x0600    //TX_MIN_EQ_RE_EST_1
 154    0x3000    //TX_MIN_EQ_RE_EST_2
-155    0x3000    //TX_MIN_EQ_RE_EST_3
+155    0x6000    //TX_MIN_EQ_RE_EST_3
 156    0x3000    //TX_MIN_EQ_RE_EST_4
 157    0x3000    //TX_MIN_EQ_RE_EST_5
 158    0x3000    //TX_MIN_EQ_RE_EST_6
-159    0x1000    //TX_MIN_EQ_RE_EST_7
+159    0x3000    //TX_MIN_EQ_RE_EST_7
 160    0x7800    //TX_MIN_EQ_RE_EST_8
 161    0x7800    //TX_MIN_EQ_RE_EST_9
 162    0x7800    //TX_MIN_EQ_RE_EST_10
 163    0x7800    //TX_MIN_EQ_RE_EST_11
 164    0x7800    //TX_MIN_EQ_RE_EST_12
-165    0x4000    //TX_LAMBDA_RE_EST
+165    0x3000    //TX_LAMBDA_RE_EST
 166    0x3000    //TX_LAMBDA_CB_NLE
 167    0x7FFF    //TX_C_POST_FLT
 168    0x4000    //TX_GAIN_NP
-169    0x0180    //TX_SE_HOLD_N
+169    0x0260    //TX_SE_HOLD_N
 170    0x00C8    //TX_DT_HOLD_N
-171    0x05DC    //TX_DT2_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
 172    0x6666    //TX_AEC_RESRV_0
 173    0x0000    //TX_AEC_RESRV_1
 174    0x0014    //TX_AEC_RESRV_2
@@ -45782,12 +72295,12 @@
 194    0x0000    //TX_NORMENERTH
 195    0x0000    //TX_NORMENERHIGHTH
 196    0x0000    //TX_NORMENERHIGHTHL
-197    0x7FF0    //TX_DTD_THR1_0
+197    0x7080    //TX_DTD_THR1_0
 198    0x7FF0    //TX_DTD_THR1_1
-199    0x7FF0    //TX_DTD_THR1_2
+199    0x7C38    //TX_DTD_THR1_2
 200    0x7FF0    //TX_DTD_THR1_3
 201    0x7FF0    //TX_DTD_THR1_4
-202    0x7FF0    //TX_DTD_THR1_5
+202    0x7D00    //TX_DTD_THR1_5
 203    0x7FF0    //TX_DTD_THR1_6
 204    0x7E00    //TX_DTD_THR2_0
 205    0x7E00    //TX_DTD_THR2_1
@@ -45798,8 +72311,8 @@
 210    0x5000    //TX_DTD_THR2_6
 211    0x7FFF    //TX_DTD_THR3
 212    0x0000    //TX_SPK_CUT_K
-213    0x36B0    //TX_DT_CUT_K
-214    0x0100    //TX_DT_CUT_THR
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
 215    0x04EB    //TX_COMFORT_G
 216    0x01F4    //TX_POWER_YOUT_TH
 217    0x4000    //TX_FDPFGAINECHO
@@ -45808,18 +72321,18 @@
 220    0x7FFF    //TX_DTD_MIC_BLK
 221    0x023E    //TX_ADPT_STRICT_L
 222    0x023E    //TX_ADPT_STRICT_H
-223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
-224    0x3A98    //TX_RATIO_DT_H_TH_LOW
-225    0x1F40    //TX_RATIO_DT_L_TH_HIGH
-226    0x6590    //TX_RATIO_DT_H_TH_HIGH
-227    0x09C4    //TX_RATIO_DT_L0_TH
-228    0x2000    //TX_B_POST_FILT_ECHO_L
-229    0x1000    //TX_B_POST_FILT_ECHO_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
 232    0x0000    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
-234    0x2328    //TX_RATIO_DT_L0_TH_HIGH
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
 235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
 236    0x7FFF    //TX_MIN_EQ_RE_EST_13
 237    0x0000    //TX_DTD_THR1_7
@@ -45828,7 +72341,7 @@
 240    0x0800    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
 242    0xF800    //TX_THR_SN_EST_0
-243    0xFA00    //TX_THR_SN_EST_1
+243    0xFB00    //TX_THR_SN_EST_1
 244    0xFA00    //TX_THR_SN_EST_2
 245    0xFA00    //TX_THR_SN_EST_3
 246    0xF800    //TX_THR_SN_EST_4
@@ -45836,12 +72349,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0100    //TX_DELTA_THR_SN_EST_1
+251    0x0120    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
 253    0x0100    //TX_DELTA_THR_SN_EST_3
-254    0x0000    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -45867,52 +72380,52 @@
 279    0x2000    //TX_B_POST_FLT_0
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
-282    0x003C    //TX_NS_LVL_CTRL_1
-283    0x003C    //TX_NS_LVL_CTRL_2
-284    0x0024    //TX_NS_LVL_CTRL_3
-285    0x003C    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
-289    0x000F    //TX_MIN_GAIN_S_0
-290    0x0010    //TX_MIN_GAIN_S_1
-291    0x0010    //TX_MIN_GAIN_S_2
-292    0x0010    //TX_MIN_GAIN_S_3
-293    0x0010    //TX_MIN_GAIN_S_4
-294    0x0010    //TX_MIN_GAIN_S_5
-295    0x0010    //TX_MIN_GAIN_S_6
-296    0x000F    //TX_MIN_GAIN_S_7
-297    0x6000    //TX_NMOS_SUP
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
 298    0x0000    //TX_NS_MAX_PRI_SNR_TH
 299    0x0000    //TX_NMOS_SUP_MENSA
 300    0x7FFF    //TX_SNRI_SUP_0
-301    0x1400    //TX_SNRI_SUP_1
-302    0x1400    //TX_SNRI_SUP_2
-303    0x1400    //TX_SNRI_SUP_3
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
-307    0x7FFF    //TX_SNRI_SUP_7
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
 310    0x09C4    //TX_GAIN0_NTH
 311    0x000A    //TX_MUSIC_MORENS
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
-314    0x5000    //TX_A_POST_FILT_S_0
-315    0x7C00    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
-321    0x7000    //TX_A_POST_FILT_S_7
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x6000    //TX_B_POST_FILT_1
 324    0x6000    //TX_B_POST_FILT_2
 325    0x6000    //TX_B_POST_FILT_3
-326    0x6000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -45920,28 +72433,28 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
-338    0x7C00    //TX_LAMBDA_PFILT
-339    0x7D00    //TX_LAMBDA_PFILT_S_0
-340    0x7D00    //TX_LAMBDA_PFILT_S_1
-341    0x7D00    //TX_LAMBDA_PFILT_S_2
-342    0x7D00    //TX_LAMBDA_PFILT_S_3
-343    0x7D00    //TX_LAMBDA_PFILT_S_4
-344    0x7D00    //TX_LAMBDA_PFILT_S_5
-345    0x7D00    //TX_LAMBDA_PFILT_S_6
-346    0x7D00    //TX_LAMBDA_PFILT_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
 347    0x0200    //TX_K_PEPPER
-348    0x0400    //TX_A_PEPPER
+348    0x0800    //TX_A_PEPPER
 349    0x1EAA    //TX_K_PEPPER_HF
 350    0x0600    //TX_A_PEPPER_HF
 351    0x0001    //TX_HMNC_BST_FLG
 352    0x0200    //TX_HMNC_BST_THR
 353    0x0040    //TX_DT_BINVAD_TH_0
-354    0x0040    //TX_DT_BINVAD_TH_1
-355    0x0100    //TX_DT_BINVAD_TH_2
-356    0x0100    //TX_DT_BINVAD_TH_3
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
 357    0x36B0    //TX_DT_BINVAD_ENDF
 358    0x0200    //TX_C_POST_FLT_DT
 359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
@@ -45959,16 +72472,16 @@
 371    0x01F4    //TX_NOISE_TH_2
 372    0x36B0    //TX_NOISE_TH_3
 373    0x2710    //TX_NOISE_TH_4
-374    0x2CEC    //TX_NOISE_TH_5
+374    0x7FFF    //TX_NOISE_TH_5
 375    0x7FFF    //TX_NOISE_TH_5_2
 376    0x0000    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x0DAC    //TX_NOISE_TH_6
 379    0x0050    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -45976,17 +72489,17 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
-401    0x0001    //TX_MAXLEVEL_CNG
+401    0x0004    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
 403    0x4000    //TX_POST_MASK_SUP
 404    0x7FFF    //TX_POST_MASK_ADJUST
@@ -46094,21 +72607,21 @@
 506    0x2000    //TX_RADIODTLV
 507    0x0320    //TX_POWER_LINEIN_TH
 508    0x0014    //TX_FE_VADCOUNT_TH_FC
-509    0x0000    //TX_ECHO_SUPP_FC
+509    0x000A    //TX_ECHO_SUPP_FC
 510    0x0C80    //TX_ECHO_TH
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -46137,37 +72650,37 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
-568    0x4848    //TX_FDEQ_GAIN_1
-569    0x4850    //TX_FDEQ_GAIN_2
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
 570    0x5050    //TX_FDEQ_GAIN_3
 571    0x4848    //TX_FDEQ_GAIN_4
-572    0x484A    //TX_FDEQ_GAIN_5
-573    0x4E5E    //TX_FDEQ_GAIN_6
-574    0x5C4C    //TX_FDEQ_GAIN_7
-575    0x4C4E    //TX_FDEQ_GAIN_8
-576    0x4844    //TX_FDEQ_GAIN_9
-577    0x4448    //TX_FDEQ_GAIN_10
-578    0x4850    //TX_FDEQ_GAIN_11
-579    0x5C6A    //TX_FDEQ_GAIN_12
-580    0x5A84    //TX_FDEQ_GAIN_13
-581    0x7880    //TX_FDEQ_GAIN_14
-582    0x7F7F    //TX_FDEQ_GAIN_15
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
 584    0x4848    //TX_FDEQ_GAIN_17
 585    0x4848    //TX_FDEQ_GAIN_18
@@ -46182,16 +72695,16 @@
 594    0x0304    //TX_FDEQ_BIN_3
 595    0x0405    //TX_FDEQ_BIN_4
 596    0x0506    //TX_FDEQ_BIN_5
-597    0x0708    //TX_FDEQ_BIN_6
-598    0x090A    //TX_FDEQ_BIN_7
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
 599    0x0B0C    //TX_FDEQ_BIN_8
 600    0x0D0E    //TX_FDEQ_BIN_9
 601    0x1013    //TX_FDEQ_BIN_10
-602    0x1719    //TX_FDEQ_BIN_11
-603    0x1B1E    //TX_FDEQ_BIN_12
-604    0x1E1E    //TX_FDEQ_BIN_13
-605    0x1E28    //TX_FDEQ_BIN_14
-606    0x282C    //TX_FDEQ_BIN_15
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
 607    0x0000    //TX_FDEQ_BIN_16
 608    0x0000    //TX_FDEQ_BIN_17
 609    0x0000    //TX_FDEQ_BIN_18
@@ -46201,7 +72714,7 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
@@ -46209,16 +72722,16 @@
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
 623    0x4848    //TX_PREEQ_GAIN_MIC0_6
-624    0x484A    //TX_PREEQ_GAIN_MIC0_7
-625    0x4C4E    //TX_PREEQ_GAIN_MIC0_8
-626    0x5054    //TX_PREEQ_GAIN_MIC0_9
-627    0x5658    //TX_PREEQ_GAIN_MIC0_10
-628    0x5C5C    //TX_PREEQ_GAIN_MIC0_11
-629    0x6474    //TX_PREEQ_GAIN_MIC0_12
-630    0x7870    //TX_PREEQ_GAIN_MIC0_13
-631    0x5C48    //TX_PREEQ_GAIN_MIC0_14
-632    0x383C    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -46232,17 +72745,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x090A    //TX_PREEQ_BIN_MIC0_7
-649    0x0B0C    //TX_PREEQ_BIN_MIC0_8
-650    0x0D0E    //TX_PREEQ_BIN_MIC0_9
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
-652    0x1719    //TX_PREEQ_BIN_MIC0_11
-653    0x1B1E    //TX_PREEQ_BIN_MIC0_12
-654    0x1E1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x282C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -46250,7 +72763,7 @@
 662    0x0000    //TX_PREEQ_BIN_MIC0_21
 663    0x0000    //TX_PREEQ_BIN_MIC0_22
 664    0x0000    //TX_PREEQ_BIN_MIC0_23
-665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
 666    0x4848    //TX_PREEQ_GAIN_MIC1_0
 667    0x4848    //TX_PREEQ_GAIN_MIC1_1
 668    0x4848    //TX_PREEQ_GAIN_MIC1_2
@@ -46263,11 +72776,11 @@
 675    0x4848    //TX_PREEQ_GAIN_MIC1_9
 676    0x4848    //TX_PREEQ_GAIN_MIC1_10
 677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
-681    0x4848    //TX_PREEQ_GAIN_MIC1_15
-682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
 684    0x4848    //TX_PREEQ_GAIN_MIC1_18
 685    0x4848    //TX_PREEQ_GAIN_MIC1_19
@@ -46275,23 +72788,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x251A    //TX_PREEQ_BIN_MIC1_0
-691    0x0F0F    //TX_PREEQ_BIN_MIC1_1
-692    0x0C0C    //TX_PREEQ_BIN_MIC1_2
-693    0x0C0F    //TX_PREEQ_BIN_MIC1_3
-694    0x0F0F    //TX_PREEQ_BIN_MIC1_4
-695    0x0F09    //TX_PREEQ_BIN_MIC1_5
-696    0x0909    //TX_PREEQ_BIN_MIC1_6
-697    0x0908    //TX_PREEQ_BIN_MIC1_7
-698    0x070F    //TX_PREEQ_BIN_MIC1_8
-699    0x1F08    //TX_PREEQ_BIN_MIC1_9
-700    0x0808    //TX_PREEQ_BIN_MIC1_10
-701    0x0920    //TX_PREEQ_BIN_MIC1_11
-702    0x2020    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x0000    //TX_PREEQ_BIN_MIC1_14
-705    0x0000    //TX_PREEQ_BIN_MIC1_15
-706    0x0000    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -46299,7 +72812,7 @@
 711    0x0000    //TX_PREEQ_BIN_MIC1_21
 712    0x0000    //TX_PREEQ_BIN_MIC1_22
 713    0x0000    //TX_PREEQ_BIN_MIC1_23
-714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
 715    0x4848    //TX_PREEQ_GAIN_MIC2_0
 716    0x4848    //TX_PREEQ_GAIN_MIC2_1
 717    0x4848    //TX_PREEQ_GAIN_MIC2_2
@@ -46312,11 +72825,11 @@
 724    0x4848    //TX_PREEQ_GAIN_MIC2_9
 725    0x4848    //TX_PREEQ_GAIN_MIC2_10
 726    0x4848    //TX_PREEQ_GAIN_MIC2_11
-727    0x4848    //TX_PREEQ_GAIN_MIC2_12
-728    0x4848    //TX_PREEQ_GAIN_MIC2_13
-729    0x4848    //TX_PREEQ_GAIN_MIC2_14
-730    0x4848    //TX_PREEQ_GAIN_MIC2_15
-731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
 732    0x4848    //TX_PREEQ_GAIN_MIC2_17
 733    0x4848    //TX_PREEQ_GAIN_MIC2_18
 734    0x4848    //TX_PREEQ_GAIN_MIC2_19
@@ -46324,23 +72837,23 @@
 736    0x4848    //TX_PREEQ_GAIN_MIC2_21
 737    0x4848    //TX_PREEQ_GAIN_MIC2_22
 738    0x4848    //TX_PREEQ_GAIN_MIC2_23
-739    0x0608    //TX_PREEQ_BIN_MIC2_0
-740    0x0808    //TX_PREEQ_BIN_MIC2_1
-741    0x0808    //TX_PREEQ_BIN_MIC2_2
-742    0x0808    //TX_PREEQ_BIN_MIC2_3
-743    0x0808    //TX_PREEQ_BIN_MIC2_4
-744    0x0808    //TX_PREEQ_BIN_MIC2_5
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
 745    0x0808    //TX_PREEQ_BIN_MIC2_6
-746    0x0808    //TX_PREEQ_BIN_MIC2_7
-747    0x0808    //TX_PREEQ_BIN_MIC2_8
-748    0x0808    //TX_PREEQ_BIN_MIC2_9
-749    0x0808    //TX_PREEQ_BIN_MIC2_10
-750    0x0808    //TX_PREEQ_BIN_MIC2_11
-751    0x0808    //TX_PREEQ_BIN_MIC2_12
-752    0x0808    //TX_PREEQ_BIN_MIC2_13
-753    0x0808    //TX_PREEQ_BIN_MIC2_14
-754    0xF200    //TX_PREEQ_BIN_MIC2_15
-755    0x0000    //TX_PREEQ_BIN_MIC2_16
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
 756    0x0000    //TX_PREEQ_BIN_MIC2_17
 757    0x0000    //TX_PREEQ_BIN_MIC2_18
 758    0x0000    //TX_PREEQ_BIN_MIC2_19
@@ -46350,17 +72863,17 @@
 762    0x0000    //TX_PREEQ_BIN_MIC2_23
 763    0x0006    //TX_MASKING_ABILITY
 764    0x0800    //TX_NND_WEIGHT
-765    0x0050    //TX_MIC_CALIBRATION_0
-766    0x0065    //TX_MIC_CALIBRATION_1
-767    0x0050    //TX_MIC_CALIBRATION_2
-768    0x0050    //TX_MIC_CALIBRATION_3
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
 769    0x0046    //TX_MIC_PWR_BIAS_0
-770    0x0040    //TX_MIC_PWR_BIAS_1
+770    0x0046    //TX_MIC_PWR_BIAS_1
 771    0x0046    //TX_MIC_PWR_BIAS_2
 772    0x0046    //TX_MIC_PWR_BIAS_3
 773    0x0000    //TX_GAIN_LIMIT_0
 774    0x000F    //TX_GAIN_LIMIT_1
-775    0x0000    //TX_GAIN_LIMIT_2
+775    0x000F    //TX_GAIN_LIMIT_2
 776    0x0000    //TX_GAIN_LIMIT_3
 777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
 778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
@@ -46368,15 +72881,15 @@
 780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
 781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
 782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
-783    0x0800    //TX_TDDRC_ALPHA_UP_01
-784    0x0800    //TX_TDDRC_ALPHA_UP_02
-785    0x0800    //TX_TDDRC_ALPHA_UP_03
-786    0x0800    //TX_TDDRC_ALPHA_UP_04
-787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
 788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
 789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
-790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
-791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
 792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
 793    0x0000    //TX_TDDRC_RESRV_0
 794    0x0000    //TX_TDDRC_RESRV_1
@@ -46401,8 +72914,8 @@
 813    0x5333    //TX_FDDRC_SLANT_1_1
 814    0x5333    //TX_FDDRC_SLANT_1_2
 815    0x5333    //TX_FDDRC_SLANT_1_3
-816    0x0010    //TX_DEADMIC_SILENCE_TH
-817    0x0600    //TX_MIC_DEGRADE_TH
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
 818    0x0078    //TX_DEADMIC_CNT
 819    0x0078    //TX_MIC_DEGRADE_CNT
 820    0x0000    //TX_FDDRC_RESRV_4
@@ -46439,19 +72952,19 @@
 851    0x0000    //TX_FFP_RESRV_5
 852    0x0000    //TX_FFP_RESRV_6
 853    0x0002    //TX_FILTINDX
-854    0x0001    //TX_TDDRC_THRD_0
-855    0x0002    //TX_TDDRC_THRD_1
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
 856    0x1000    //TX_TDDRC_THRD_2
-857    0x1000    //TX_TDDRC_THRD_3
-858    0x6000    //TX_TDDRC_SLANT_0
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
 859    0x6000    //TX_TDDRC_SLANT_1
-860    0x0800    //TX_TDDRC_ALPHA_UP_00
-861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
 862    0x0000    //TX_TDDRC_HMNC_FLAG
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0E21    //TX_TDDRC_DRC_GAIN
+866    0x12D6    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -46482,62 +72995,127 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x247C    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
-2    0x0000    //RX_SAMPLINGFREQ_SIG
-3    0x0000    //RX_SAMPLINGFREQ_PROC
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
 4    0x000A    //RX_FRAME_SZ
 5    0x0000    //RX_DELAY_OPT
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-10    0x050D    //RX_PGA
-11    0x7652    //RX_A_HP
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7D83    //RX_A_HP
 12    0x4000    //RX_B_PE
 13    0x7800    //RX_THR_PITCH_DET_0
 14    0x7000    //RX_THR_PITCH_DET_1
 15    0x6000    //RX_THR_PITCH_DET_2
-16    0x0000    //RX_PITCH_BFR_LEN
-17    0x0000    //RX_SBD_PITCH_DET
-18    0x0000    //RX_PP_RESRV_0
-19    0x0000    //RX_PP_RESRV_1
-20    0xF800    //RX_N_SN_EST
-21    0x0000    //RX_N2_SN_EST
-22    0x000F    //RX_NS_LVL_CTRL
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
 23    0xF800    //RX_THR_SN_EST
-24    0x7E00    //RX_LAMBDA_PFILT
+24    0x7CCD    //RX_LAMBDA_PFILT
 25    0x000A    //RX_FENS_RESRV_0
-26    0x0000    //RX_FENS_RESRV_1
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-30    0x0000    //RX_EXTRA_NS_L
-31    0x0000    //RX_EXTRA_NS_A
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-35    0x0000    //RX_A_POST_FLT
+35    0x199A    //RX_A_POST_FLT
 36    0x0000    //RX_LMT_THRD
 37    0x4000    //RX_LMT_ALPHA
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
-40    0x4848    //RX_FDEQ_GAIN_1
-41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
-44    0x4848    //RX_FDEQ_GAIN_5
-45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -46546,22 +73124,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -46570,117 +73148,117 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-111    0x0003    //RX_FILTINDX
+111    0x0004    //RX_FILTINDX
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
 125    0x7C00    //RX_LAMBDA_PKA_FP
-126    0x2000    //RX_TPKA_FP
-127    0x0080    //RX_MIN_G_FP
-128    0x2000    //RX_MAX_G_FP
-129    0x0100    //RX_SPK_VOL
+126    0x1014    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0A12    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
-131    0x0010    //RX_MAXLEVEL_CNG
-132    0x0000    //RX_BWE_UV_TH
-133    0x0000    //RX_BWE_UV_TH2
-134    0x0000    //RX_BWE_UV_TH3
-135    0x0000    //RX_BWE_V_TH
-136    0x0000    //RX_BWE_GAIN1_V_TH1
-137    0x0000    //RX_BWE_GAIN1_V_TH2
-138    0x0000    //RX_BWE_UV_EQ
-139    0x0000    //RX_BWE_V_EQ
-140    0x0000    //RX_BWE_TONE_TH
-141    0x0000    //RX_BWE_UV_HOLD_T
-142    0x0000    //RX_BWE_GAIN2_ALPHA
-143    0x0000    //RX_BWE_GAIN3_ALPHA
-144    0x0000    //RX_BWE_CUTOFF
-145    0x0000    //RX_BWE_GAINFILL
-146    0x0000    //RX_BWE_MAXTH_TONE
-147    0x0000    //RX_BWE_EQ_0
-148    0x0000    //RX_BWE_EQ_1
-149    0x0000    //RX_BWE_EQ_2
-150    0x0000    //RX_BWE_EQ_3
-151    0x0000    //RX_BWE_EQ_4
-152    0x0000    //RX_BWE_EQ_5
-153    0x0000    //RX_BWE_EQ_6
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
 154    0x0000    //RX_BWE_RESRV_0
 155    0x0000    //RX_BWE_RESRV_1
 156    0x0000    //RX_BWE_RESRV_2
 #VOL    0
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x0100    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -46689,22 +73267,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -46713,73 +73291,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0043    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    1
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x0100    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -46788,22 +73366,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -46812,73 +73390,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x0068    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    2
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x0100    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -46887,22 +73465,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -46911,73 +73489,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x009E    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    3
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
 124    0x0100    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -46986,22 +73564,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -47010,73 +73588,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
-129    0x0100    //RX_SPK_VOL
+129    0x00F2    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    4
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0004    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x017B    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -47085,22 +73663,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -47109,73 +73687,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    5
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
 112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+113    0x0007    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x027C    //RX_TDDRC_DRC_GAIN
 38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4864    //RX_FDEQ_GAIN_7
+47    0x709E    //RX_FDEQ_GAIN_8
+48    0x9E82    //RX_FDEQ_GAIN_9
+49    0x7A82    //RX_FDEQ_GAIN_10
+50    0x766C    //RX_FDEQ_GAIN_11
+51    0x6278    //RX_FDEQ_GAIN_12
+52    0x623C    //RX_FDEQ_GAIN_13
+53    0x424E    //RX_FDEQ_GAIN_14
+54    0x6060    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -47184,22 +73762,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -47208,73 +73786,73 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
 #VOL    6
-6    0x3000    //RX_TDDRC_ALPHA_UP_1
-7    0x3000    //RX_TDDRC_ALPHA_UP_2
-8    0x3000    //RX_TDDRC_ALPHA_UP_3
-9    0x3000    //RX_TDDRC_ALPHA_UP_4
-27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
-28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
-29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
-32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
-33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x2000    //RX_TDDRC_ALPHA_UP_3
+9    0x0A00    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
 34    0x0800    //RX_TDDRC_LIMITER_GAIN
-112    0x0000    //RX_TDDRC_THRD_0
-113    0x0000    //RX_TDDRC_THRD_1
-114    0x0E80    //RX_TDDRC_THRD_2
-115    0x3800    //RX_TDDRC_THRD_3
-116    0x2A00    //RX_TDDRC_SLANT_0
-117    0x6E00    //RX_TDDRC_SLANT_1
-118    0x3000    //RX_TDDRC_ALPHA_UP_0
-119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+112    0x0002    //RX_TDDRC_THRD_0
+113    0x0014    //RX_TDDRC_THRD_1
+114    0x1600    //RX_TDDRC_THRD_2
+115    0x1D00    //RX_TDDRC_THRD_3
+116    0x4000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
 120    0x0000    //RX_TDDRC_HMNC_FLAG
-121    0x0000    //RX_TDDRC_HMNC_GAIN
-122    0x0000    //RX_TDDRC_SMT_FLAG
-123    0x0000    //RX_TDDRC_SMT_W
-124    0x0100    //RX_TDDRC_DRC_GAIN
-38    0x0020    //RX_FDEQ_SUBNUM
-39    0x4848    //RX_FDEQ_GAIN_0
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x07F1    //RX_TDDRC_DRC_GAIN
+38    0x0025    //RX_FDEQ_SUBNUM
+39    0x8484    //RX_FDEQ_GAIN_0
 40    0x4848    //RX_FDEQ_GAIN_1
 41    0x4848    //RX_FDEQ_GAIN_2
-42    0x4848    //RX_FDEQ_GAIN_3
-43    0x4848    //RX_FDEQ_GAIN_4
+42    0x4A4C    //RX_FDEQ_GAIN_3
+43    0x4C48    //RX_FDEQ_GAIN_4
 44    0x4848    //RX_FDEQ_GAIN_5
 45    0x4848    //RX_FDEQ_GAIN_6
-46    0x4848    //RX_FDEQ_GAIN_7
-47    0x4848    //RX_FDEQ_GAIN_8
-48    0x4848    //RX_FDEQ_GAIN_9
-49    0x4848    //RX_FDEQ_GAIN_10
-50    0x4848    //RX_FDEQ_GAIN_11
-51    0x4848    //RX_FDEQ_GAIN_12
-52    0x4848    //RX_FDEQ_GAIN_13
-53    0x4848    //RX_FDEQ_GAIN_14
-54    0x4848    //RX_FDEQ_GAIN_15
+46    0x4870    //RX_FDEQ_GAIN_7
+47    0x84B4    //RX_FDEQ_GAIN_8
+48    0xB098    //RX_FDEQ_GAIN_9
+49    0x9098    //RX_FDEQ_GAIN_10
+50    0x8882    //RX_FDEQ_GAIN_11
+51    0x788C    //RX_FDEQ_GAIN_12
+52    0x784E    //RX_FDEQ_GAIN_13
+53    0x5260    //RX_FDEQ_GAIN_14
+54    0x786C    //RX_FDEQ_GAIN_15
 55    0x4848    //RX_FDEQ_GAIN_16
 56    0x4848    //RX_FDEQ_GAIN_17
 57    0x4848    //RX_FDEQ_GAIN_18
@@ -47283,22 +73861,22 @@
 60    0x4848    //RX_FDEQ_GAIN_21
 61    0x4848    //RX_FDEQ_GAIN_22
 62    0x4848    //RX_FDEQ_GAIN_23
-63    0x0000    //RX_FDEQ_BIN_0
-64    0x0000    //RX_FDEQ_BIN_1
-65    0x0000    //RX_FDEQ_BIN_2
-66    0x0000    //RX_FDEQ_BIN_3
-67    0x0000    //RX_FDEQ_BIN_4
-68    0x0000    //RX_FDEQ_BIN_5
-69    0x0000    //RX_FDEQ_BIN_6
-70    0x0000    //RX_FDEQ_BIN_7
-71    0x0000    //RX_FDEQ_BIN_8
-72    0x0000    //RX_FDEQ_BIN_9
-73    0x0000    //RX_FDEQ_BIN_10
-74    0x0000    //RX_FDEQ_BIN_11
-75    0x0000    //RX_FDEQ_BIN_12
-76    0x0000    //RX_FDEQ_BIN_13
-77    0x0000    //RX_FDEQ_BIN_14
-78    0x0000    //RX_FDEQ_BIN_15
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0201    //RX_FDEQ_BIN_1
+65    0x0405    //RX_FDEQ_BIN_2
+66    0x0505    //RX_FDEQ_BIN_3
+67    0x0203    //RX_FDEQ_BIN_4
+68    0x0505    //RX_FDEQ_BIN_5
+69    0x0808    //RX_FDEQ_BIN_6
+70    0x1917    //RX_FDEQ_BIN_7
+71    0x0A0A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1E1A    //RX_FDEQ_BIN_13
+77    0x0F37    //RX_FDEQ_BIN_14
+78    0x5360    //RX_FDEQ_BIN_15
 79    0x0000    //RX_FDEQ_BIN_16
 80    0x0000    //RX_FDEQ_BIN_17
 81    0x0000    //RX_FDEQ_BIN_18
@@ -47307,36 +73885,888 @@
 84    0x0000    //RX_FDEQ_BIN_21
 85    0x0000    //RX_FDEQ_BIN_22
 86    0x0000    //RX_FDEQ_BIN_23
-87    0x0000    //RX_FDEQ_RESRV_0
-88    0x0000    //RX_FDEQ_RESRV_1
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
 89    0x0018    //RX_FDDRC_BAND_MARGIN_0
-90    0x0030    //RX_FDDRC_BAND_MARGIN_1
-91    0x0050    //RX_FDDRC_BAND_MARGIN_2
-92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
 93    0x0004    //RX_FDDRC_BLOCK_EXP
 94    0x5000    //RX_FDDRC_THRD_2_0
 95    0x5000    //RX_FDDRC_THRD_2_1
-96    0x5000    //RX_FDDRC_THRD_2_2
+96    0x2000    //RX_FDDRC_THRD_2_2
 97    0x5000    //RX_FDDRC_THRD_2_3
 98    0x6400    //RX_FDDRC_THRD_3_0
 99    0x6400    //RX_FDDRC_THRD_3_1
-100    0x6400    //RX_FDDRC_THRD_3_2
-101    0x6400    //RX_FDDRC_THRD_3_3
-102    0x2000    //RX_FDDRC_SLANT_0_0
-103    0x2000    //RX_FDDRC_SLANT_0_1
-104    0x2000    //RX_FDDRC_SLANT_0_2
-105    0x2000    //RX_FDDRC_SLANT_0_3
-106    0x2000    //RX_FDDRC_SLANT_1_0
-107    0x2000    //RX_FDDRC_SLANT_1_1
-108    0x2000    //RX_FDDRC_SLANT_1_2
-109    0x2000    //RX_FDDRC_SLANT_1_3
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x7468    //RX_FDEQ_GAIN_9
+206    0x6060    //RX_FDEQ_GAIN_10
+207    0x6060    //RX_FDEQ_GAIN_11
+208    0x5C54    //RX_FDEQ_GAIN_12
+209    0x5450    //RX_FDEQ_GAIN_13
+210    0x5050    //RX_FDEQ_GAIN_14
+211    0x5860    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0308    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7EB8    //RX_TDDRC_SLANT_0
+274    0x2500    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0550    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0039    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0054    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0085    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x00C7    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0134    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01EE    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8464    //RX_FDEQ_GAIN_0
+197    0x5150    //RX_FDEQ_GAIN_1
+198    0x555C    //RX_FDEQ_GAIN_2
+199    0x6E75    //RX_FDEQ_GAIN_3
+200    0x8077    //RX_FDEQ_GAIN_4
+201    0x756D    //RX_FDEQ_GAIN_5
+202    0x6667    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0006    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03AD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8468    //RX_FDEQ_GAIN_0
+197    0x4F4F    //RX_FDEQ_GAIN_1
+198    0x555A    //RX_FDEQ_GAIN_2
+199    0x6069    //RX_FDEQ_GAIN_3
+200    0x7D86    //RX_FDEQ_GAIN_4
+201    0x8682    //RX_FDEQ_GAIN_5
+202    0x7461    //RX_FDEQ_GAIN_6
+203    0x5352    //RX_FDEQ_GAIN_7
+204    0x5860    //RX_FDEQ_GAIN_8
+205    0x5D5F    //RX_FDEQ_GAIN_9
+206    0x5A52    //RX_FDEQ_GAIN_10
+207    0x535A    //RX_FDEQ_GAIN_11
+208    0x6654    //RX_FDEQ_GAIN_12
+209    0x6068    //RX_FDEQ_GAIN_13
+210    0x6F69    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_VCO-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0001    //TX_OPERATION_MODE_1
@@ -47359,15 +74789,15 @@
 18    0x0000    //TX_SYS_RESRV_2
 19    0x0000    //TX_SYS_RESRV_3
 20    0x0000    //TX_DIST2REF0
-21    0x00A4    //TX_DIST2REF1
-22    0x0017    //TX_DIST2REF_02
+21    0x009D    //TX_DIST2REF1
+22    0x0010    //TX_DIST2REF_02
 23    0x0000    //TX_DIST2REF_03
 24    0x0000    //TX_DIST2REF_04
 25    0x0000    //TX_DIST2REF_05
 26    0x0000    //TX_MMIC
-27    0x0FF7    //TX_PGA_0
-28    0x0FF7    //TX_PGA_1
-29    0x0FF7    //TX_PGA_2
+27    0x0A19    //TX_PGA_0
+28    0x0A19    //TX_PGA_1
+29    0x0A19    //TX_PGA_2
 30    0x0000    //TX_PGA_3
 31    0x0000    //TX_PGA_4
 32    0x0000    //TX_PGA_5
@@ -47570,7 +75000,7 @@
 229    0x2000    //TX_B_POST_FILT_ECHO_H
 230    0x0200    //TX_MIN_G_CTRL_ECHO
 231    0x1000    //TX_B_LESSCUT_RTO_ECHO
-232    0x0000    //TX_EPD_OFFSET_00
+232    0x0063    //TX_EPD_OFFSET_00
 233    0x0000    //TX_EPD_OFFST_01
 234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
 235    0x3A98    //TX_RATIO_DT_H_TH_CUT
@@ -47589,11 +75019,11 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0200    //TX_DELTA_THR_SN_EST_1
-252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0200    //TX_DELTA_THR_SN_EST_3
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
 254    0x0100    //TX_DELTA_THR_SN_EST_4
-255    0x0100    //TX_DELTA_THR_SN_EST_5
+255    0x0200    //TX_DELTA_THR_SN_EST_5
 256    0x0200    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
@@ -47621,11 +75051,11 @@
 280    0x1000    //TX_B_POST_FLT_1
 281    0x0010    //TX_NS_LVL_CTRL_0
 282    0x0014    //TX_NS_LVL_CTRL_1
-283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0018    //TX_NS_LVL_CTRL_3
-285    0x0016    //TX_NS_LVL_CTRL_4
-286    0x0014    //TX_NS_LVL_CTRL_5
-287    0x0011    //TX_NS_LVL_CTRL_6
+283    0x0018    //TX_NS_LVL_CTRL_2
+284    0x0016    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x0014    //TX_NS_LVL_CTRL_6
 288    0x0011    //TX_NS_LVL_CTRL_7
 289    0x000F    //TX_MIN_GAIN_S_0
 290    0x0010    //TX_MIN_GAIN_S_1
@@ -47643,8 +75073,8 @@
 302    0x4000    //TX_SNRI_SUP_2
 303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
-305    0x4000    //TX_SNRI_SUP_5
-306    0x50C0    //TX_SNRI_SUP_6
+305    0x50C0    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
 307    0x7FFF    //TX_SNRI_SUP_7
 308    0x7FFF    //TX_THR_LFNS
 309    0x0018    //TX_G_LFNS
@@ -47653,19 +75083,19 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x2000    //TX_A_POST_FILT_1
 314    0x5000    //TX_A_POST_FILT_S_0
-315    0x6000    //TX_A_POST_FILT_S_1
-316    0x4C00    //TX_A_POST_FILT_S_2
-317    0x4000    //TX_A_POST_FILT_S_3
-318    0x6000    //TX_A_POST_FILT_S_4
-319    0x4000    //TX_A_POST_FILT_S_5
-320    0x5000    //TX_A_POST_FILT_S_6
+315    0x4C00    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
 321    0x7000    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
-323    0x1000    //TX_B_POST_FILT_1
+323    0x2000    //TX_B_POST_FILT_1
 324    0x2000    //TX_B_POST_FILT_2
-325    0x2000    //TX_B_POST_FILT_3
+325    0x4000    //TX_B_POST_FILT_3
 326    0x4000    //TX_B_POST_FILT_4
-327    0x4000    //TX_B_POST_FILT_5
+327    0x1000    //TX_B_POST_FILT_5
 328    0x1000    //TX_B_POST_FILT_6
 329    0x2000    //TX_B_POST_FILT_7
 330    0x4000    //TX_B_LESSCUT_RTO_S_0
@@ -47673,14 +75103,14 @@
 332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
 333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
 334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
-335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
-336    0x6000    //TX_B_LESSCUT_RTO_S_6
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
 337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
 338    0x7C00    //TX_LAMBDA_PFILT
 339    0x7C00    //TX_LAMBDA_PFILT_S_0
 340    0x7C00    //TX_LAMBDA_PFILT_S_1
-341    0x7C00    //TX_LAMBDA_PFILT_S_2
-342    0x7A00    //TX_LAMBDA_PFILT_S_3
+341    0x7A00    //TX_LAMBDA_PFILT_S_2
+342    0x7C00    //TX_LAMBDA_PFILT_S_3
 343    0x7C00    //TX_LAMBDA_PFILT_S_4
 344    0x7C00    //TX_LAMBDA_PFILT_S_5
 345    0x7C00    //TX_LAMBDA_PFILT_S_6
@@ -47718,10 +75148,10 @@
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x2710    //TX_NOISE_TH_6
 379    0x0033    //TX_MINENOISE_TH
-380    0x4000    //TX_MINENOISE_MIC0_TH_MTS
-381    0xFFEE    //TX_MINENOISE_MIC0_TH_EXP
-382    0x6000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0xFFF3    //TX_MINENOISE_MIC0_S_TH_EXP
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x7999    //TX_RATIODTL_CUT_TH
+383    0x0119    //TX_DT_CUT_K1
 384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
 385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x0333    //TX_OUT_ENER_S_TH_NOISY
@@ -47729,15 +75159,15 @@
 388    0x0333    //TX_OUT_ENER_TH_SPEECH
 389    0x2000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0800    //TX_MU_ARSP_EST
-396    0x00C8    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0002    //TX_EXTRA_NS_L
-398    0x0800    //TX_EXTRA_NS_A
-399    0x0005    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x4000    //TX_A_POST_FLT_WNS
 400    0x0148    //TX_MIN_G_LOW300HZ
 401    0x0002    //TX_MAXLEVEL_CNG
 402    0x00B4    //TX_STN_NOISE_TH
@@ -47852,16 +75282,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x0000    //TX_MICTOBFGAIN0
 513    0x0000    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -47890,19 +75320,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0070    //TX_BF_LESSCUT_BBIN
-554    0x0070    //TX_BF_LESSCUT_EBIN
-555    0x0010    //TX_POSTBFB0
-556    0x0070    //TX_POSTBFB
-557    0x00B0    //TX_POSTBFE
-558    0x0E66    //TX_SPEECH_SNR_TH
-559    0x0050    //TX_PB_MAX_PRI_SNR_TH
-560    0x770A    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -47910,15 +75340,15 @@
 569    0x4848    //TX_FDEQ_GAIN_2
 570    0x4848    //TX_FDEQ_GAIN_3
 571    0x4848    //TX_FDEQ_GAIN_4
-572    0x4848    //TX_FDEQ_GAIN_5
+572    0x5048    //TX_FDEQ_GAIN_5
 573    0x4848    //TX_FDEQ_GAIN_6
 574    0x4848    //TX_FDEQ_GAIN_7
 575    0x4848    //TX_FDEQ_GAIN_8
-576    0x4853    //TX_FDEQ_GAIN_9
-577    0x5450    //TX_FDEQ_GAIN_10
-578    0x7465    //TX_FDEQ_GAIN_11
-579    0x807F    //TX_FDEQ_GAIN_12
-580    0x82C4    //TX_FDEQ_GAIN_13
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x5B5B    //TX_FDEQ_GAIN_10
+578    0x737B    //TX_FDEQ_GAIN_11
+579    0x7B9A    //TX_FDEQ_GAIN_12
+580    0x9AC4    //TX_FDEQ_GAIN_13
 581    0xC4C4    //TX_FDEQ_GAIN_14
 582    0xC4C4    //TX_FDEQ_GAIN_15
 583    0x4848    //TX_FDEQ_GAIN_16
@@ -47954,24 +75384,24 @@
 613    0x0000    //TX_FDEQ_BIN_22
 614    0x0000    //TX_FDEQ_BIN_23
 615    0x0000    //TX_FDEQ_PADDING
-616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+616    0x0030    //TX_PREEQ_SUBNUM_MIC0
 617    0x4848    //TX_PREEQ_GAIN_MIC0_0
 618    0x4848    //TX_PREEQ_GAIN_MIC0_1
 619    0x4848    //TX_PREEQ_GAIN_MIC0_2
 620    0x4848    //TX_PREEQ_GAIN_MIC0_3
 621    0x4848    //TX_PREEQ_GAIN_MIC0_4
 622    0x4848    //TX_PREEQ_GAIN_MIC0_5
-623    0x4A4C    //TX_PREEQ_GAIN_MIC0_6
-624    0x4E50    //TX_PREEQ_GAIN_MIC0_7
-625    0x5456    //TX_PREEQ_GAIN_MIC0_8
-626    0x585C    //TX_PREEQ_GAIN_MIC0_9
-627    0x5C64    //TX_PREEQ_GAIN_MIC0_10
-628    0x7478    //TX_PREEQ_GAIN_MIC0_11
-629    0x705C    //TX_PREEQ_GAIN_MIC0_12
-630    0x4838    //TX_PREEQ_GAIN_MIC0_13
-631    0x3C70    //TX_PREEQ_GAIN_MIC0_14
-632    0x4848    //TX_PREEQ_GAIN_MIC0_15
-633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+623    0x4849    //TX_PREEQ_GAIN_MIC0_6
+624    0x4A4B    //TX_PREEQ_GAIN_MIC0_7
+625    0x4C4B    //TX_PREEQ_GAIN_MIC0_8
+626    0x4A48    //TX_PREEQ_GAIN_MIC0_9
+627    0x4B4C    //TX_PREEQ_GAIN_MIC0_10
+628    0x4C4B    //TX_PREEQ_GAIN_MIC0_11
+629    0x4838    //TX_PREEQ_GAIN_MIC0_12
+630    0x3858    //TX_PREEQ_GAIN_MIC0_13
+631    0x7060    //TX_PREEQ_GAIN_MIC0_14
+632    0x9870    //TX_PREEQ_GAIN_MIC0_15
+633    0x5848    //TX_PREEQ_GAIN_MIC0_16
 634    0x4848    //TX_PREEQ_GAIN_MIC0_17
 635    0x4848    //TX_PREEQ_GAIN_MIC0_18
 636    0x4848    //TX_PREEQ_GAIN_MIC0_19
@@ -47985,17 +75415,17 @@
 644    0x0304    //TX_PREEQ_BIN_MIC0_3
 645    0x0405    //TX_PREEQ_BIN_MIC0_4
 646    0x0506    //TX_PREEQ_BIN_MIC0_5
-647    0x0708    //TX_PREEQ_BIN_MIC0_6
-648    0x0909    //TX_PREEQ_BIN_MIC0_7
-649    0x090B    //TX_PREEQ_BIN_MIC0_8
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
 650    0x0C10    //TX_PREEQ_BIN_MIC0_9
 651    0x1013    //TX_PREEQ_BIN_MIC0_10
 652    0x1414    //TX_PREEQ_BIN_MIC0_11
-653    0x1414    //TX_PREEQ_BIN_MIC0_12
-654    0x1C1E    //TX_PREEQ_BIN_MIC0_13
-655    0x1E28    //TX_PREEQ_BIN_MIC0_14
-656    0x462C    //TX_PREEQ_BIN_MIC0_15
-657    0x0000    //TX_PREEQ_BIN_MIC0_16
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x4000    //TX_PREEQ_BIN_MIC0_16
 658    0x0000    //TX_PREEQ_BIN_MIC0_17
 659    0x0000    //TX_PREEQ_BIN_MIC0_18
 660    0x0000    //TX_PREEQ_BIN_MIC0_19
@@ -48010,15 +75440,15 @@
 669    0x4848    //TX_PREEQ_GAIN_MIC1_3
 670    0x4848    //TX_PREEQ_GAIN_MIC1_4
 671    0x4848    //TX_PREEQ_GAIN_MIC1_5
-672    0x4848    //TX_PREEQ_GAIN_MIC1_6
-673    0x4848    //TX_PREEQ_GAIN_MIC1_7
-674    0x4848    //TX_PREEQ_GAIN_MIC1_8
-675    0x4848    //TX_PREEQ_GAIN_MIC1_9
-676    0x4848    //TX_PREEQ_GAIN_MIC1_10
-677    0x4848    //TX_PREEQ_GAIN_MIC1_11
-678    0x4848    //TX_PREEQ_GAIN_MIC1_12
-679    0x4848    //TX_PREEQ_GAIN_MIC1_13
-680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+672    0x4645    //TX_PREEQ_GAIN_MIC1_6
+673    0x4442    //TX_PREEQ_GAIN_MIC1_7
+674    0x4140    //TX_PREEQ_GAIN_MIC1_8
+675    0x3E3D    //TX_PREEQ_GAIN_MIC1_9
+676    0x3C3C    //TX_PREEQ_GAIN_MIC1_10
+677    0x3C3C    //TX_PREEQ_GAIN_MIC1_11
+678    0x3938    //TX_PREEQ_GAIN_MIC1_12
+679    0x3A3C    //TX_PREEQ_GAIN_MIC1_13
+680    0x3C3E    //TX_PREEQ_GAIN_MIC1_14
 681    0x4848    //TX_PREEQ_GAIN_MIC1_15
 682    0x4848    //TX_PREEQ_GAIN_MIC1_16
 683    0x4848    //TX_PREEQ_GAIN_MIC1_17
@@ -48028,23 +75458,23 @@
 687    0x4848    //TX_PREEQ_GAIN_MIC1_21
 688    0x4848    //TX_PREEQ_GAIN_MIC1_22
 689    0x4848    //TX_PREEQ_GAIN_MIC1_23
-690    0x1812    //TX_PREEQ_BIN_MIC1_0
-691    0x0A0A    //TX_PREEQ_BIN_MIC1_1
-692    0x0808    //TX_PREEQ_BIN_MIC1_2
-693    0x080A    //TX_PREEQ_BIN_MIC1_3
-694    0x0B09    //TX_PREEQ_BIN_MIC1_4
-695    0x0A06    //TX_PREEQ_BIN_MIC1_5
-696    0x0606    //TX_PREEQ_BIN_MIC1_6
-697    0x0605    //TX_PREEQ_BIN_MIC1_7
-698    0x050A    //TX_PREEQ_BIN_MIC1_8
-699    0x1505    //TX_PREEQ_BIN_MIC1_9
-700    0x0506    //TX_PREEQ_BIN_MIC1_10
-701    0x0615    //TX_PREEQ_BIN_MIC1_11
-702    0x1516    //TX_PREEQ_BIN_MIC1_12
-703    0x2021    //TX_PREEQ_BIN_MIC1_13
-704    0x2021    //TX_PREEQ_BIN_MIC1_14
-705    0x2021    //TX_PREEQ_BIN_MIC1_15
-706    0x0800    //TX_PREEQ_BIN_MIC1_16
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x4000    //TX_PREEQ_BIN_MIC1_16
 707    0x0000    //TX_PREEQ_BIN_MIC1_17
 708    0x0000    //TX_PREEQ_BIN_MIC1_18
 709    0x0000    //TX_PREEQ_BIN_MIC1_19
@@ -48204,7 +75634,7 @@
 863    0x199A    //TX_TDDRC_HMNC_GAIN
 864    0x0000    //TX_TDDRC_SMT_FLAG
 865    0x0CCD    //TX_TDDRC_SMT_W
-866    0x0A98    //TX_TDDRC_DRC_GAIN
+866    0x0FDA    //TX_TDDRC_DRC_GAIN
 867    0x7FFF    //TX_TDDRC_LMT_THRD
 868    0x0000    //TX_TDDRC_LMT_ALPHA
 869    0x0000    //TX_TFMASKLTH
@@ -48235,8 +75665,73 @@
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -49086,10 +76581,3532 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-TTY_VCO-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x00F3    //TX_PATCH_REG
+3    0x6F7D    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0003    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009C    //TX_DIST2REF1
+22    0x0019    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x1000    //TX_PGA_0
+28    0x1000    //TX_PGA_1
+29    0x1000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0001    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0002    //TX_MIC_DATA_SRC0
+42    0x0000    //TX_MIC_DATA_SRC1
+43    0x0001    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3B33    //TX_DIST2REF_11
+73    0x0A70    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0CAE    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7B02    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x5000    //TX_THR_PITCH_DET_0
+131    0x4800    //TX_THR_PITCH_DET_1
+132    0x4000    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x0400    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x2000    //TX_MIN_EQ_RE_EST_0
+153    0x0600    //TX_MIN_EQ_RE_EST_1
+154    0x3000    //TX_MIN_EQ_RE_EST_2
+155    0x6000    //TX_MIN_EQ_RE_EST_3
+156    0x3000    //TX_MIN_EQ_RE_EST_4
+157    0x3000    //TX_MIN_EQ_RE_EST_5
+158    0x3000    //TX_MIN_EQ_RE_EST_6
+159    0x3000    //TX_MIN_EQ_RE_EST_7
+160    0x7800    //TX_MIN_EQ_RE_EST_8
+161    0x7800    //TX_MIN_EQ_RE_EST_9
+162    0x7800    //TX_MIN_EQ_RE_EST_10
+163    0x7800    //TX_MIN_EQ_RE_EST_11
+164    0x7800    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x3000    //TX_LAMBDA_CB_NLE
+167    0x7FFF    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0260    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x0680    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7080    //TX_DTD_THR1_0
+198    0x7FF0    //TX_DTD_THR1_1
+199    0x7C38    //TX_DTD_THR1_2
+200    0x7FF0    //TX_DTD_THR1_3
+201    0x7FF0    //TX_DTD_THR1_4
+202    0x7D00    //TX_DTD_THR1_5
+203    0x7FF0    //TX_DTD_THR1_6
+204    0x7E00    //TX_DTD_THR2_0
+205    0x7E00    //TX_DTD_THR2_1
+206    0x5000    //TX_DTD_THR2_2
+207    0x5000    //TX_DTD_THR2_3
+208    0x5000    //TX_DTD_THR2_4
+209    0x5000    //TX_DTD_THR2_5
+210    0x5000    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x2710    //TX_DT_CUT_K
+214    0x0040    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x7FFF    //TX_DTD_MIC_BLK
+221    0x023E    //TX_ADPT_STRICT_L
+222    0x023E    //TX_ADPT_STRICT_H
+223    0x0001    //TX_RATIO_DT_L_TH_LOW
+224    0x1A98    //TX_RATIO_DT_H_TH_LOW
+225    0x02BC    //TX_RATIO_DT_L_TH_HIGH
+226    0x157C    //TX_RATIO_DT_H_TH_HIGH
+227    0x0001    //TX_RATIO_DT_L0_TH
+228    0x3000    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x0190    //TX_RATIO_DT_L0_TH_HIGH
+235    0x7FFF    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF800    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0120    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0100    //TX_DELTA_THR_SN_EST_3
+254    0x0100    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0100    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0022    //TX_NS_LVL_CTRL_1
+283    0x0024    //TX_NS_LVL_CTRL_2
+284    0x001A    //TX_NS_LVL_CTRL_3
+285    0x0014    //TX_NS_LVL_CTRL_4
+286    0x0011    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x0020    //TX_MIN_GAIN_S_0
+290    0x0020    //TX_MIN_GAIN_S_1
+291    0x0020    //TX_MIN_GAIN_S_2
+292    0x0020    //TX_MIN_GAIN_S_3
+293    0x0020    //TX_MIN_GAIN_S_4
+294    0x0020    //TX_MIN_GAIN_S_5
+295    0x0020    //TX_MIN_GAIN_S_6
+296    0x0020    //TX_MIN_GAIN_S_7
+297    0x3000    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x4000    //TX_SNRI_SUP_1
+302    0x6000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x4000    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0018    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x7FFF    //TX_A_POST_FILT_S_0
+315    0x7FFF    //TX_A_POST_FILT_S_1
+316    0x7FFF    //TX_A_POST_FILT_S_2
+317    0x7FFF    //TX_A_POST_FILT_S_3
+318    0x7FFF    //TX_A_POST_FILT_S_4
+319    0x7FFF    //TX_A_POST_FILT_S_5
+320    0x7FFF    //TX_A_POST_FILT_S_6
+321    0x7FFF    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x6000    //TX_B_POST_FILT_1
+324    0x6000    //TX_B_POST_FILT_2
+325    0x6000    //TX_B_POST_FILT_3
+326    0x4000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x4000    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x6000    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7F00    //TX_LAMBDA_PFILT
+339    0x7F00    //TX_LAMBDA_PFILT_S_0
+340    0x7F00    //TX_LAMBDA_PFILT_S_1
+341    0x7F00    //TX_LAMBDA_PFILT_S_2
+342    0x7F00    //TX_LAMBDA_PFILT_S_3
+343    0x7F00    //TX_LAMBDA_PFILT_S_4
+344    0x7F00    //TX_LAMBDA_PFILT_S_5
+345    0x7F00    //TX_LAMBDA_PFILT_S_6
+346    0x7F00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0600    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0040    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x2000    //TX_DT_BINVAD_TH_2
+356    0x2000    //TX_DT_BINVAD_TH_3
+357    0x36B0    //TX_DT_BINVAD_ENDF
+358    0x0200    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0140    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0064    //TX_NDETCT
+367    0x0050    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x01F4    //TX_NOISE_TH_2
+372    0x36B0    //TX_NOISE_TH_3
+373    0x2710    //TX_NOISE_TH_4
+374    0x7FFF    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x0DAC    //TX_NOISE_TH_6
+379    0x0050    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x07D0    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x7FFF    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0050    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x4000    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x2000    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x4000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0x3000    //TX_DEREVERB_LF_MU
+515    0x34CD    //TX_DEREVERB_HF_MU
+516    0x0007    //TX_DEREVERB_DELAY
+517    0x0004    //TX_DEREVERB_COEF_LEN
+518    0x0003    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x3A98    //TX_GSC_RTOL_TH
+522    0x3A98    //TX_GSC_RTOH_TH
+523    0x7E2C    //TX_WIDE2_MEANHTH
+524    0x0064    //TX_DR_RESRV_5
+525    0x1000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x484C    //TX_FDEQ_GAIN_1
+569    0x4E50    //TX_FDEQ_GAIN_2
+570    0x5050    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4854    //TX_FDEQ_GAIN_5
+573    0x545C    //TX_FDEQ_GAIN_6
+574    0x5252    //TX_FDEQ_GAIN_7
+575    0x545A    //TX_FDEQ_GAIN_8
+576    0x5A58    //TX_FDEQ_GAIN_9
+577    0x6066    //TX_FDEQ_GAIN_10
+578    0x6E6A    //TX_FDEQ_GAIN_11
+579    0x727A    //TX_FDEQ_GAIN_12
+580    0x7A78    //TX_FDEQ_GAIN_13
+581    0x4E36    //TX_FDEQ_GAIN_14
+582    0x5C70    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x050C    //TX_FDEQ_BIN_6
+598    0x070A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1710    //TX_FDEQ_BIN_11
+603    0x241E    //TX_FDEQ_BIN_12
+604    0x1E32    //TX_FDEQ_BIN_13
+605    0x0A3C    //TX_FDEQ_BIN_14
+606    0x144A    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0022    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x484E    //TX_PREEQ_GAIN_MIC0_12
+630    0x525C    //TX_PREEQ_GAIN_MIC0_13
+631    0x6868    //TX_PREEQ_GAIN_MIC0_14
+632    0x6868    //TX_PREEQ_GAIN_MIC0_15
+633    0x6C70    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0202    //TX_PREEQ_BIN_MIC0_0
+642    0x0203    //TX_PREEQ_BIN_MIC0_1
+643    0x0303    //TX_PREEQ_BIN_MIC0_2
+644    0x0304    //TX_PREEQ_BIN_MIC0_3
+645    0x0405    //TX_PREEQ_BIN_MIC0_4
+646    0x0506    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0809    //TX_PREEQ_BIN_MIC0_7
+649    0x0A0A    //TX_PREEQ_BIN_MIC0_8
+650    0x0C10    //TX_PREEQ_BIN_MIC0_9
+651    0x1013    //TX_PREEQ_BIN_MIC0_10
+652    0x1414    //TX_PREEQ_BIN_MIC0_11
+653    0x261E    //TX_PREEQ_BIN_MIC0_12
+654    0x1E14    //TX_PREEQ_BIN_MIC0_13
+655    0x1414    //TX_PREEQ_BIN_MIC0_14
+656    0x2814    //TX_PREEQ_BIN_MIC0_15
+657    0x322C    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0022    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x484E    //TX_PREEQ_GAIN_MIC1_12
+679    0x525C    //TX_PREEQ_GAIN_MIC1_13
+680    0x6868    //TX_PREEQ_GAIN_MIC1_14
+681    0x6868    //TX_PREEQ_GAIN_MIC1_15
+682    0x6C70    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0202    //TX_PREEQ_BIN_MIC1_0
+691    0x0203    //TX_PREEQ_BIN_MIC1_1
+692    0x0303    //TX_PREEQ_BIN_MIC1_2
+693    0x0304    //TX_PREEQ_BIN_MIC1_3
+694    0x0405    //TX_PREEQ_BIN_MIC1_4
+695    0x0506    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0809    //TX_PREEQ_BIN_MIC1_7
+698    0x0A0A    //TX_PREEQ_BIN_MIC1_8
+699    0x0C10    //TX_PREEQ_BIN_MIC1_9
+700    0x1013    //TX_PREEQ_BIN_MIC1_10
+701    0x1414    //TX_PREEQ_BIN_MIC1_11
+702    0x261E    //TX_PREEQ_BIN_MIC1_12
+703    0x1E14    //TX_PREEQ_BIN_MIC1_13
+704    0x1414    //TX_PREEQ_BIN_MIC1_14
+705    0x2814    //TX_PREEQ_BIN_MIC1_15
+706    0x322C    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0022    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x484E    //TX_PREEQ_GAIN_MIC2_12
+728    0x525C    //TX_PREEQ_GAIN_MIC2_13
+729    0x6868    //TX_PREEQ_GAIN_MIC2_14
+730    0x6868    //TX_PREEQ_GAIN_MIC2_15
+731    0x6870    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0202    //TX_PREEQ_BIN_MIC2_0
+740    0x0203    //TX_PREEQ_BIN_MIC2_1
+741    0x0303    //TX_PREEQ_BIN_MIC2_2
+742    0x0304    //TX_PREEQ_BIN_MIC2_3
+743    0x0405    //TX_PREEQ_BIN_MIC2_4
+744    0x0506    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0809    //TX_PREEQ_BIN_MIC2_7
+747    0x0A0A    //TX_PREEQ_BIN_MIC2_8
+748    0x0C10    //TX_PREEQ_BIN_MIC2_9
+749    0x1013    //TX_PREEQ_BIN_MIC2_10
+750    0x1414    //TX_PREEQ_BIN_MIC2_11
+751    0x261E    //TX_PREEQ_BIN_MIC2_12
+752    0x1E14    //TX_PREEQ_BIN_MIC2_13
+753    0x1414    //TX_PREEQ_BIN_MIC2_14
+754    0x2814    //TX_PREEQ_BIN_MIC2_15
+755    0x3628    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x005A    //TX_MIC_CALIBRATION_0
+766    0x005A    //TX_MIC_CALIBRATION_1
+767    0x005A    //TX_MIC_CALIBRATION_2
+768    0x005A    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x0000    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x6000    //TX_TDDRC_ALPHA_UP_01
+784    0x7EB8    //TX_TDDRC_ALPHA_UP_02
+785    0x7EB8    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x6000    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x4000    //TX_TDDRC_ALPHA_DWN_04
+791    0x7214    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0006    //TX_DEADMIC_SILENCE_TH
+817    0x2800    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0096    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0004    //TX_TDDRC_THRD_0
+855    0x0010    //TX_TDDRC_THRD_1
+856    0x1000    //TX_TDDRC_THRD_2
+857    0x1800    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6000    //TX_TDDRC_SLANT_1
+860    0x4000    //TX_TDDRC_ALPHA_UP_00
+861    0x6000    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x12D6    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x6379    //TX_SENDFUNC_REG_MICMUTE
+898    0x0020    //TX_SENDFUNC_REG_MICMUTE1
+899    0x0258    //TX_MICMUTE_RATIO_THR
+900    0x02A8    //TX_MICMUTE_AMP_THR
+901    0x0000    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x0E00    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0000    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7B00    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x7F58    //TX_DTD_THR1_MICMUTE_0
+912    0x797C    //TX_DTD_THR1_MICMUTE_1
+913    0x3CF0    //TX_DTD_THR1_MICMUTE_2
+914    0x4970    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x7FFF    //TX_MIC1MUTE_RATIO_THR
+940    0x0001    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0100    //TX_AMS_RESRV_01
+944    0xDCD8    //TX_AMS_RESRV_02
+945    0x0FA0    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x247C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7652    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0010    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x7214    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x847C    //RX_FDEQ_GAIN_0
+40    0x5A56    //RX_FDEQ_GAIN_1
+41    0x6266    //RX_FDEQ_GAIN_2
+42    0x6E7A    //RX_FDEQ_GAIN_3
+43    0x8678    //RX_FDEQ_GAIN_4
+44    0x6D66    //RX_FDEQ_GAIN_5
+45    0x706E    //RX_FDEQ_GAIN_6
+46    0x6C64    //RX_FDEQ_GAIN_7
+47    0x5C6A    //RX_FDEQ_GAIN_8
+48    0x6268    //RX_FDEQ_GAIN_9
+49    0x6462    //RX_FDEQ_GAIN_10
+50    0x646E    //RX_FDEQ_GAIN_11
+51    0x6860    //RX_FDEQ_GAIN_12
+52    0x646A    //RX_FDEQ_GAIN_13
+53    0x7478    //RX_FDEQ_GAIN_14
+54    0x9898    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0301    //RX_FDEQ_BIN_0
+64    0x0105    //RX_FDEQ_BIN_1
+65    0x0203    //RX_FDEQ_BIN_2
+66    0x0205    //RX_FDEQ_BIN_3
+67    0x0404    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0410    //RX_FDEQ_BIN_6
+70    0x050A    //RX_FDEQ_BIN_7
+71    0x0B07    //RX_FDEQ_BIN_8
+72    0x120E    //RX_FDEQ_BIN_9
+73    0x100E    //RX_FDEQ_BIN_10
+74    0x0E2D    //RX_FDEQ_BIN_11
+75    0x1923    //RX_FDEQ_BIN_12
+76    0x151E    //RX_FDEQ_BIN_13
+77    0x1E2D    //RX_FDEQ_BIN_14
+78    0x2D40    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0004    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x0CE0    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x03FC    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x13E0    //RX_TPKA_FP
+127    0x0400    //RX_MIN_G_FP
+128    0x0800    //RX_MAX_G_FP
+129    0x0058    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C94    //RX_FDEQ_GAIN_8
+48    0x8488    //RX_FDEQ_GAIN_9
+49    0x7C6E    //RX_FDEQ_GAIN_10
+50    0x6C6C    //RX_FDEQ_GAIN_11
+51    0x6E74    //RX_FDEQ_GAIN_12
+52    0x5A50    //RX_FDEQ_GAIN_13
+53    0x6470    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0050    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C94    //RX_FDEQ_GAIN_8
+48    0x8488    //RX_FDEQ_GAIN_9
+49    0x7C6E    //RX_FDEQ_GAIN_10
+50    0x6C6C    //RX_FDEQ_GAIN_11
+51    0x6E74    //RX_FDEQ_GAIN_12
+52    0x5A50    //RX_FDEQ_GAIN_13
+53    0x6470    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0079    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C94    //RX_FDEQ_GAIN_8
+48    0x8488    //RX_FDEQ_GAIN_9
+49    0x7C6E    //RX_FDEQ_GAIN_10
+50    0x6C6C    //RX_FDEQ_GAIN_11
+51    0x6E74    //RX_FDEQ_GAIN_12
+52    0x5A50    //RX_FDEQ_GAIN_13
+53    0x6470    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x00B6    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0118    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C94    //RX_FDEQ_GAIN_8
+48    0x8488    //RX_FDEQ_GAIN_9
+49    0x7C6E    //RX_FDEQ_GAIN_10
+50    0x6C6C    //RX_FDEQ_GAIN_11
+51    0x6E74    //RX_FDEQ_GAIN_12
+52    0x5A50    //RX_FDEQ_GAIN_13
+53    0x6470    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x00F8    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0002    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x019B    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C94    //RX_FDEQ_GAIN_8
+48    0x8488    //RX_FDEQ_GAIN_9
+49    0x7C6E    //RX_FDEQ_GAIN_10
+50    0x6C6C    //RX_FDEQ_GAIN_11
+51    0x6E74    //RX_FDEQ_GAIN_12
+52    0x5A50    //RX_FDEQ_GAIN_13
+53    0x6470    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0005    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x028F    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C98    //RX_FDEQ_GAIN_8
+48    0x9894    //RX_FDEQ_GAIN_9
+49    0x8476    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7478    //RX_FDEQ_GAIN_12
+52    0x6860    //RX_FDEQ_GAIN_13
+53    0x6C7C    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x6000    //RX_TDDRC_ALPHA_UP_1
+7    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+8    0x6000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x6000    //RX_TDDRC_ALPHA_DWN_3
+32    0x4000    //RX_TDDRC_ALPHA_DWN_4
+33    0x50C2    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0002    //RX_TDDRC_THRD_0
+113    0x0007    //RX_TDDRC_THRD_1
+114    0x0340    //RX_TDDRC_THRD_2
+115    0x1400    //RX_TDDRC_THRD_3
+116    0x0000    //RX_TDDRC_SLANT_0
+117    0x7FFF    //RX_TDDRC_SLANT_1
+118    0x6000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0550    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0xA4A4    //RX_FDEQ_GAIN_0
+40    0x5448    //RX_FDEQ_GAIN_1
+41    0x5464    //RX_FDEQ_GAIN_2
+42    0x605E    //RX_FDEQ_GAIN_3
+43    0x5A4E    //RX_FDEQ_GAIN_4
+44    0x4E48    //RX_FDEQ_GAIN_5
+45    0x4C50    //RX_FDEQ_GAIN_6
+46    0x525C    //RX_FDEQ_GAIN_7
+47    0x8C98    //RX_FDEQ_GAIN_8
+48    0x9894    //RX_FDEQ_GAIN_9
+49    0x8476    //RX_FDEQ_GAIN_10
+50    0x7474    //RX_FDEQ_GAIN_11
+51    0x7478    //RX_FDEQ_GAIN_12
+52    0x6860    //RX_FDEQ_GAIN_13
+53    0x6C7C    //RX_FDEQ_GAIN_14
+54    0x7084    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0102    //RX_FDEQ_BIN_1
+65    0x0406    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0205    //RX_FDEQ_BIN_4
+68    0x0303    //RX_FDEQ_BIN_5
+69    0x0A08    //RX_FDEQ_BIN_6
+70    0x1613    //RX_FDEQ_BIN_7
+71    0x110A    //RX_FDEQ_BIN_8
+72    0x0A0A    //RX_FDEQ_BIN_9
+73    0x0A0A    //RX_FDEQ_BIN_10
+74    0x0A0A    //RX_FDEQ_BIN_11
+75    0x0A0A    //RX_FDEQ_BIN_12
+76    0x1424    //RX_FDEQ_BIN_13
+77    0x2150    //RX_FDEQ_BIN_14
+78    0x2860    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0035    //RX_FDDRC_BAND_MARGIN_1
+91    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+92    0x0120    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x2000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x2000    //RX_FDDRC_THRD_3_2
+101    0x5000    //RX_FDDRC_THRD_3_3
+102    0x4000    //RX_FDDRC_SLANT_0_0
+103    0x4000    //RX_FDDRC_SLANT_0_1
+104    0x4000    //RX_FDDRC_SLANT_0_2
+105    0x4000    //RX_FDDRC_SLANT_0_3
+106    0x7FFF    //RX_FDDRC_SLANT_1_0
+107    0x7FFF    //RX_FDDRC_SLANT_1_1
+108    0x7FFF    //RX_FDDRC_SLANT_1_2
+109    0x7FFF    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x027C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x6000    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0010    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4850    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4860    //RX_FDEQ_GAIN_8
+205    0x7468    //RX_FDEQ_GAIN_9
+206    0x6060    //RX_FDEQ_GAIN_10
+207    0x6060    //RX_FDEQ_GAIN_11
+208    0x5C54    //RX_FDEQ_GAIN_12
+209    0x5450    //RX_FDEQ_GAIN_13
+210    0x5050    //RX_FDEQ_GAIN_14
+211    0x5860    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0308    //RX_FDEQ_BIN_5
+226    0x0808    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x7EB8    //RX_TDDRC_SLANT_0
+274    0x2500    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0550    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x0014    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0039    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0054    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0085    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0002    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x00C7    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x19C0    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0134    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8458    //RX_FDEQ_GAIN_0
+197    0x4B4B    //RX_FDEQ_GAIN_1
+198    0x5156    //RX_FDEQ_GAIN_2
+199    0x646C    //RX_FDEQ_GAIN_3
+200    0x7B73    //RX_FDEQ_GAIN_4
+201    0x6D66    //RX_FDEQ_GAIN_5
+202    0x6768    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0004    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01EE    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8464    //RX_FDEQ_GAIN_0
+197    0x5150    //RX_FDEQ_GAIN_1
+198    0x555C    //RX_FDEQ_GAIN_2
+199    0x6E75    //RX_FDEQ_GAIN_3
+200    0x8077    //RX_FDEQ_GAIN_4
+201    0x756D    //RX_FDEQ_GAIN_5
+202    0x6667    //RX_FDEQ_GAIN_6
+203    0x6D68    //RX_FDEQ_GAIN_7
+204    0x5E6A    //RX_FDEQ_GAIN_8
+205    0x6668    //RX_FDEQ_GAIN_9
+206    0x645A    //RX_FDEQ_GAIN_10
+207    0x5A5E    //RX_FDEQ_GAIN_11
+208    0x6A58    //RX_FDEQ_GAIN_12
+209    0x646E    //RX_FDEQ_GAIN_13
+210    0x787C    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x6000    //RX_TDDRC_ALPHA_UP_1
+164    0x7EB8    //RX_TDDRC_ALPHA_UP_2
+165    0x6000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x6000    //RX_TDDRC_ALPHA_DWN_3
+189    0x4000    //RX_TDDRC_ALPHA_DWN_4
+190    0x7214    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0002    //RX_TDDRC_THRD_0
+270    0x0006    //RX_TDDRC_THRD_1
+271    0x0340    //RX_TDDRC_THRD_2
+272    0x1C00    //RX_TDDRC_THRD_3
+273    0x0000    //RX_TDDRC_SLANT_0
+274    0x7FFF    //RX_TDDRC_SLANT_1
+275    0x6000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x03AD    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x8468    //RX_FDEQ_GAIN_0
+197    0x4F4F    //RX_FDEQ_GAIN_1
+198    0x555A    //RX_FDEQ_GAIN_2
+199    0x6069    //RX_FDEQ_GAIN_3
+200    0x7D86    //RX_FDEQ_GAIN_4
+201    0x8682    //RX_FDEQ_GAIN_5
+202    0x7461    //RX_FDEQ_GAIN_6
+203    0x5352    //RX_FDEQ_GAIN_7
+204    0x5860    //RX_FDEQ_GAIN_8
+205    0x5D5F    //RX_FDEQ_GAIN_9
+206    0x5A52    //RX_FDEQ_GAIN_10
+207    0x535A    //RX_FDEQ_GAIN_11
+208    0x6654    //RX_FDEQ_GAIN_12
+209    0x6068    //RX_FDEQ_GAIN_13
+210    0x6F69    //RX_FDEQ_GAIN_14
+211    0x9898    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0301    //RX_FDEQ_BIN_0
+221    0x0204    //RX_FDEQ_BIN_1
+222    0x0203    //RX_FDEQ_BIN_2
+223    0x0205    //RX_FDEQ_BIN_3
+224    0x0404    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0410    //RX_FDEQ_BIN_6
+227    0x050A    //RX_FDEQ_BIN_7
+228    0x0B07    //RX_FDEQ_BIN_8
+229    0x120E    //RX_FDEQ_BIN_9
+230    0x100E    //RX_FDEQ_BIN_10
+231    0x0E2D    //RX_FDEQ_BIN_11
+232    0x1923    //RX_FDEQ_BIN_12
+233    0x151E    //RX_FDEQ_BIN_13
+234    0x1E2D    //RX_FDEQ_BIN_14
+235    0x2D40    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0035    //RX_FDDRC_BAND_MARGIN_1
+248    0x00D5    //RX_FDDRC_BAND_MARGIN_2
+249    0x0120    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x2000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x2000    //RX_FDDRC_THRD_3_2
+258    0x5000    //RX_FDDRC_THRD_3_3
+259    0x4000    //RX_FDDRC_SLANT_0_0
+260    0x4000    //RX_FDDRC_SLANT_0_1
+261    0x4000    //RX_FDDRC_SLANT_0_2
+262    0x4000    //RX_FDDRC_SLANT_0_3
+263    0x7FFF    //RX_FDDRC_SLANT_1_0
+264    0x7FFF    //RX_FDDRC_SLANT_1_1
+265    0x7FFF    //RX_FDDRC_SLANT_1_2
+266    0x7FFF    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_FULL-VOICE_GENERIC-NB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -49280,7 +80297,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -49333,7 +80350,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -49342,12 +80359,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -49373,12 +80390,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -49394,10 +80411,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -49406,12 +80423,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -49458,7 +80475,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x003B    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -49470,11 +80487,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -49482,22 +80499,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -49605,16 +80622,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -49643,19 +80660,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -49980,16 +80997,81 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -50839,10 +81921,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_FULL-VOICE_GENERIC-WB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -51033,7 +82967,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -51086,7 +83020,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -51095,12 +83029,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -51126,12 +83060,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -51147,10 +83081,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -51159,12 +83093,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -51211,7 +83145,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x0102    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -51223,11 +83157,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -51235,22 +83169,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -51358,16 +83292,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -51396,19 +83330,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -51733,16 +83667,81 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -52592,10 +84591,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_FULL-VOICE_GENERIC-SWB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -52786,7 +85637,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -52839,7 +85690,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xFA00    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -52848,12 +85699,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -52879,12 +85730,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -52900,10 +85751,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -52912,12 +85763,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -52964,7 +85815,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x0383    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -52976,11 +85827,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -52988,22 +85839,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -53111,16 +85962,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -53149,19 +86000,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -53486,16 +86337,81 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -54345,10 +87261,862 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
 #CASE_NAME  HEADSET-TTY_FULL-VOICE_GENERIC-FB
-#PARAM_TYPE  TX+RX
-#TOTAL_CUSTOM_STEP  7
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
 #TX
 0    0x0001    //TX_OPERATION_MODE_0
 1    0x0000    //TX_OPERATION_MODE_1
@@ -54539,7 +88307,7 @@
 186    0x0000    //TX_MU0_PTD_FRQ_AEC
 187    0x0000    //TX_MINENOISETH
 188    0x0000    //TX_MU0_RE_EST
-189    0x0000    //TX_AEC_NUM_CH
+189    0x0001    //TX_AEC_NUM_CH
 190    0x0000    //TX_BIGECHOATTENUATION_MAX
 191    0x0000    //TX_A_POST_FLT_MICBLK
 192    0x0000    //TX_BLKENERTH
@@ -54592,7 +88360,7 @@
 239    0x0000    //TX_DT_RESRV_7
 240    0x0000    //TX_DT_RESRV_8
 241    0x0000    //TX_DT_RESRV_9
-242    0xF200    //TX_THR_SN_EST_0
+242    0xF700    //TX_THR_SN_EST_0
 243    0xF400    //TX_THR_SN_EST_1
 244    0xF800    //TX_THR_SN_EST_2
 245    0xF600    //TX_THR_SN_EST_3
@@ -54601,12 +88369,12 @@
 248    0xF800    //TX_THR_SN_EST_6
 249    0xF800    //TX_THR_SN_EST_7
 250    0x0100    //TX_DELTA_THR_SN_EST_0
-251    0x0000    //TX_DELTA_THR_SN_EST_1
+251    0x0100    //TX_DELTA_THR_SN_EST_1
 252    0x0100    //TX_DELTA_THR_SN_EST_2
-253    0x0100    //TX_DELTA_THR_SN_EST_3
+253    0x0200    //TX_DELTA_THR_SN_EST_3
 254    0x0200    //TX_DELTA_THR_SN_EST_4
 255    0x0200    //TX_DELTA_THR_SN_EST_5
-256    0x0200    //TX_DELTA_THR_SN_EST_6
+256    0x0000    //TX_DELTA_THR_SN_EST_6
 257    0x0200    //TX_DELTA_THR_SN_EST_7
 258    0x4000    //TX_LAMBDA_NN_EST_0
 259    0x4000    //TX_LAMBDA_NN_EST_1
@@ -54632,12 +88400,12 @@
 279    0x0000    //TX_B_POST_FLT_0
 280    0x0000    //TX_B_POST_FLT_1
 281    0x001A    //TX_NS_LVL_CTRL_0
-282    0x001A    //TX_NS_LVL_CTRL_1
+282    0x0014    //TX_NS_LVL_CTRL_1
 283    0x0014    //TX_NS_LVL_CTRL_2
-284    0x0014    //TX_NS_LVL_CTRL_3
+284    0x000C    //TX_NS_LVL_CTRL_3
 285    0x000C    //TX_NS_LVL_CTRL_4
 286    0x000C    //TX_NS_LVL_CTRL_5
-287    0x000C    //TX_NS_LVL_CTRL_6
+287    0x001A    //TX_NS_LVL_CTRL_6
 288    0x000C    //TX_NS_LVL_CTRL_7
 289    0x000E    //TX_MIN_GAIN_S_0
 290    0x0014    //TX_MIN_GAIN_S_1
@@ -54653,10 +88421,10 @@
 300    0x7FFF    //TX_SNRI_SUP_0
 301    0x7FFF    //TX_SNRI_SUP_1
 302    0x7FFF    //TX_SNRI_SUP_2
-303    0x7FFF    //TX_SNRI_SUP_3
+303    0x4000    //TX_SNRI_SUP_3
 304    0x4000    //TX_SNRI_SUP_4
 305    0x4000    //TX_SNRI_SUP_5
-306    0x4000    //TX_SNRI_SUP_6
+306    0x7FFF    //TX_SNRI_SUP_6
 307    0x4000    //TX_SNRI_SUP_7
 308    0x1200    //TX_THR_LFNS
 309    0x0147    //TX_G_LFNS
@@ -54665,12 +88433,12 @@
 312    0x7FFF    //TX_A_POST_FILT_0
 313    0x7FFF    //TX_A_POST_FILT_1
 314    0x4000    //TX_A_POST_FILT_S_0
-315    0x199A    //TX_A_POST_FILT_S_1
+315    0x1000    //TX_A_POST_FILT_S_1
 316    0x1000    //TX_A_POST_FILT_S_2
-317    0x1000    //TX_A_POST_FILT_S_3
+317    0x6666    //TX_A_POST_FILT_S_3
 318    0x6666    //TX_A_POST_FILT_S_4
 319    0x6666    //TX_A_POST_FILT_S_5
-320    0x6666    //TX_A_POST_FILT_S_6
+320    0x199A    //TX_A_POST_FILT_S_6
 321    0x6666    //TX_A_POST_FILT_S_7
 322    0x2000    //TX_B_POST_FILT_0
 323    0x2000    //TX_B_POST_FILT_1
@@ -54717,7 +88485,7 @@
 364    0x0000    //TX_K_APT
 365    0x0001    //TX_NOISEDET
 366    0x05A0    //TX_NDETCT
-367    0x000A    //TX_NOISE_TH_0
+367    0x04E8    //TX_NOISE_TH_0
 368    0x1388    //TX_NOISE_TH_0_2
 369    0x3A98    //TX_NOISE_TH_0_3
 370    0x0C80    //TX_NOISE_TH_1
@@ -54729,11 +88497,11 @@
 376    0x7FFF    //TX_NOISE_TH_5_3
 377    0x7FFF    //TX_NOISE_TH_5_4
 378    0x00C8    //TX_NOISE_TH_6
-379    0x000A    //TX_MINENOISE_TH
-380    0x0000    //TX_MINENOISE_MIC0_TH_MTS
-381    0x0000    //TX_MINENOISE_MIC0_TH_EXP
-382    0x0000    //TX_MINENOISE_MIC0_S_TH_MTS
-383    0x0000    //TX_MINENOISE_MIC0_S_TH_EXP
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
 384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
 385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
 386    0x6400    //TX_OUT_ENER_S_TH_NOISY
@@ -54741,22 +88509,22 @@
 388    0x7D00    //TX_OUT_ENER_TH_SPEECH
 389    0x0000    //TX_SN_NPB_GAIN
 390    0x0000    //TX_NN_NPB_GAIN
-391    0x0000    //TX_CSX_ALPHA_0
-392    0x0000    //TX_CSX_ALPHA_1
-393    0x0000    //TX_CSX_ALPHA_2
-394    0x0000    //TX_CSX_ALPHA_3
-395    0x0000    //TX_MU_ARSP_EST
-396    0x0000    //TX_P_OUTBEAM_MIN_TH
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
 397    0x0000    //TX_EXTRA_NS_L
-398    0x0000    //TX_EXTRA_NS_A
-399    0x0000    //TX_VR_NOISE_FLOOR_TH
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
 400    0x0000    //TX_MIN_G_LOW300HZ
 401    0x0010    //TX_MAXLEVEL_CNG
 402    0x0000    //TX_STN_NOISE_TH
 403    0x0000    //TX_POST_MASK_SUP
 404    0x0000    //TX_POST_MASK_ADJUST
 405    0x0014    //TX_NS_ENOISE_MIC0_TH
-406    0x0014    //TX_MINENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
 407    0x0226    //TX_MINENOISE_MIC0_S_TH
 408    0x2879    //TX_MIN_G_CTRL_SSNS
 409    0x0400    //TX_METAL_RTO_THR
@@ -54864,16 +88632,16 @@
 511    0x6666    //TX_MIC_TO_BFGAIN
 512    0x6666    //TX_MICTOBFGAIN0
 513    0x0014    //TX_FASTMUE_TH
-514    0x0000    //TX_DERVB_LEN_0
-515    0x0000    //TX_DERVB_LEN_1
-516    0x0000    //TX_RHO_DERVB
-517    0x0000    //TX_MIC_INDX_DERVB
-518    0x0000    //TX_MU_DERVB
-519    0x0000    //TX_DR_RESRV_0
-520    0x0000    //TX_DR_RESRV_1
-521    0x0000    //TX_DR_RESRV_2
-522    0x0000    //TX_DR_RESRV_3
-523    0x0000    //TX_DR_RESRV_4
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
 524    0x0000    //TX_DR_RESRV_5
 525    0x0000    //TX_DR_RESRV_6
 526    0x0000    //TX_DR_RESRV_7
@@ -54902,19 +88670,19 @@
 549    0x0000    //TX_WNS_RESRV_4
 550    0x0000    //TX_WNS_RESRV_5
 551    0x0000    //TX_WNS_RESRV_6
-552    0x0000    //TX_PB_B_POST_FLT_LESSCUT
-553    0x0000    //TX_BF_LESSCUT_BBIN
-554    0x0000    //TX_BF_LESSCUT_EBIN
-555    0x0000    //TX_POSTBFB0
-556    0x0000    //TX_POSTBFB
-557    0x0000    //TX_POSTBFE
-558    0x0000    //TX_SPEECH_SNR_TH
-559    0x0000    //TX_PB_MAX_PRI_SNR_TH
-560    0x0000    //TX_MAX_PRI_SNR_TH_L
-561    0x0000    //TX_PFGAIN
-562    0x0000    //TX_MAINTOREFR_TH
-563    0x0000    //TX_SAM_MARK
-564    0x0000    //TX_PB_RESRV_0
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
 565    0x0000    //TX_PB_RESRV_1
 566    0x0020    //TX_FDEQ_SUBNUM
 567    0x4848    //TX_FDEQ_GAIN_0
@@ -55239,16 +89007,81 @@
 886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
 887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
 888    0x00C8    //TX_FASTNS_ARSPC_TH
-889    0xD99A    //TX_FASTNS_MASK5_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
 890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
-891    0x7FFF    //TX_A_LESSCUT_RTO_MASK
+891    0x7000    //TX_A_LESSCUT_RTO_MASK
 892    0x1770    //TX_FASTNS_NOISETH
 893    0xC000    //TX_FASTNS_SSA_THLFL
 894    0xC000    //TX_FASTNS_SSA_THHFL
 895    0xCCCC    //TX_FASTNS_SSA_THLFH
 896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
 #RX
-0    0x0040    //RX_RECVFUNC_MODE_0
+0    0x2040    //RX_RECVFUNC_MODE_0
 1    0x0000    //RX_RECVFUNC_MODE_1
 2    0x0000    //RX_SAMPLINGFREQ_SIG
 3    0x0000    //RX_SAMPLINGFREQ_PROC
@@ -56098,4 +89931,16875 @@
 110    0x0000    //RX_FDDRC_RESRV_0
 129    0x0100    //RX_SPK_VOL
 130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x2040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-TTY_FULL-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0001    //TX_OPERATION_MODE_0
+1    0x0000    //TX_OPERATION_MODE_1
+2    0x0000    //TX_PATCH_REG
+3    0x0200    //TX_SENDFUNC_MODE_0
+4    0x0000    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x0078    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0302    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0000    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0000    //TX_MICS_OF_PAIR0
+38    0x0000    //TX_MICS_OF_PAIR1
+39    0x0000    //TX_MICS_OF_PAIR2
+40    0x0000    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0003    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x0000    //TX_HD_BIN_MASK
+53    0x0000    //TX_HD_SUBAND_MASK
+54    0x0000    //TX_HD_FRAME_AVG_MASK
+55    0x0000    //TX_HD_MIN_FRQ
+56    0x0000    //TX_HD_ALPHA_PSD
+57    0x0000    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0x0000    //TX_T_PSDVAT
+63    0x0000    //TX_CNT
+64    0x0000    //TX_ANTI_HOWL_GAIN
+65    0x0000    //TX_MICFORBFMARK_0
+66    0x0000    //TX_MICFORBFMARK_1
+67    0x0000    //TX_MICFORBFMARK_2
+68    0x0000    //TX_MICFORBFMARK_3
+69    0x0000    //TX_MICFORBFMARK_4
+70    0x0000    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x0000    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0800    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x0000    //TX_ADCS_GAIN
+112    0x0000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x7FFF    //TX_BLMIC_BLKFACTOR
+116    0x7FFF    //TX_BRMIC_BLKFACTOR
+117    0x000A    //TX_MICBLK_START_BIN
+118    0x0041    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0015    //TX_FENE_HOLD
+123    0x0000    //TX_FE_ENER_TH_MTS
+124    0x0000    //TX_FE_ENER_TH_EXP
+125    0x0000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x0000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0020    //TX_MIC_BLOCK_N
+128    0x7652    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x7800    //TX_THR_PITCH_DET_0
+131    0x7000    //TX_THR_PITCH_DET_1
+132    0x6000    //TX_THR_PITCH_DET_2
+133    0x0000    //TX_PITCH_BFR_LEN
+134    0x0000    //TX_SBD_PITCH_DET
+135    0x0000    //TX_TD_AEC_L
+136    0x0000    //TX_MU0_UNP_TD_AEC
+137    0x0000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x0028    //TX_TAIL_LENGTH
+147    0x2000    //TX_AEC_REF_GAIN_0
+148    0x2000    //TX_AEC_REF_GAIN_1
+149    0x2000    //TX_AEC_REF_GAIN_2
+150    0x4000    //TX_EAD_THR
+151    0x0200    //TX_THR_RE_EST
+152    0x0100    //TX_MIN_EQ_RE_EST_0
+153    0x0100    //TX_MIN_EQ_RE_EST_1
+154    0x0100    //TX_MIN_EQ_RE_EST_2
+155    0x0100    //TX_MIN_EQ_RE_EST_3
+156    0x0100    //TX_MIN_EQ_RE_EST_4
+157    0x0100    //TX_MIN_EQ_RE_EST_5
+158    0x0100    //TX_MIN_EQ_RE_EST_6
+159    0x0100    //TX_MIN_EQ_RE_EST_7
+160    0x0100    //TX_MIN_EQ_RE_EST_8
+161    0x0100    //TX_MIN_EQ_RE_EST_9
+162    0x0100    //TX_MIN_EQ_RE_EST_10
+163    0x0100    //TX_MIN_EQ_RE_EST_11
+164    0x0100    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x0000    //TX_LAMBDA_CB_NLE
+167    0x0000    //TX_C_POST_FLT
+168    0x4000    //TX_GAIN_NP
+169    0x0008    //TX_SE_HOLD_N
+170    0x0050    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x0000    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x0000    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0000    //TX_FRQ_LIN_LEN
+184    0x0000    //TX_FRQ_AEC_LEN_RHO
+185    0x0000    //TX_MU0_UNP_FRQ_AEC
+186    0x0000    //TX_MU0_PTD_FRQ_AEC
+187    0x0000    //TX_MINENOISETH
+188    0x0000    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x0000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7333    //TX_DTD_THR1_0
+198    0x7333    //TX_DTD_THR1_1
+199    0x7333    //TX_DTD_THR1_2
+200    0x7333    //TX_DTD_THR1_3
+201    0x7333    //TX_DTD_THR1_4
+202    0x7333    //TX_DTD_THR1_5
+203    0x7333    //TX_DTD_THR1_6
+204    0x0CCD    //TX_DTD_THR2_0
+205    0x0CCD    //TX_DTD_THR2_1
+206    0x0CCD    //TX_DTD_THR2_2
+207    0x0CCD    //TX_DTD_THR2_3
+208    0x0CCD    //TX_DTD_THR2_4
+209    0x0CCD    //TX_DTD_THR2_5
+210    0x0CCD    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0400    //TX_DT_CUT_K
+214    0x0000    //TX_DT_CUT_THR
+215    0x0000    //TX_COMFORT_G
+216    0x0000    //TX_POWER_YOUT_TH
+217    0x0000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x0800    //TX_B_POST_FILT_ECHO_H
+230    0x0000    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0000    //TX_EPD_OFFSET_00
+233    0x0000    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x0000    //TX_MIN_EQ_RE_EST_13
+237    0x0000    //TX_DTD_THR1_7
+238    0x0000    //TX_DTD_THR2_7
+239    0x0000    //TX_DT_RESRV_7
+240    0x0000    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF800    //TX_THR_SN_EST_2
+245    0xF600    //TX_THR_SN_EST_3
+246    0xF800    //TX_THR_SN_EST_4
+247    0xF800    //TX_THR_SN_EST_5
+248    0xF800    //TX_THR_SN_EST_6
+249    0xF800    //TX_THR_SN_EST_7
+250    0x0100    //TX_DELTA_THR_SN_EST_0
+251    0x0100    //TX_DELTA_THR_SN_EST_1
+252    0x0100    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0A00    //TX_N_SN_EST
+267    0x0000    //TX_INBEAM_T
+268    0x0000    //TX_INBEAMHOLDT
+269    0x1FFF    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x1000    //TX_NE_RTO_TH_L
+274    0x1000    //TX_MAINREFRTOH_TH_H
+275    0x1000    //TX_MAINREFRTOH_TH_L
+276    0x2000    //TX_MAINREFRTO_TH_H
+277    0x1400    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x0000    //TX_B_POST_FLT_0
+280    0x0000    //TX_B_POST_FLT_1
+281    0x001A    //TX_NS_LVL_CTRL_0
+282    0x0014    //TX_NS_LVL_CTRL_1
+283    0x0014    //TX_NS_LVL_CTRL_2
+284    0x000C    //TX_NS_LVL_CTRL_3
+285    0x000C    //TX_NS_LVL_CTRL_4
+286    0x000C    //TX_NS_LVL_CTRL_5
+287    0x001A    //TX_NS_LVL_CTRL_6
+288    0x000C    //TX_NS_LVL_CTRL_7
+289    0x000E    //TX_MIN_GAIN_S_0
+290    0x0014    //TX_MIN_GAIN_S_1
+291    0x0014    //TX_MIN_GAIN_S_2
+292    0x0014    //TX_MIN_GAIN_S_3
+293    0x0014    //TX_MIN_GAIN_S_4
+294    0x0014    //TX_MIN_GAIN_S_5
+295    0x0014    //TX_MIN_GAIN_S_6
+296    0x0014    //TX_MIN_GAIN_S_7
+297    0x0000    //TX_NMOS_SUP
+298    0x0064    //TX_NS_MAX_PRI_SNR_TH
+299    0x7FFF    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x4000    //TX_SNRI_SUP_3
+304    0x4000    //TX_SNRI_SUP_4
+305    0x4000    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x4000    //TX_SNRI_SUP_7
+308    0x1200    //TX_THR_LFNS
+309    0x0147    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x7FFF    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x7FFF    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x1000    //TX_A_POST_FILT_S_2
+317    0x6666    //TX_A_POST_FILT_S_3
+318    0x6666    //TX_A_POST_FILT_S_4
+319    0x6666    //TX_A_POST_FILT_S_5
+320    0x199A    //TX_A_POST_FILT_S_6
+321    0x6666    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x2000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7E00    //TX_LAMBDA_PFILT
+339    0x7E00    //TX_LAMBDA_PFILT_S_0
+340    0x7E00    //TX_LAMBDA_PFILT_S_1
+341    0x7E00    //TX_LAMBDA_PFILT_S_2
+342    0x7E00    //TX_LAMBDA_PFILT_S_3
+343    0x7E00    //TX_LAMBDA_PFILT_S_4
+344    0x7E00    //TX_LAMBDA_PFILT_S_5
+345    0x7E00    //TX_LAMBDA_PFILT_S_6
+346    0x7E00    //TX_LAMBDA_PFILT_S_7
+347    0x0010    //TX_K_PEPPER
+348    0x0400    //TX_A_PEPPER
+349    0x0000    //TX_K_PEPPER_HF
+350    0x0000    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0000    //TX_DT_BINVAD_TH_0
+354    0x0000    //TX_DT_BINVAD_TH_1
+355    0x0000    //TX_DT_BINVAD_TH_2
+356    0x0000    //TX_DT_BINVAD_TH_3
+357    0x0000    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0001    //TX_BF_SGRAD_FLG
+362    0x0000    //TX_BF_DVG_TH
+363    0x0000    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x05A0    //TX_NDETCT
+367    0x0383    //TX_NOISE_TH_0
+368    0x1388    //TX_NOISE_TH_0_2
+369    0x3A98    //TX_NOISE_TH_0_3
+370    0x0C80    //TX_NOISE_TH_1
+371    0x0032    //TX_NOISE_TH_2
+372    0x3D54    //TX_NOISE_TH_3
+373    0x012C    //TX_NOISE_TH_4
+374    0x07D0    //TX_NOISE_TH_5
+375    0x6590    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x00C8    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x6400    //TX_OUT_ENER_S_TH_CLEAN
+385    0x6400    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x6400    //TX_OUT_ENER_S_TH_NOISY
+387    0x6400    //TX_OUT_ENER_TH_NOISE
+388    0x7D00    //TX_OUT_ENER_TH_SPEECH
+389    0x0000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0000    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0000    //TX_MIN_G_LOW300HZ
+401    0x0010    //TX_MAXLEVEL_CNG
+402    0x0000    //TX_STN_NOISE_TH
+403    0x0000    //TX_POST_MASK_SUP
+404    0x0000    //TX_POST_MASK_ADJUST
+405    0x0014    //TX_NS_ENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
+407    0x0226    //TX_MINENOISE_MIC0_S_TH
+408    0x2879    //TX_MIN_G_CTRL_SSNS
+409    0x0400    //TX_METAL_RTO_THR
+410    0x0080    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x2000    //TX_RHO_UPB
+415    0x0020    //TX_N_HOLD_HS
+416    0x0009    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0000    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x0219    //TX_THR_STD_PLH
+421    0x09C4    //TX_N_HOLD_STD
+422    0x0166    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0800    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x0000    //TX_SB_RTO_MEAN_TH_RUB
+428    0x2000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0064    //TX_DESIRED_TALK_HOLDT
+431    0x1000    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0000    //TX_HS_VAD_BIN
+435    0x0000    //TX_THR_VAD_HS
+436    0x0000    //TX_MEAN_RTO_MIN_TH2
+437    0x0000    //TX_SILENCE_T
+438    0x4000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x099A    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x001E    //TX_DOA_VAD_THR_1
+445    0x001E    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x00B4    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x005A    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x00B4    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x005A    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x00B4    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x005A    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0172    //TX_BF_HOLDOFF_T
+473    0x8000    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x071C    //TX_DOA_TRACK_HT
+477    0x0280    //TX_N1_HOLD_HF
+478    0x0140    //TX_N2_HOLD_HF
+479    0x2AAB    //TX_BF_RESET_THR_HF
+480    0x4000    //TX_DOA_SMOOTH
+481    0x0000    //TX_MU_BF
+482    0x0200    //TX_BF_MU_LF_B2
+483    0x0000    //TX_BF_FC_END_BIN_B2
+484    0x0000    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0000    //TX_N_DOA_SEED
+488    0x0000    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x0000    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x0000    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x0000    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0168    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0004    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0230    //TX_NOR_OFF_TH1
+503    0xD333    //TX_WIDE_MASK_TH
+504    0x4650    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x000A    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x6666    //TX_MICTOBFGAIN0
+513    0x0014    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x0000    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0028    //TX_SNR_THR
+531    0x03E8    //TX_ENGY_THR
+532    0x0000    //TX_CORR_HIGH_TH
+533    0x0000    //TX_ENGY_THR_2
+534    0x0000    //TX_MEAN_RTO_THR
+535    0x0000    //TX_WNS_ENOISE_MIC0_TH
+536    0x0000    //TX_RATIOMICL_TH
+537    0x0000    //TX_CALIG_HS
+538    0x000A    //TX_LVL_CTRL
+539    0x0000    //TX_WIND_SUPRTO
+540    0x0000    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x0000    //TX_RATIOMICH_TH
+543    0x0000    //TX_WIND_INBEAM_L_TH
+544    0x0000    //TX_WIND_INBEAM_H_TH
+545    0x0000    //TX_WNS_RESRV_0
+546    0x0000    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0000    //TX_BVE_NOISE_FLOOR_1
+554    0x0000    //TX_BVE_NOISE_FLOOR_2
+555    0x0000    //TX_BVE_NOISE_FLOOR_3
+556    0x0000    //TX_BVE_NOISE_FLOOR_4
+557    0x0000    //TX_BVE_NOISE_FLOOR_5
+558    0x0000    //TX_BVE_NOISE_FLOOR_6
+559    0x0000    //TX_BVE_NOISE_FLOOR_7
+560    0x0000    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0000    //TX_FDEQ_BIN_0
+592    0x0000    //TX_FDEQ_BIN_1
+593    0x0000    //TX_FDEQ_BIN_2
+594    0x0000    //TX_FDEQ_BIN_3
+595    0x0000    //TX_FDEQ_BIN_4
+596    0x0000    //TX_FDEQ_BIN_5
+597    0x0000    //TX_FDEQ_BIN_6
+598    0x0000    //TX_FDEQ_BIN_7
+599    0x0000    //TX_FDEQ_BIN_8
+600    0x0000    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0000    //TX_PREEQ_BIN_MIC0_0
+642    0x0000    //TX_PREEQ_BIN_MIC0_1
+643    0x0000    //TX_PREEQ_BIN_MIC0_2
+644    0x0000    //TX_PREEQ_BIN_MIC0_3
+645    0x0000    //TX_PREEQ_BIN_MIC0_4
+646    0x0000    //TX_PREEQ_BIN_MIC0_5
+647    0x0000    //TX_PREEQ_BIN_MIC0_6
+648    0x0000    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0000    //TX_PREEQ_BIN_MIC1_0
+691    0x0000    //TX_PREEQ_BIN_MIC1_1
+692    0x0000    //TX_PREEQ_BIN_MIC1_2
+693    0x0000    //TX_PREEQ_BIN_MIC1_3
+694    0x0000    //TX_PREEQ_BIN_MIC1_4
+695    0x0000    //TX_PREEQ_BIN_MIC1_5
+696    0x0000    //TX_PREEQ_BIN_MIC1_6
+697    0x0000    //TX_PREEQ_BIN_MIC1_7
+698    0x0000    //TX_PREEQ_BIN_MIC1_8
+699    0x0000    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0000    //TX_PREEQ_BIN_MIC2_0
+740    0x0000    //TX_PREEQ_BIN_MIC2_1
+741    0x0000    //TX_PREEQ_BIN_MIC2_2
+742    0x0000    //TX_PREEQ_BIN_MIC2_3
+743    0x0000    //TX_PREEQ_BIN_MIC2_4
+744    0x0000    //TX_PREEQ_BIN_MIC2_5
+745    0x0000    //TX_PREEQ_BIN_MIC2_6
+746    0x0000    //TX_PREEQ_BIN_MIC2_7
+747    0x0000    //TX_PREEQ_BIN_MIC2_8
+748    0x0000    //TX_PREEQ_BIN_MIC2_9
+749    0x0000    //TX_PREEQ_BIN_MIC2_10
+750    0x0000    //TX_PREEQ_BIN_MIC2_11
+751    0x0000    //TX_PREEQ_BIN_MIC2_12
+752    0x0000    //TX_PREEQ_BIN_MIC2_13
+753    0x0000    //TX_PREEQ_BIN_MIC2_14
+754    0x0000    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0064    //TX_MIC_CALIBRATION_0
+766    0x006A    //TX_MIC_CALIBRATION_1
+767    0x006A    //TX_MIC_CALIBRATION_2
+768    0x006B    //TX_MIC_CALIBRATION_3
+769    0x0048    //TX_MIC_PWR_BIAS_0
+770    0x003C    //TX_MIC_PWR_BIAS_1
+771    0x003C    //TX_MIC_PWR_BIAS_2
+772    0x003C    //TX_MIC_PWR_BIAS_3
+773    0x0000    //TX_GAIN_LIMIT_0
+774    0x0009    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F3D    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7FB0    //TX_TDDRC_ALPHA_DWN_01
+788    0x7FB0    //TX_TDDRC_ALPHA_DWN_02
+789    0x7FB0    //TX_TDDRC_ALPHA_DWN_03
+790    0x7FB0    //TX_TDDRC_ALPHA_DWN_04
+791    0x65AD    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0002    //TX_DEADMIC_SILENCE_TH
+817    0x0147    //TX_MIC_DEGRADE_TH
+818    0x0078    //TX_DEADMIC_CNT
+819    0x0078    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x0000    //TX_KS_NOISEPASTE_FACTOR
+824    0x0000    //TX_KS_CONFIG
+825    0x0000    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0000    //TX_FFP_FP_K_METAL
+834    0x0000    //TX_A_POST_FLT_FP
+835    0x0000    //TX_RTO_OUTBEAM_TH
+836    0x0000    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0000    //TX_FFP_RESRV_2
+849    0x0000    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x0E80    //TX_TDDRC_THRD_2
+857    0x3800    //TX_TDDRC_THRD_3
+858    0x2A00    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7FB0    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x0000    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0000    //TX_TDDRC_SMT_W
+866    0x0100    //TX_TDDRC_DRC_GAIN
+867    0x0000    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x1EB8    //TX_TFMASKLTH
+870    0x170A    //TX_TFMASKLTHL
+871    0x7FFF    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x4000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x0000    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x0000    //TX_FASTNS_OUTIN_TH
+884    0x0000    //TX_FASTNS_TFMASK_TH
+885    0x0000    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0000    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0000    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x051F    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x2040    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0000    //RX_SAMPLINGFREQ_SIG
+3    0x0000    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x050D    //RX_PGA
+11    0x7652    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0000    //RX_PITCH_BFR_LEN
+17    0x0000    //RX_SBD_PITCH_DET
+18    0x0000    //RX_PP_RESRV_0
+19    0x0000    //RX_PP_RESRV_1
+20    0xF800    //RX_N_SN_EST
+21    0x0000    //RX_N2_SN_EST
+22    0x000F    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7E00    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0000    //RX_FENS_RESRV_1
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+30    0x0000    //RX_EXTRA_NS_L
+31    0x0000    //RX_EXTRA_NS_A
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x0000    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0003    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x0080    //RX_MIN_G_FP
+128    0x2000    //RX_MAX_G_FP
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0010    //RX_MAXLEVEL_CNG
+132    0x0000    //RX_BWE_UV_TH
+133    0x0000    //RX_BWE_UV_TH2
+134    0x0000    //RX_BWE_UV_TH3
+135    0x0000    //RX_BWE_V_TH
+136    0x0000    //RX_BWE_GAIN1_V_TH1
+137    0x0000    //RX_BWE_GAIN1_V_TH2
+138    0x0000    //RX_BWE_UV_EQ
+139    0x0000    //RX_BWE_V_EQ
+140    0x0000    //RX_BWE_TONE_TH
+141    0x0000    //RX_BWE_UV_HOLD_T
+142    0x0000    //RX_BWE_GAIN2_ALPHA
+143    0x0000    //RX_BWE_GAIN3_ALPHA
+144    0x0000    //RX_BWE_CUTOFF
+145    0x0000    //RX_BWE_GAINFILL
+146    0x0000    //RX_BWE_MAXTH_TONE
+147    0x0000    //RX_BWE_EQ_0
+148    0x0000    //RX_BWE_EQ_1
+149    0x0000    //RX_BWE_EQ_2
+150    0x0000    //RX_BWE_EQ_3
+151    0x0000    //RX_BWE_EQ_4
+152    0x0000    //RX_BWE_EQ_5
+153    0x0000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+28    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+29    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+32    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+33    0xDA9E    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x0E80    //RX_TDDRC_THRD_2
+115    0x3800    //RX_TDDRC_THRD_3
+116    0x2A00    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x0000    //RX_TDDRC_HMNC_GAIN
+122    0x0000    //RX_TDDRC_SMT_FLAG
+123    0x0000    //RX_TDDRC_SMT_W
+124    0x0100    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0000    //RX_FDEQ_BIN_0
+64    0x0000    //RX_FDEQ_BIN_1
+65    0x0000    //RX_FDEQ_BIN_2
+66    0x0000    //RX_FDEQ_BIN_3
+67    0x0000    //RX_FDEQ_BIN_4
+68    0x0000    //RX_FDEQ_BIN_5
+69    0x0000    //RX_FDEQ_BIN_6
+70    0x0000    //RX_FDEQ_BIN_7
+71    0x0000    //RX_FDEQ_BIN_8
+72    0x0000    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x0000    //RX_FDEQ_RESRV_0
+88    0x0000    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0004    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x2000    //RX_FDDRC_SLANT_1_0
+107    0x2000    //RX_FDDRC_SLANT_1_1
+108    0x2000    //RX_FDDRC_SLANT_1_2
+109    0x2000    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x0040    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x050D    //RX_PGA
+168    0x7652    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0000    //RX_PITCH_BFR_LEN
+174    0x0000    //RX_SBD_PITCH_DET
+175    0x0000    //RX_PP_RESRV_0
+176    0x0000    //RX_PP_RESRV_1
+177    0xF800    //RX_N_SN_EST
+178    0x0000    //RX_N2_SN_EST
+179    0x000F    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7E00    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0000    //RX_FENS_RESRV_1
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+187    0x0000    //RX_EXTRA_NS_L
+188    0x0000    //RX_EXTRA_NS_A
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x0000    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0003    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x0080    //RX_MIN_G_FP
+285    0x2000    //RX_MAX_G_FP
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0010    //RX_MAXLEVEL_CNG
+289    0x0000    //RX_BWE_UV_TH
+290    0x0000    //RX_BWE_UV_TH2
+291    0x0000    //RX_BWE_UV_TH3
+292    0x0000    //RX_BWE_V_TH
+293    0x0000    //RX_BWE_GAIN1_V_TH1
+294    0x0000    //RX_BWE_GAIN1_V_TH2
+295    0x0000    //RX_BWE_UV_EQ
+296    0x0000    //RX_BWE_V_EQ
+297    0x0000    //RX_BWE_TONE_TH
+298    0x0000    //RX_BWE_UV_HOLD_T
+299    0x0000    //RX_BWE_GAIN2_ALPHA
+300    0x0000    //RX_BWE_GAIN3_ALPHA
+301    0x0000    //RX_BWE_CUTOFF
+302    0x0000    //RX_BWE_GAINFILL
+303    0x0000    //RX_BWE_MAXTH_TONE
+304    0x0000    //RX_BWE_EQ_0
+305    0x0000    //RX_BWE_EQ_1
+306    0x0000    //RX_BWE_EQ_2
+307    0x0000    //RX_BWE_EQ_3
+308    0x0000    //RX_BWE_EQ_4
+309    0x0000    //RX_BWE_EQ_5
+310    0x0000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7FB0    //RX_TDDRC_ALPHA_DWN_1
+185    0x7FB0    //RX_TDDRC_ALPHA_DWN_2
+186    0x7FB0    //RX_TDDRC_ALPHA_DWN_3
+189    0x7FB0    //RX_TDDRC_ALPHA_DWN_4
+190    0xDA9E    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x0E80    //RX_TDDRC_THRD_2
+272    0x3800    //RX_TDDRC_THRD_3
+273    0x2A00    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7FB0    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x0000    //RX_TDDRC_HMNC_GAIN
+279    0x0000    //RX_TDDRC_SMT_FLAG
+280    0x0000    //RX_TDDRC_SMT_W
+281    0x0100    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0000    //RX_FDEQ_BIN_0
+221    0x0000    //RX_FDEQ_BIN_1
+222    0x0000    //RX_FDEQ_BIN_2
+223    0x0000    //RX_FDEQ_BIN_3
+224    0x0000    //RX_FDEQ_BIN_4
+225    0x0000    //RX_FDEQ_BIN_5
+226    0x0000    //RX_FDEQ_BIN_6
+227    0x0000    //RX_FDEQ_BIN_7
+228    0x0000    //RX_FDEQ_BIN_8
+229    0x0000    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x0000    //RX_FDEQ_RESRV_0
+245    0x0000    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0004    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x2000    //RX_FDDRC_SLANT_1_0
+264    0x2000    //RX_FDDRC_SLANT_1_1
+265    0x2000    //RX_FDDRC_SLANT_1_2
+266    0x2000    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-NB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0008    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2B68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0000    //TX_SAMPLINGFREQ_SIG
+7    0x0000    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7646    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x7CCC    //TX_THR_PITCH_DET_0
+131    0x7000    //TX_THR_PITCH_DET_1
+132    0x6333    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0010    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x1000    //TX_THR_RE_EST
+152    0x1000    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x2000    //TX_C_POST_FLT
+168    0x2000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x0064    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x5000    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7F00    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x2000    //TX_DTD_THR2_0
+205    0x2000    //TX_DTD_THR2_1
+206    0x2000    //TX_DTD_THR2_2
+207    0x2000    //TX_DTD_THR2_3
+208    0x2000    //TX_DTD_THR2_4
+209    0x2000    //TX_DTD_THR2_5
+210    0x2000    //TX_DTD_THR2_6
+211    0x4100    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x03E8    //TX_DT_CUT_K
+214    0x1000    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x1000    //TX_B_LESSCUT_RTO_ECHO
+232    0x0010    //TX_EPD_OFFSET_00
+233    0x0010    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xFA00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xFA00    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xFA00    //TX_THR_SN_EST_5
+248    0xFA00    //TX_THR_SN_EST_6
+249    0xFA00    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0000    //TX_DELTA_THR_SN_EST_1
+252    0x0000    //TX_DELTA_THR_SN_EST_2
+253    0x0000    //TX_DELTA_THR_SN_EST_3
+254    0x0000    //TX_DELTA_THR_SN_EST_4
+255    0x0000    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0000    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x0400    //TX_B_POST_FLT_0
+280    0x0400    //TX_B_POST_FLT_1
+281    0x0010    //TX_NS_LVL_CTRL_0
+282    0x0010    //TX_NS_LVL_CTRL_1
+283    0x0010    //TX_NS_LVL_CTRL_2
+284    0x0010    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
+286    0x0010    //TX_NS_LVL_CTRL_5
+287    0x0010    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x000D    //TX_MIN_GAIN_S_0
+290    0x000D    //TX_MIN_GAIN_S_1
+291    0x000D    //TX_MIN_GAIN_S_2
+292    0x000D    //TX_MIN_GAIN_S_3
+293    0x000D    //TX_MIN_GAIN_S_4
+294    0x000D    //TX_MIN_GAIN_S_5
+295    0x000D    //TX_MIN_GAIN_S_6
+296    0x000D    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0014    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x1000    //TX_A_POST_FILT_S_1
+316    0x4000    //TX_A_POST_FILT_S_2
+317    0x4000    //TX_A_POST_FILT_S_3
+318    0x4000    //TX_A_POST_FILT_S_4
+319    0x4000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x4000    //TX_A_POST_FILT_S_7
+322    0x0400    //TX_B_POST_FILT_0
+323    0x2000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x0400    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7E14    //TX_LAMBDA_PFILT
+339    0x7C29    //TX_LAMBDA_PFILT_S_0
+340    0x7C29    //TX_LAMBDA_PFILT_S_1
+341    0x7C29    //TX_LAMBDA_PFILT_S_2
+342    0x7C29    //TX_LAMBDA_PFILT_S_3
+343    0x7C29    //TX_LAMBDA_PFILT_S_4
+344    0x7C29    //TX_LAMBDA_PFILT_S_5
+345    0x7C29    //TX_LAMBDA_PFILT_S_6
+346    0x7C29    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x0FA0    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x4000    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x003B    //TX_NOISE_TH_0
+368    0x1B58    //TX_NOISE_TH_0_2
+369    0x2134    //TX_NOISE_TH_0_3
+370    0x02BC    //TX_NOISE_TH_1
+371    0x1F40    //TX_NOISE_TH_2
+372    0x4650    //TX_NOISE_TH_3
+373    0x7148    //TX_NOISE_TH_4
+374    0x044C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x0000    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x0032    //TX_NOISE_TH_6
+379    0x00C8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x00A5    //TX_OUT_ENER_S_TH_CLEAN
+385    0x00A5    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x00A5    //TX_OUT_ENER_S_TH_NOISY
+387    0x0029    //TX_OUT_ENER_TH_NOISE
+388    0x00CE    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x0032    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x7FFF    //TX_NOISEDET_BOOST_TH
+412    0x0000    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0280    //TX_N_HOLD_HS
+416    0x006E    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0333    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2400    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0640    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x2000    //TX_WTA_EN_RTO_TH
+429    0x1400    //TX_TOP_ENER_TH_F
+430    0x0064    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x003C    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x0D9A    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x2A3D    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x0000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0014    //TX_FDEQ_SUBNUM
+567    0x6048    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4844    //TX_FDEQ_GAIN_6
+574    0x4444    //TX_FDEQ_GAIN_7
+575    0x4040    //TX_FDEQ_GAIN_8
+576    0x3C3C    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0401    //TX_FDEQ_BIN_0
+592    0x0103    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x0000    //TX_FDEQ_BIN_10
+602    0x0000    //TX_FDEQ_BIN_11
+603    0x0000    //TX_FDEQ_BIN_12
+604    0x0000    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0010    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0608    //TX_PREEQ_BIN_MIC0_0
+642    0x0808    //TX_PREEQ_BIN_MIC0_1
+643    0x0808    //TX_PREEQ_BIN_MIC0_2
+644    0x0808    //TX_PREEQ_BIN_MIC0_3
+645    0x0808    //TX_PREEQ_BIN_MIC0_4
+646    0x0808    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0802    //TX_PREEQ_BIN_MIC0_7
+649    0x0000    //TX_PREEQ_BIN_MIC0_8
+650    0x0000    //TX_PREEQ_BIN_MIC0_9
+651    0x0000    //TX_PREEQ_BIN_MIC0_10
+652    0x0000    //TX_PREEQ_BIN_MIC0_11
+653    0x0000    //TX_PREEQ_BIN_MIC0_12
+654    0x0000    //TX_PREEQ_BIN_MIC0_13
+655    0x0000    //TX_PREEQ_BIN_MIC0_14
+656    0x0000    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0010    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0608    //TX_PREEQ_BIN_MIC1_0
+691    0x0808    //TX_PREEQ_BIN_MIC1_1
+692    0x0808    //TX_PREEQ_BIN_MIC1_2
+693    0x0808    //TX_PREEQ_BIN_MIC1_3
+694    0x0808    //TX_PREEQ_BIN_MIC1_4
+695    0x0808    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0802    //TX_PREEQ_BIN_MIC1_7
+698    0x0000    //TX_PREEQ_BIN_MIC1_8
+699    0x0000    //TX_PREEQ_BIN_MIC1_9
+700    0x0000    //TX_PREEQ_BIN_MIC1_10
+701    0x0000    //TX_PREEQ_BIN_MIC1_11
+702    0x0000    //TX_PREEQ_BIN_MIC1_12
+703    0x0000    //TX_PREEQ_BIN_MIC1_13
+704    0x0000    //TX_PREEQ_BIN_MIC1_14
+705    0x0000    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0010    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0802    //TX_PREEQ_BIN_MIC2_7
+747    0x0000    //TX_PREEQ_BIN_MIC2_8
+748    0x0000    //TX_PREEQ_BIN_MIC2_9
+749    0x0000    //TX_PREEQ_BIN_MIC2_10
+750    0x0000    //TX_PREEQ_BIN_MIC2_11
+751    0x0000    //TX_PREEQ_BIN_MIC2_12
+752    0x0000    //TX_PREEQ_BIN_MIC2_13
+753    0x0000    //TX_PREEQ_BIN_MIC2_14
+754    0x0000    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0065    //TX_MIC_CALIBRATION_0
+766    0x0065    //TX_MIC_CALIBRATION_1
+767    0x0065    //TX_MIC_CALIBRATION_2
+768    0x0065    //TX_MIC_CALIBRATION_3
+769    0x0044    //TX_MIC_PWR_BIAS_0
+770    0x0044    //TX_MIC_PWR_BIAS_1
+771    0x0044    //TX_MIC_PWR_BIAS_2
+772    0x0044    //TX_MIC_PWR_BIAS_3
+773    0x000B    //TX_GAIN_LIMIT_0
+774    0x000B    //TX_GAIN_LIMIT_1
+775    0x000B    //TX_GAIN_LIMIT_2
+776    0x000B    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0001    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x1000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x05A0    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0xF800    //TX_TFMASKLTH_DOA
+875    0x0CCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA02C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0000    //RX_SAMPLINGFREQ_SIG
+3    0x0000    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x3800    //RX_THR_PITCH_DET_0
+14    0x3000    //RX_THR_PITCH_DET_1
+15    0x2800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0200    //RX_TDDRC_DRC_GAIN
+38    0x0014    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D08    //RX_FDEQ_BIN_9
+73    0x0000    //RX_FDEQ_BIN_10
+74    0x0000    //RX_FDEQ_BIN_11
+75    0x0000    //RX_FDEQ_BIN_12
+76    0x0000    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0000    //RX_SAMPLINGFREQ_SIG
+160    0x0000    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0200    //RX_TDDRC_DRC_GAIN
+195    0x0014    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D08    //RX_FDEQ_BIN_9
+230    0x0000    //RX_FDEQ_BIN_10
+231    0x0000    //RX_FDEQ_BIN_11
+232    0x0000    //RX_FDEQ_BIN_12
+233    0x0000    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-WB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0008    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2B68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0001    //TX_SAMPLINGFREQ_SIG
+7    0x0001    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7D83    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x6800    //TX_THR_PITCH_DET_0
+131    0x6000    //TX_THR_PITCH_DET_1
+132    0x5800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x0019    //TX_EPD_OFFSET_00
+233    0x0019    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000F    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x4000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7CCD    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0102    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x00F8    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x00DC    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x7FFF    //TX_MIN_G_CTRL_SSNS
+409    0x0000    //TX_METAL_RTO_THR
+410    0x0000    //TX_NS_FP_K_METAL
+411    0x7FFF    //TX_NOISEDET_BOOST_TH
+412    0x0000    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x0230    //TX_NOR_OFF_THR
+498    0x0CCD    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x001C    //TX_FDEQ_SUBNUM
+567    0x5850    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0302    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D07    //TX_FDEQ_BIN_9
+601    0x0E0F    //TX_FDEQ_BIN_10
+602    0x0F10    //TX_FDEQ_BIN_11
+603    0x1011    //TX_FDEQ_BIN_12
+604    0x1119    //TX_FDEQ_BIN_13
+605    0x0000    //TX_FDEQ_BIN_14
+606    0x0000    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0608    //TX_PREEQ_BIN_MIC0_0
+642    0x0808    //TX_PREEQ_BIN_MIC0_1
+643    0x0808    //TX_PREEQ_BIN_MIC0_2
+644    0x0808    //TX_PREEQ_BIN_MIC0_3
+645    0x0808    //TX_PREEQ_BIN_MIC0_4
+646    0x0808    //TX_PREEQ_BIN_MIC0_5
+647    0x0808    //TX_PREEQ_BIN_MIC0_6
+648    0x0808    //TX_PREEQ_BIN_MIC0_7
+649    0x0808    //TX_PREEQ_BIN_MIC0_8
+650    0x0808    //TX_PREEQ_BIN_MIC0_9
+651    0x0808    //TX_PREEQ_BIN_MIC0_10
+652    0x0808    //TX_PREEQ_BIN_MIC0_11
+653    0x0808    //TX_PREEQ_BIN_MIC0_12
+654    0x0808    //TX_PREEQ_BIN_MIC0_13
+655    0x0808    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0608    //TX_PREEQ_BIN_MIC1_0
+691    0x0808    //TX_PREEQ_BIN_MIC1_1
+692    0x0808    //TX_PREEQ_BIN_MIC1_2
+693    0x0808    //TX_PREEQ_BIN_MIC1_3
+694    0x0808    //TX_PREEQ_BIN_MIC1_4
+695    0x0808    //TX_PREEQ_BIN_MIC1_5
+696    0x0808    //TX_PREEQ_BIN_MIC1_6
+697    0x0808    //TX_PREEQ_BIN_MIC1_7
+698    0x0808    //TX_PREEQ_BIN_MIC1_8
+699    0x0808    //TX_PREEQ_BIN_MIC1_9
+700    0x0808    //TX_PREEQ_BIN_MIC1_10
+701    0x0808    //TX_PREEQ_BIN_MIC1_11
+702    0x0808    //TX_PREEQ_BIN_MIC1_12
+703    0x0808    //TX_PREEQ_BIN_MIC1_13
+704    0x0808    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0608    //TX_PREEQ_BIN_MIC2_0
+740    0x0808    //TX_PREEQ_BIN_MIC2_1
+741    0x0808    //TX_PREEQ_BIN_MIC2_2
+742    0x0808    //TX_PREEQ_BIN_MIC2_3
+743    0x0808    //TX_PREEQ_BIN_MIC2_4
+744    0x0808    //TX_PREEQ_BIN_MIC2_5
+745    0x0808    //TX_PREEQ_BIN_MIC2_6
+746    0x0808    //TX_PREEQ_BIN_MIC2_7
+747    0x0808    //TX_PREEQ_BIN_MIC2_8
+748    0x0808    //TX_PREEQ_BIN_MIC2_9
+749    0x0808    //TX_PREEQ_BIN_MIC2_10
+750    0x0808    //TX_PREEQ_BIN_MIC2_11
+751    0x0808    //TX_PREEQ_BIN_MIC2_12
+752    0x0808    //TX_PREEQ_BIN_MIC2_13
+753    0x0808    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x1000    //TX_TDDRC_ALPHA_UP_01
+784    0x1000    //TX_TDDRC_ALPHA_UP_02
+785    0x1000    //TX_TDDRC_ALPHA_UP_03
+786    0x1000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x0000    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0001    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x1000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x05A0    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x00C8    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0xA02C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0001    //RX_SAMPLINGFREQ_SIG
+3    0x0001    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x3800    //RX_THR_PITCH_DET_0
+14    0x3000    //RX_THR_PITCH_DET_1
+15    0x2800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0600    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0006    //RX_NS_LVL_CTRL
+23    0xF800    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x3000    //RX_TDDRC_ALPHA_UP_1
+7    0x3000    //RX_TDDRC_ALPHA_UP_2
+8    0x3000    //RX_TDDRC_ALPHA_UP_3
+9    0x3000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x2000    //RX_TDDRC_THRD_2
+115    0x3000    //RX_TDDRC_THRD_3
+116    0x0800    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x3000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0196    //RX_TDDRC_DRC_GAIN
+38    0x001C    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x0E0F    //RX_FDEQ_BIN_10
+74    0x0F10    //RX_FDEQ_BIN_11
+75    0x1011    //RX_FDEQ_BIN_12
+76    0x1104    //RX_FDEQ_BIN_13
+77    0x0000    //RX_FDEQ_BIN_14
+78    0x0000    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0xA02C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0001    //RX_SAMPLINGFREQ_SIG
+160    0x0001    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x3800    //RX_THR_PITCH_DET_0
+171    0x3000    //RX_THR_PITCH_DET_1
+172    0x2800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0600    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0006    //RX_NS_LVL_CTRL
+180    0xF800    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x3000    //RX_TDDRC_ALPHA_UP_1
+164    0x3000    //RX_TDDRC_ALPHA_UP_2
+165    0x3000    //RX_TDDRC_ALPHA_UP_3
+166    0x3000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x2000    //RX_TDDRC_THRD_2
+272    0x3000    //RX_TDDRC_THRD_3
+273    0x0800    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x3000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0196    //RX_TDDRC_DRC_GAIN
+195    0x001C    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x0E0F    //RX_FDEQ_BIN_10
+231    0x0F10    //RX_FDEQ_BIN_11
+232    0x1011    //RX_FDEQ_BIN_12
+233    0x1104    //RX_FDEQ_BIN_13
+234    0x0000    //RX_FDEQ_BIN_14
+235    0x0000    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2B68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0383    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x05A0    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x202C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-RESERVE1-VOICE_GENERIC-FB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0009    //TX_OPERATION_MODE_1
+2    0x0020    //TX_PATCH_REG
+3    0x6B6A    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0004    //TX_SAMPLINGFREQ_SIG
+7    0x0004    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B4C    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0000    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7E56    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x6800    //TX_THR_PITCH_DET_0
+131    0x6000    //TX_THR_PITCH_DET_1
+132    0x5800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0200    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x61A8    //TX_EAD_THR
+151    0x0400    //TX_THR_RE_EST
+152    0x3000    //TX_MIN_EQ_RE_EST_0
+153    0x3000    //TX_MIN_EQ_RE_EST_1
+154    0x4000    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x6000    //TX_MIN_EQ_RE_EST_6
+159    0x6000    //TX_MIN_EQ_RE_EST_7
+160    0x6000    //TX_MIN_EQ_RE_EST_8
+161    0x6000    //TX_MIN_EQ_RE_EST_9
+162    0x4000    //TX_MIN_EQ_RE_EST_10
+163    0x4000    //TX_MIN_EQ_RE_EST_11
+164    0x4000    //TX_MIN_EQ_RE_EST_12
+165    0x3000    //TX_LAMBDA_RE_EST
+166    0x4000    //TX_LAMBDA_CB_NLE
+167    0x3000    //TX_C_POST_FLT
+168    0x7FFF    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x0800    //TX_DTD_THR1_0
+198    0x0800    //TX_DTD_THR1_1
+199    0x0800    //TX_DTD_THR1_2
+200    0x0800    //TX_DTD_THR1_3
+201    0x0800    //TX_DTD_THR1_4
+202    0x0800    //TX_DTD_THR1_5
+203    0x0800    //TX_DTD_THR1_6
+204    0x0800    //TX_DTD_THR2_0
+205    0x0800    //TX_DTD_THR2_1
+206    0x0800    //TX_DTD_THR2_2
+207    0x0800    //TX_DTD_THR2_3
+208    0x0800    //TX_DTD_THR2_4
+209    0x0100    //TX_DTD_THR2_5
+210    0x0100    //TX_DTD_THR2_6
+211    0x7FFF    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x03E8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00C0    //TX_EPD_OFFSET_00
+233    0x00C0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xF700    //TX_THR_SN_EST_0
+243    0xFB00    //TX_THR_SN_EST_1
+244    0xFA00    //TX_THR_SN_EST_2
+245    0xF700    //TX_THR_SN_EST_3
+246    0xFA00    //TX_THR_SN_EST_4
+247    0xF600    //TX_THR_SN_EST_5
+248    0xF600    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0200    //TX_DELTA_THR_SN_EST_0
+251    0x0400    //TX_DELTA_THR_SN_EST_1
+252    0x0300    //TX_DELTA_THR_SN_EST_2
+253    0x0600    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0200    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x4000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x4000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x2000    //TX_B_POST_FLT_0
+280    0x2000    //TX_B_POST_FLT_1
+281    0x0012    //TX_NS_LVL_CTRL_0
+282    0x0016    //TX_NS_LVL_CTRL_1
+283    0x0016    //TX_NS_LVL_CTRL_2
+284    0x0019    //TX_NS_LVL_CTRL_3
+285    0x0010    //TX_NS_LVL_CTRL_4
+286    0x0010    //TX_NS_LVL_CTRL_5
+287    0x0019    //TX_NS_LVL_CTRL_6
+288    0x0010    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000C    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000F    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x0011    //TX_MIN_GAIN_S_6
+296    0x000C    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7000    //TX_SNRI_SUP_0
+301    0x7000    //TX_SNRI_SUP_1
+302    0x7000    //TX_SNRI_SUP_2
+303    0x6000    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x6000    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x0016    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x6000    //TX_A_POST_FILT_S_0
+315    0x6000    //TX_A_POST_FILT_S_1
+316    0x6000    //TX_A_POST_FILT_S_2
+317    0x6000    //TX_A_POST_FILT_S_3
+318    0x6000    //TX_A_POST_FILT_S_4
+319    0x6000    //TX_A_POST_FILT_S_5
+320    0x6000    //TX_A_POST_FILT_S_6
+321    0x6000    //TX_A_POST_FILT_S_7
+322    0x2000    //TX_B_POST_FILT_0
+323    0x4000    //TX_B_POST_FILT_1
+324    0x2000    //TX_B_POST_FILT_2
+325    0x2000    //TX_B_POST_FILT_3
+326    0x2000    //TX_B_POST_FILT_4
+327    0x2000    //TX_B_POST_FILT_5
+328    0x2000    //TX_B_POST_FILT_6
+329    0x2000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7CCD    //TX_LAMBDA_PFILT
+339    0x7CCD    //TX_LAMBDA_PFILT_S_0
+340    0x7CCD    //TX_LAMBDA_PFILT_S_1
+341    0x7CCD    //TX_LAMBDA_PFILT_S_2
+342    0x7CCD    //TX_LAMBDA_PFILT_S_3
+343    0x7CCD    //TX_LAMBDA_PFILT_S_4
+344    0x7CCD    //TX_LAMBDA_PFILT_S_5
+345    0x7CCD    //TX_LAMBDA_PFILT_S_6
+346    0x7CCD    //TX_LAMBDA_PFILT_S_7
+347    0x0200    //TX_K_PEPPER
+348    0x0500    //TX_A_PEPPER
+349    0x1600    //TX_K_PEPPER_HF
+350    0x0400    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x04E8    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x02A6    //TX_NOISE_TH_1
+371    0x04B0    //TX_NOISE_TH_2
+372    0x3194    //TX_NOISE_TH_3
+373    0x0960    //TX_NOISE_TH_4
+374    0x5555    //TX_NOISE_TH_5
+375    0x3FF4    //TX_NOISE_TH_5_2
+376    0x0001    //TX_NOISE_TH_5_3
+377    0x0000    //TX_NOISE_TH_5_4
+378    0x02BC    //TX_NOISE_TH_6
+379    0x02BC    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x1482    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0004    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x04E7    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0304    //TX_FDEQ_BIN_2
+594    0x0405    //TX_FDEQ_BIN_3
+595    0x0607    //TX_FDEQ_BIN_4
+596    0x0809    //TX_FDEQ_BIN_5
+597    0x0A0B    //TX_FDEQ_BIN_6
+598    0x0C0D    //TX_FDEQ_BIN_7
+599    0x0E0F    //TX_FDEQ_BIN_8
+600    0x1011    //TX_FDEQ_BIN_9
+601    0x1214    //TX_FDEQ_BIN_10
+602    0x1618    //TX_FDEQ_BIN_11
+603    0x1C1C    //TX_FDEQ_BIN_12
+604    0x2020    //TX_FDEQ_BIN_13
+605    0x2020    //TX_FDEQ_BIN_14
+606    0x2011    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4848    //TX_PREEQ_GAIN_MIC0_8
+626    0x4848    //TX_PREEQ_GAIN_MIC0_9
+627    0x4848    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x2000    //TX_NND_WEIGHT
+765    0x0060    //TX_MIC_CALIBRATION_0
+766    0x0060    //TX_MIC_CALIBRATION_1
+767    0x0070    //TX_MIC_CALIBRATION_2
+768    0x0070    //TX_MIC_CALIBRATION_3
+769    0x0050    //TX_MIC_PWR_BIAS_0
+770    0x0040    //TX_MIC_PWR_BIAS_1
+771    0x0040    //TX_MIC_PWR_BIAS_2
+772    0x0040    //TX_MIC_PWR_BIAS_3
+773    0x0009    //TX_GAIN_LIMIT_0
+774    0x000F    //TX_GAIN_LIMIT_1
+775    0x000F    //TX_GAIN_LIMIT_2
+776    0x000F    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x0C00    //TX_TDDRC_ALPHA_UP_01
+784    0x0C00    //TX_TDDRC_ALPHA_UP_02
+785    0x0C00    //TX_TDDRC_ALPHA_UP_03
+786    0x0C00    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x7FFF    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0002    //TX_FILTINDX
+854    0x0001    //TX_TDDRC_THRD_0
+855    0x0001    //TX_TDDRC_THRD_1
+856    0x1900    //TX_TDDRC_THRD_2
+857    0x1900    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x7B00    //TX_TDDRC_SLANT_1
+860    0x0C00    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x07F2    //TX_TDDRC_DRC_GAIN
+867    0x7FFF    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0xC000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x7000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x202C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0004    //RX_SAMPLINGFREQ_SIG
+3    0x0004    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7B02    //RX_A_HP
+12    0x4000    //RX_B_PE
+13    0x7800    //RX_THR_PITCH_DET_0
+14    0x7000    //RX_THR_PITCH_DET_1
+15    0x6000    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0500    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x000A    //RX_NS_LVL_CTRL
+23    0xF600    //RX_THR_SN_EST
+24    0x7000    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x1000    //RX_TDDRC_ALPHA_UP_1
+7    0x1000    //RX_TDDRC_ALPHA_UP_2
+8    0x1000    //RX_TDDRC_ALPHA_UP_3
+9    0x1000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x7FFF    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1200    //RX_TDDRC_THRD_2
+115    0x1900    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x6E00    //RX_TDDRC_SLANT_1
+118    0x1000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x0240    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0304    //RX_FDEQ_BIN_2
+66    0x0405    //RX_FDEQ_BIN_3
+67    0x0607    //RX_FDEQ_BIN_4
+68    0x0809    //RX_FDEQ_BIN_5
+69    0x0A0B    //RX_FDEQ_BIN_6
+70    0x0C0D    //RX_FDEQ_BIN_7
+71    0x0E0F    //RX_FDEQ_BIN_8
+72    0x1011    //RX_FDEQ_BIN_9
+73    0x1214    //RX_FDEQ_BIN_10
+74    0x1618    //RX_FDEQ_BIN_11
+75    0x1C1C    //RX_FDEQ_BIN_12
+76    0x2020    //RX_FDEQ_BIN_13
+77    0x2020    //RX_FDEQ_BIN_14
+78    0x2011    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x202C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0004    //RX_SAMPLINGFREQ_SIG
+160    0x0004    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7B02    //RX_A_HP
+169    0x4000    //RX_B_PE
+170    0x7800    //RX_THR_PITCH_DET_0
+171    0x7000    //RX_THR_PITCH_DET_1
+172    0x6000    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0500    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x000A    //RX_NS_LVL_CTRL
+180    0xF600    //RX_THR_SN_EST
+181    0x7000    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x1000    //RX_TDDRC_ALPHA_UP_1
+164    0x1000    //RX_TDDRC_ALPHA_UP_2
+165    0x1000    //RX_TDDRC_ALPHA_UP_3
+166    0x1000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x7FFF    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1200    //RX_TDDRC_THRD_2
+272    0x1900    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x6E00    //RX_TDDRC_SLANT_1
+275    0x1000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x0240    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0304    //RX_FDEQ_BIN_2
+223    0x0405    //RX_FDEQ_BIN_3
+224    0x0607    //RX_FDEQ_BIN_4
+225    0x0809    //RX_FDEQ_BIN_5
+226    0x0A0B    //RX_FDEQ_BIN_6
+227    0x0C0D    //RX_FDEQ_BIN_7
+228    0x0E0F    //RX_FDEQ_BIN_8
+229    0x1011    //RX_FDEQ_BIN_9
+230    0x1214    //RX_FDEQ_BIN_10
+231    0x1618    //RX_FDEQ_BIN_11
+232    0x1C1C    //RX_FDEQ_BIN_12
+233    0x2020    //RX_FDEQ_BIN_13
+234    0x2020    //RX_FDEQ_BIN_14
+235    0x2011    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+
+#CASE_NAME  HEADSET-RESERVE1-RESERVE2-SWB
+#PARAM_MODE  FULL
+#PARAM_TYPE TX+2RX
+#TOTAL_CUSTOM_STEP 7+7
+#TX
+0    0x0009    //TX_OPERATION_MODE_0
+1    0x0001    //TX_OPERATION_MODE_1
+2    0x0033    //TX_PATCH_REG
+3    0x2B68    //TX_SENDFUNC_MODE_0
+4    0x0001    //TX_SENDFUNC_MODE_1
+5    0x0001    //TX_NUM_MIC
+6    0x0003    //TX_SAMPLINGFREQ_SIG
+7    0x0003    //TX_SAMPLINGFREQ_PROC
+8    0x000A    //TX_FRAME_SZ_SIG
+9    0x000A    //TX_FRAME_SZ
+10    0x0000    //TX_DELAY_OPT
+11    0x0028    //TX_MAX_TAIL_LENGTH
+12    0x0001    //TX_NUM_LOUTCHN
+13    0x0001    //TX_MAXNUM_AECREF
+14    0x0000    //TX_DBG_FUNC_REG
+15    0x0000    //TX_DBG_FUNC_REG1
+16    0x0000    //TX_SYS_RESRV_0
+17    0x0000    //TX_SYS_RESRV_1
+18    0x0000    //TX_SYS_RESRV_2
+19    0x0000    //TX_SYS_RESRV_3
+20    0x0000    //TX_DIST2REF0
+21    0x009B    //TX_DIST2REF1
+22    0x0000    //TX_DIST2REF_02
+23    0x0000    //TX_DIST2REF_03
+24    0x0000    //TX_DIST2REF_04
+25    0x0000    //TX_DIST2REF_05
+26    0x0000    //TX_MMIC
+27    0x0B80    //TX_PGA_0
+28    0x0800    //TX_PGA_1
+29    0x0800    //TX_PGA_2
+30    0x0000    //TX_PGA_3
+31    0x0000    //TX_PGA_4
+32    0x0000    //TX_PGA_5
+33    0x0000    //TX_MIC_PAIRS
+34    0x0000    //TX_MIC_PAIRS_HS
+35    0x0002    //TX_MICS_FOR_BF
+36    0x0000    //TX_MIC_PAIRS_FORL1
+37    0x0002    //TX_MICS_OF_PAIR0
+38    0x0002    //TX_MICS_OF_PAIR1
+39    0x0002    //TX_MICS_OF_PAIR2
+40    0x0002    //TX_MICS_OF_PAIR3
+41    0x0000    //TX_MIC_DATA_SRC0
+42    0x0001    //TX_MIC_DATA_SRC1
+43    0x0002    //TX_MIC_DATA_SRC2
+44    0x0000    //TX_MIC_DATA_SRC3
+45    0x0000    //TX_MIC_PAIR_CH_04
+46    0x0000    //TX_MIC_PAIR_CH_05
+47    0x0000    //TX_MIC_PAIR_CH_10
+48    0x0000    //TX_MIC_PAIR_CH_11
+49    0x0000    //TX_MIC_PAIR_CH_12
+50    0x0000    //TX_MIC_PAIR_CH_13
+51    0x0000    //TX_MIC_PAIR_CH_14
+52    0x05DC    //TX_HD_BIN_MASK
+53    0x0010    //TX_HD_SUBAND_MASK
+54    0x19A1    //TX_HD_FRAME_AVG_MASK
+55    0x0320    //TX_HD_MIN_FRQ
+56    0x1000    //TX_HD_ALPHA_PSD
+57    0x1100    //TX_T_PHPR1
+58    0x0000    //TX_T_PHPR2
+59    0x0000    //TX_T_PTPR
+60    0x0000    //TX_T_PNPR
+61    0x0000    //TX_T_PAPR1
+62    0xEE6C    //TX_T_PSDVAT
+63    0x0800    //TX_CNT
+64    0x4000    //TX_ANTI_HOWL_GAIN
+65    0x0001    //TX_MICFORBFMARK_0
+66    0x0001    //TX_MICFORBFMARK_1
+67    0x0001    //TX_MICFORBFMARK_2
+68    0x0001    //TX_MICFORBFMARK_3
+69    0x0001    //TX_MICFORBFMARK_4
+70    0x0001    //TX_MICFORBFMARK_5
+71    0x0000    //TX_DIST2REF_10
+72    0x3E00    //TX_DIST2REF_11
+73    0x0000    //TX_DIST2REF2
+74    0x0000    //TX_DIST2REF_13
+75    0x0000    //TX_DIST2REF_14
+76    0x0000    //TX_DIST2REF_15
+77    0x0000    //TX_DIST2REF_20
+78    0x0000    //TX_DIST2REF_21
+79    0x0000    //TX_DIST2REF_22
+80    0x0000    //TX_DIST2REF_23
+81    0x0000    //TX_DIST2REF_24
+82    0x0000    //TX_DIST2REF_25
+83    0x0000    //TX_DIST2REF_30
+84    0x0000    //TX_DIST2REF_31
+85    0x0000    //TX_DIST2REF_32
+86    0x0000    //TX_DIST2REF_33
+87    0x0000    //TX_DIST2REF_34
+88    0x0000    //TX_DIST2REF_35
+89    0x0000    //TX_MIC_LOC_00
+90    0x0000    //TX_MIC_LOC_01
+91    0x0000    //TX_MIC_LOC_02
+92    0x0000    //TX_MIC_LOC_03
+93    0x0000    //TX_MIC_LOC_04
+94    0x0000    //TX_MIC_LOC_05
+95    0x0000    //TX_MIC_LOC_10
+96    0x0000    //TX_MIC_LOC_11
+97    0x0000    //TX_MIC_LOC_12
+98    0x0000    //TX_MIC_LOC_13
+99    0x0000    //TX_MIC_LOC_14
+100    0x0000    //TX_MIC_LOC_15
+101    0x0000    //TX_MIC_LOC_20
+102    0x0000    //TX_MIC_LOC_21
+103    0x0000    //TX_MIC_LOC_22
+104    0x0000    //TX_MIC_LOC_23
+105    0x0000    //TX_MIC_LOC_24
+106    0x0000    //TX_MIC_LOC_25
+107    0x0200    //TX_MIC_REFBLK_VOLUME
+108    0x0800    //TX_MIC_BLOCK_VOLUME
+109    0x0000    //TX_INVERSE_MASK
+110    0x0000    //TX_ADCS_MASK
+111    0x04D0    //TX_ADCS_GAIN
+112    0x4000    //TX_NFC_GAINFAC
+113    0x0000    //TX_MAINMIC_BLKFACTOR
+114    0x0000    //TX_REFMIC_BLKFACTOR
+115    0x0000    //TX_BLMIC_BLKFACTOR
+116    0x0000    //TX_BRMIC_BLKFACTOR
+117    0x0031    //TX_MICBLK_START_BIN
+118    0x0060    //TX_MICBLK_END_BIN
+119    0x0015    //TX_MICBLK_FE_HOLD
+120    0xFFF2    //TX_MICBLK_MR_EXP_TH
+121    0xFFF2    //TX_MICBLK_LR_EXP_TH
+122    0x0000    //TX_FENE_HOLD
+123    0x4000    //TX_FE_ENER_TH_MTS
+124    0x0004    //TX_FE_ENER_TH_EXP
+125    0x6000    //TX_C_POST_FLT_MIC_MAINBLK
+126    0x6000    //TX_C_POST_FLT_MIC_REFBLK
+127    0x0010    //TX_MIC_BLOCK_N
+128    0x7EFF    //TX_A_HP
+129    0x4000    //TX_B_PE
+130    0x1800    //TX_THR_PITCH_DET_0
+131    0x1000    //TX_THR_PITCH_DET_1
+132    0x0800    //TX_THR_PITCH_DET_2
+133    0x0008    //TX_PITCH_BFR_LEN
+134    0x0003    //TX_SBD_PITCH_DET
+135    0x0050    //TX_TD_AEC_L
+136    0x4000    //TX_MU0_UNP_TD_AEC
+137    0x1000    //TX_MU0_PTD_TD_AEC
+138    0x0000    //TX_PP_RESRV_0
+139    0x2A94    //TX_PP_RESRV_1
+140    0x55F0    //TX_PP_RESRV_2
+141    0x0000    //TX_PP_RESRV_3
+142    0x0000    //TX_PP_RESRV_4
+143    0x0000    //TX_PP_RESRV_5
+144    0x0000    //TX_PP_RESRV_6
+145    0x0000    //TX_PP_RESRV_7
+146    0x001E    //TX_TAIL_LENGTH
+147    0x0080    //TX_AEC_REF_GAIN_0
+148    0x0800    //TX_AEC_REF_GAIN_1
+149    0x0800    //TX_AEC_REF_GAIN_2
+150    0x7000    //TX_EAD_THR
+151    0x0800    //TX_THR_RE_EST
+152    0x0800    //TX_MIN_EQ_RE_EST_0
+153    0x0800    //TX_MIN_EQ_RE_EST_1
+154    0x0800    //TX_MIN_EQ_RE_EST_2
+155    0x0800    //TX_MIN_EQ_RE_EST_3
+156    0x0800    //TX_MIN_EQ_RE_EST_4
+157    0x0800    //TX_MIN_EQ_RE_EST_5
+158    0x0800    //TX_MIN_EQ_RE_EST_6
+159    0x0800    //TX_MIN_EQ_RE_EST_7
+160    0x0800    //TX_MIN_EQ_RE_EST_8
+161    0x0800    //TX_MIN_EQ_RE_EST_9
+162    0x0800    //TX_MIN_EQ_RE_EST_10
+163    0x0800    //TX_MIN_EQ_RE_EST_11
+164    0x0800    //TX_MIN_EQ_RE_EST_12
+165    0x4000    //TX_LAMBDA_RE_EST
+166    0x2000    //TX_LAMBDA_CB_NLE
+167    0x6000    //TX_C_POST_FLT
+168    0x7000    //TX_GAIN_NP
+169    0x00C8    //TX_SE_HOLD_N
+170    0x00C8    //TX_DT_HOLD_N
+171    0x03E8    //TX_DT2_HOLD_N
+172    0x6666    //TX_AEC_RESRV_0
+173    0x0000    //TX_AEC_RESRV_1
+174    0x0014    //TX_AEC_RESRV_2
+175    0x0000    //TX_MIC_DELAY_LENGTH
+176    0x0000    //TX_REF_DELAY_LENGTH
+177    0x0000    //TX_ADD_LINEIN_GAINL
+178    0x0000    //TX_ADD_LINEIN_GAINH
+179    0x0000    //TX_MIN_EQ_RE_EST_14
+180    0x0000    //TX_DTD_THR1_8
+181    0x7FFF    //TX_DTD_THR2_8
+182    0x0000    //TX_DTD_MIC_BLK2
+183    0x0008    //TX_FRQ_LIN_LEN
+184    0x7FFF    //TX_FRQ_AEC_LEN_RHO
+185    0x6000    //TX_MU0_UNP_FRQ_AEC
+186    0x4000    //TX_MU0_PTD_FRQ_AEC
+187    0x000A    //TX_MINENOISETH
+188    0x0800    //TX_MU0_RE_EST
+189    0x0001    //TX_AEC_NUM_CH
+190    0x0000    //TX_BIGECHOATTENUATION_MAX
+191    0x2000    //TX_A_POST_FLT_MICBLK
+192    0x0000    //TX_BLKENERTH
+193    0x0000    //TX_BLKENERHIGHTH
+194    0x0000    //TX_NORMENERTH
+195    0x0000    //TX_NORMENERHIGHTH
+196    0x0000    //TX_NORMENERHIGHTHL
+197    0x7800    //TX_DTD_THR1_0
+198    0x7000    //TX_DTD_THR1_1
+199    0x7FFF    //TX_DTD_THR1_2
+200    0x7FFF    //TX_DTD_THR1_3
+201    0x7FFF    //TX_DTD_THR1_4
+202    0x7FFF    //TX_DTD_THR1_5
+203    0x7FFF    //TX_DTD_THR1_6
+204    0x7FFF    //TX_DTD_THR2_0
+205    0x7FFF    //TX_DTD_THR2_1
+206    0x7FFF    //TX_DTD_THR2_2
+207    0x7FFF    //TX_DTD_THR2_3
+208    0x7FFF    //TX_DTD_THR2_4
+209    0x7FFF    //TX_DTD_THR2_5
+210    0x7FFF    //TX_DTD_THR2_6
+211    0x1000    //TX_DTD_THR3
+212    0x0000    //TX_SPK_CUT_K
+213    0x0BB8    //TX_DT_CUT_K
+214    0x0CCD    //TX_DT_CUT_THR
+215    0x04EB    //TX_COMFORT_G
+216    0x01F4    //TX_POWER_YOUT_TH
+217    0x4000    //TX_FDPFGAINECHO
+218    0x0000    //TX_DTD_HD_THR
+219    0x0000    //TX_SPK_CUT_K_S
+220    0x0000    //TX_DTD_MIC_BLK
+221    0x0400    //TX_ADPT_STRICT_L
+222    0x0200    //TX_ADPT_STRICT_H
+223    0x0BB8    //TX_RATIO_DT_L_TH_LOW
+224    0x3A98    //TX_RATIO_DT_H_TH_LOW
+225    0x1770    //TX_RATIO_DT_L_TH_HIGH
+226    0x4E20    //TX_RATIO_DT_H_TH_HIGH
+227    0x09C4    //TX_RATIO_DT_L0_TH
+228    0x0800    //TX_B_POST_FILT_ECHO_L
+229    0x7FFF    //TX_B_POST_FILT_ECHO_H
+230    0x0200    //TX_MIN_G_CTRL_ECHO
+231    0x7FFF    //TX_B_LESSCUT_RTO_ECHO
+232    0x00F0    //TX_EPD_OFFSET_00
+233    0x00F0    //TX_EPD_OFFST_01
+234    0x1388    //TX_RATIO_DT_L0_TH_HIGH
+235    0x3A98    //TX_RATIO_DT_H_TH_CUT
+236    0x7FFF    //TX_MIN_EQ_RE_EST_13
+237    0x7FFF    //TX_DTD_THR1_7
+238    0x7FFF    //TX_DTD_THR2_7
+239    0x0800    //TX_DT_RESRV_7
+240    0x0800    //TX_DT_RESRV_8
+241    0x0000    //TX_DT_RESRV_9
+242    0xFA00    //TX_THR_SN_EST_0
+243    0xF400    //TX_THR_SN_EST_1
+244    0xF600    //TX_THR_SN_EST_2
+245    0xF400    //TX_THR_SN_EST_3
+246    0xF400    //TX_THR_SN_EST_4
+247    0xF400    //TX_THR_SN_EST_5
+248    0xF400    //TX_THR_SN_EST_6
+249    0xF600    //TX_THR_SN_EST_7
+250    0x0000    //TX_DELTA_THR_SN_EST_0
+251    0x0200    //TX_DELTA_THR_SN_EST_1
+252    0x0200    //TX_DELTA_THR_SN_EST_2
+253    0x0200    //TX_DELTA_THR_SN_EST_3
+254    0x0200    //TX_DELTA_THR_SN_EST_4
+255    0x0200    //TX_DELTA_THR_SN_EST_5
+256    0x0000    //TX_DELTA_THR_SN_EST_6
+257    0x0200    //TX_DELTA_THR_SN_EST_7
+258    0x6000    //TX_LAMBDA_NN_EST_0
+259    0x4000    //TX_LAMBDA_NN_EST_1
+260    0x4000    //TX_LAMBDA_NN_EST_2
+261    0x4000    //TX_LAMBDA_NN_EST_3
+262    0x4000    //TX_LAMBDA_NN_EST_4
+263    0x4000    //TX_LAMBDA_NN_EST_5
+264    0x6000    //TX_LAMBDA_NN_EST_6
+265    0x4000    //TX_LAMBDA_NN_EST_7
+266    0x0400    //TX_N_SN_EST
+267    0x001E    //TX_INBEAM_T
+268    0x0041    //TX_INBEAMHOLDT
+269    0x2000    //TX_G_STRICT
+270    0x2000    //TX_EQ_THR_BF
+271    0x799A    //TX_LAMBDA_EQ_BF
+272    0x1000    //TX_NE_RTO_TH
+273    0x0400    //TX_NE_RTO_TH_L
+274    0x0800    //TX_MAINREFRTOH_TH_H
+275    0x0800    //TX_MAINREFRTOH_TH_L
+276    0x0800    //TX_MAINREFRTO_TH_H
+277    0x0800    //TX_MAINREFRTO_TH_L
+278    0x0200    //TX_MAINREFRTO_TH_EQ
+279    0x1000    //TX_B_POST_FLT_0
+280    0x1000    //TX_B_POST_FLT_1
+281    0x000B    //TX_NS_LVL_CTRL_0
+282    0x0011    //TX_NS_LVL_CTRL_1
+283    0x000F    //TX_NS_LVL_CTRL_2
+284    0x000F    //TX_NS_LVL_CTRL_3
+285    0x000F    //TX_NS_LVL_CTRL_4
+286    0x000F    //TX_NS_LVL_CTRL_5
+287    0x000F    //TX_NS_LVL_CTRL_6
+288    0x0011    //TX_NS_LVL_CTRL_7
+289    0x000C    //TX_MIN_GAIN_S_0
+290    0x000F    //TX_MIN_GAIN_S_1
+291    0x000C    //TX_MIN_GAIN_S_2
+292    0x000C    //TX_MIN_GAIN_S_3
+293    0x000C    //TX_MIN_GAIN_S_4
+294    0x000C    //TX_MIN_GAIN_S_5
+295    0x000C    //TX_MIN_GAIN_S_6
+296    0x000F    //TX_MIN_GAIN_S_7
+297    0x7FFF    //TX_NMOS_SUP
+298    0x0000    //TX_NS_MAX_PRI_SNR_TH
+299    0x0000    //TX_NMOS_SUP_MENSA
+300    0x7FFF    //TX_SNRI_SUP_0
+301    0x7FFF    //TX_SNRI_SUP_1
+302    0x7FFF    //TX_SNRI_SUP_2
+303    0x7FFF    //TX_SNRI_SUP_3
+304    0x7FFF    //TX_SNRI_SUP_4
+305    0x7FFF    //TX_SNRI_SUP_5
+306    0x7FFF    //TX_SNRI_SUP_6
+307    0x7FFF    //TX_SNRI_SUP_7
+308    0x7FFF    //TX_THR_LFNS
+309    0x000E    //TX_G_LFNS
+310    0x09C4    //TX_GAIN0_NTH
+311    0x000A    //TX_MUSIC_MORENS
+312    0x7FFF    //TX_A_POST_FILT_0
+313    0x2000    //TX_A_POST_FILT_1
+314    0x2000    //TX_A_POST_FILT_S_0
+315    0x5000    //TX_A_POST_FILT_S_1
+316    0x5000    //TX_A_POST_FILT_S_2
+317    0x5000    //TX_A_POST_FILT_S_3
+318    0x5000    //TX_A_POST_FILT_S_4
+319    0x5000    //TX_A_POST_FILT_S_5
+320    0x4000    //TX_A_POST_FILT_S_6
+321    0x5000    //TX_A_POST_FILT_S_7
+322    0x1000    //TX_B_POST_FILT_0
+323    0x1000    //TX_B_POST_FILT_1
+324    0x1000    //TX_B_POST_FILT_2
+325    0x1000    //TX_B_POST_FILT_3
+326    0x1000    //TX_B_POST_FILT_4
+327    0x1000    //TX_B_POST_FILT_5
+328    0x1000    //TX_B_POST_FILT_6
+329    0x1000    //TX_B_POST_FILT_7
+330    0x7FFF    //TX_B_LESSCUT_RTO_S_0
+331    0x7FFF    //TX_B_LESSCUT_RTO_S_1
+332    0x7FFF    //TX_B_LESSCUT_RTO_S_2
+333    0x7FFF    //TX_B_LESSCUT_RTO_S_3
+334    0x7FFF    //TX_B_LESSCUT_RTO_S_4
+335    0x7FFF    //TX_B_LESSCUT_RTO_S_5
+336    0x7FFF    //TX_B_LESSCUT_RTO_S_6
+337    0x7FFF    //TX_B_LESSCUT_RTO_S_7
+338    0x7900    //TX_LAMBDA_PFILT
+339    0x7B00    //TX_LAMBDA_PFILT_S_0
+340    0x7B00    //TX_LAMBDA_PFILT_S_1
+341    0x7B00    //TX_LAMBDA_PFILT_S_2
+342    0x7B00    //TX_LAMBDA_PFILT_S_3
+343    0x7B00    //TX_LAMBDA_PFILT_S_4
+344    0x7B00    //TX_LAMBDA_PFILT_S_5
+345    0x7B00    //TX_LAMBDA_PFILT_S_6
+346    0x7B00    //TX_LAMBDA_PFILT_S_7
+347    0x0000    //TX_K_PEPPER
+348    0x0800    //TX_A_PEPPER
+349    0x1EAA    //TX_K_PEPPER_HF
+350    0x0800    //TX_A_PEPPER_HF
+351    0x0001    //TX_HMNC_BST_FLG
+352    0x0200    //TX_HMNC_BST_THR
+353    0x0800    //TX_DT_BINVAD_TH_0
+354    0x0800    //TX_DT_BINVAD_TH_1
+355    0x0800    //TX_DT_BINVAD_TH_2
+356    0x0800    //TX_DT_BINVAD_TH_3
+357    0x1D4C    //TX_DT_BINVAD_ENDF
+358    0x0000    //TX_C_POST_FLT_DT
+359    0x0CCD    //TX_NS_B_POST_FLT_LESSCUT
+360    0x0100    //TX_DT_BOOST
+361    0x0000    //TX_BF_SGRAD_FLG
+362    0x0005    //TX_BF_DVG_TH
+363    0x001E    //TX_SN_C_F
+364    0x0000    //TX_K_APT
+365    0x0001    //TX_NOISEDET
+366    0x0190    //TX_NDETCT
+367    0x0383    //TX_NOISE_TH_0
+368    0x7FFF    //TX_NOISE_TH_0_2
+369    0x7FFF    //TX_NOISE_TH_0_3
+370    0x07D0    //TX_NOISE_TH_1
+371    0x00C8    //TX_NOISE_TH_2
+372    0x3A98    //TX_NOISE_TH_3
+373    0x0FA0    //TX_NOISE_TH_4
+374    0x157C    //TX_NOISE_TH_5
+375    0x7FFF    //TX_NOISE_TH_5_2
+376    0x7FFF    //TX_NOISE_TH_5_3
+377    0x7FFF    //TX_NOISE_TH_5_4
+378    0x044C    //TX_NOISE_TH_6
+379    0x044C    //TX_MINENOISE_TH
+380    0xD508    //TX_MORENS_TFMASK_TH
+381    0x0001    //TX_DRC_QUIET_FLOOR
+382    0x3A98    //TX_RATIODTL_CUT_TH
+383    0x0DAC    //TX_DT_CUT_K1
+384    0x0666    //TX_OUT_ENER_S_TH_CLEAN
+385    0x0666    //TX_OUT_ENER_S_TH_LESSCLEAN
+386    0x0333    //TX_OUT_ENER_S_TH_NOISY
+387    0x019A    //TX_OUT_ENER_TH_NOISE
+388    0x0333    //TX_OUT_ENER_TH_SPEECH
+389    0x2000    //TX_SN_NPB_GAIN
+390    0x0000    //TX_NN_NPB_GAIN
+391    0x7FFF    //TX_POST_MASK_SUP_HSNE
+392    0x1388    //TX_TAIL_DET_TH
+393    0x4000    //TX_B_LESSCUT_RTO_WTA
+394    0x0000    //TX_MEL_G_R
+395    0x0080    //TX_SUPHIGH_TH
+396    0x0000    //TX_MASK_G_R
+397    0x0002    //TX_EXTRA_NS_L
+398    0x1800    //TX_C_POST_FLT_MASK
+399    0x7FFF    //TX_A_POST_FLT_WNS
+400    0x0148    //TX_MIN_G_LOW300HZ
+401    0x0002    //TX_MAXLEVEL_CNG
+402    0x00B4    //TX_STN_NOISE_TH
+403    0x4000    //TX_POST_MASK_SUP
+404    0x7FFF    //TX_POST_MASK_ADJUST
+405    0x00C8    //TX_NS_ENOISE_MIC0_TH
+406    0x02F3    //TX_MINENOISE_MIC0_TH
+407    0x012C    //TX_MINENOISE_MIC0_S_TH
+408    0x2900    //TX_MIN_G_CTRL_SSNS
+409    0x0800    //TX_METAL_RTO_THR
+410    0x4848    //TX_NS_FP_K_METAL
+411    0x3A98    //TX_NOISEDET_BOOST_TH
+412    0x0FA0    //TX_NSMOOTH_TH
+413    0x0000    //TX_NS_RESRV_8
+414    0x1800    //TX_RHO_UPB
+415    0x0BB8    //TX_N_HOLD_HS
+416    0x0050    //TX_N_RHO_BFR0
+417    0x7FFF    //TX_LAMBDA_ARSP_EST
+418    0x0100    //TX_EXTRA_GAIN_MICBLOCK
+419    0x0CCD    //TX_THR_STD_NSR
+420    0x019A    //TX_THR_STD_PLH
+421    0x2AF8    //TX_N_HOLD_STD
+422    0x0066    //TX_THR_STD_RHO
+423    0x2000    //TX_BF_RESET_THR_HS
+424    0x09C4    //TX_SB_RTO_MEAN_TH
+425    0x0000    //TX_SB_RHO_MEAN_TH_NTALK
+426    0x3800    //TX_SB_RTO_MEAN_TH_ABN
+427    0x2EE0    //TX_SB_RTO_MEAN_TH_RUB
+428    0x0000    //TX_WTA_EN_RTO_TH
+429    0x0000    //TX_TOP_ENER_TH_F
+430    0x0000    //TX_DESIRED_TALK_HOLDT
+431    0x0800    //TX_MIC_BLOCK_FACTOR
+432    0x0000    //TX_NSEST_BFRLRNRDC
+433    0x0000    //TX_THR_POST_FLT_HS
+434    0x0010    //TX_HS_VAD_BIN
+435    0x2666    //TX_THR_VAD_HS
+436    0x2CCD    //TX_MEAN_RTO_MIN_TH2
+437    0x0032    //TX_SILENCE_T
+438    0x0000    //TX_A_POST_FLT_WTA
+439    0x799A    //TX_LAMBDA_PFLT_WTA
+440    0x0000    //TX_SB_RHO_MEAN2_TH
+441    0x0190    //TX_SB_RHO_MEAN3_TH
+442    0x0000    //TX_HS_RESRV_4
+443    0x0000    //TX_HS_RESRV_5
+444    0x003C    //TX_DOA_VAD_THR_1
+445    0x0000    //TX_DOA_VAD_THR_2
+446    0x0028    //TX_DOA_VAD_THR1_0
+447    0x0028    //TX_DOA_VAD_THR1_1
+448    0x0000    //TX_SRC_DOA_RNG_LOW_0A
+449    0x00B4    //TX_SRC_DOA_RNG_HIGH_0A
+450    0x005A    //TX_DFLT_SRC_DOA_0A
+451    0x0000    //TX_SRC_DOA_RNG_LOW_0B
+452    0x0000    //TX_SRC_DOA_RNG_HIGH_0B
+453    0x0000    //TX_DFLT_SRC_DOA_0B
+454    0x0000    //TX_SRC_DOA_RNG_LOW_0C
+455    0x0000    //TX_SRC_DOA_RNG_HIGH_0C
+456    0x0000    //TX_DFLT_SRC_DOA_0C
+457    0x0000    //TX_SRC_DOA_RNG_LOW_0D
+458    0x0000    //TX_SRC_DOA_RNG_HIGH_0D
+459    0x0000    //TX_DFLT_SRC_DOA_0D
+460    0x0000    //TX_SRC_DOA_RNG_LOW_1A
+461    0x00B4    //TX_SRC_DOA_RNG_HIGH_1A
+462    0x005A    //TX_DFLT_SRC_DOA_1A
+463    0x0000    //TX_SRC_DOA_RNG_LOW_1B
+464    0x00B4    //TX_SRC_DOA_RNG_HIGH_1B
+465    0x005A    //TX_DFLT_SRC_DOA_1B
+466    0x0000    //TX_SRC_DOA_RNG_LOW_1C
+467    0x00B4    //TX_SRC_DOA_RNG_HIGH_1C
+468    0x005A    //TX_DFLT_SRC_DOA_1C
+469    0x0000    //TX_SRC_DOA_RNG_LOW_1D
+470    0x00B4    //TX_SRC_DOA_RNG_HIGH_1D
+471    0x005A    //TX_DFLT_SRC_DOA_1D
+472    0x0100    //TX_BF_HOLDOFF_T
+473    0x7FFF    //TX_DOA_COST_FACTOR
+474    0x4000    //TX_MAINTOREFR_TH0
+475    0x071C    //TX_DOA_TRK_THR
+476    0x012C    //TX_DOA_TRACK_HT
+477    0x0200    //TX_N1_HOLD_HF
+478    0x0100    //TX_N2_HOLD_HF
+479    0x3000    //TX_BF_RESET_THR_HF
+480    0x7333    //TX_DOA_SMOOTH
+481    0x0800    //TX_MU_BF
+482    0x0800    //TX_BF_MU_LF_B2
+483    0x0040    //TX_BF_FC_END_BIN_B2
+484    0x0020    //TX_BF_FC_END_BIN
+485    0x0000    //TX_HF_RESRV_25
+486    0x0000    //TX_HF_RESRV_26
+487    0x0007    //TX_N_DOA_SEED
+488    0x0001    //TX_FINE_DOA_SEARCH_FLG
+489    0x0000    //TX_HF_RESRV_27
+490    0x038E    //TX_DLT_SRC_DOA_RNG
+491    0x0200    //TX_BF_MU_LF
+492    0x0000    //TX_DFLT_SRC_LOC_0
+493    0x7FFF    //TX_DFLT_SRC_LOC_1
+494    0x0000    //TX_DFLT_SRC_LOC_2
+495    0x038E    //TX_DOA_TRACK_VADTH
+496    0x0000    //TX_DOA_TRACK_NEW
+497    0x01E0    //TX_NOR_OFF_THR
+498    0x7C00    //TX_MORE_ON_700HZ_THR
+499    0x2000    //TX_MU_BF_ADPT_NS
+500    0x0000    //TX_ADAPT_LEN
+501    0x6666    //TX_MORE_SNS
+502    0x0000    //TX_NOR_OFF_TH1
+503    0x0000    //TX_WIDE_MASK_TH
+504    0xD333    //TX_SUBSNRATIOHIGH4MEANBCK_THR
+505    0x6000    //TX_C_POST_FLT_CUT
+506    0x2000    //TX_RADIODTLV
+507    0x0320    //TX_POWER_LINEIN_TH
+508    0x0014    //TX_FE_VADCOUNT_TH_FC
+509    0x0000    //TX_ECHO_SUPP_FC
+510    0x0C80    //TX_ECHO_TH
+511    0x6666    //TX_MIC_TO_BFGAIN
+512    0x0000    //TX_MICTOBFGAIN0
+513    0x0000    //TX_FASTMUE_TH
+514    0xC000    //TX_DEREVERB_LF_MU
+515    0xC000    //TX_DEREVERB_HF_MU
+516    0xCCCC    //TX_DEREVERB_DELAY
+517    0xD999    //TX_DEREVERB_COEF_LEN
+518    0x1F40    //TX_DEREVERB_DNR
+519    0x0000    //TX_DEREVERB_ALPHA
+520    0x0000    //TX_DEREVERB_BETA
+521    0x0000    //TX_GSC_RTOL_TH
+522    0x7000    //TX_GSC_RTOH_TH
+523    0x0064    //TX_WIDE2_MEANHTH
+524    0x0000    //TX_DR_RESRV_5
+525    0x0000    //TX_DR_RESRV_6
+526    0x0000    //TX_DR_RESRV_7
+527    0x0000    //TX_DR_RESRV_8
+528    0x1333    //TX_WIND_MARK_TH
+529    0x399A    //TX_CORR_THR
+530    0x0004    //TX_SNR_THR
+531    0x0010    //TX_ENGY_THR
+532    0x1770    //TX_CORR_HIGH_TH
+533    0x6000    //TX_ENGY_THR_2
+534    0x3400    //TX_MEAN_RTO_THR
+535    0x0028    //TX_WNS_ENOISE_MIC0_TH
+536    0x3000    //TX_RATIOMICL_TH
+537    0x64CD    //TX_CALIG_HS
+538    0x0000    //TX_LVL_CTRL
+539    0x0014    //TX_WIND_SUPRTO
+540    0x000A    //TX_WNS_MIN_G
+541    0x0000    //TX_WNS_B_POST_FLT
+542    0x2800    //TX_RATIOMICH_TH
+543    0xD120    //TX_WIND_INBEAM_L_TH
+544    0x0FA0    //TX_WIND_INBEAM_H_TH
+545    0x2000    //TX_WNS_RESRV_0
+546    0x59D8    //TX_WNS_RESRV_1
+547    0x0000    //TX_WNS_RESRV_2
+548    0x0000    //TX_WNS_RESRV_3
+549    0x0000    //TX_WNS_RESRV_4
+550    0x0000    //TX_WNS_RESRV_5
+551    0x0000    //TX_WNS_RESRV_6
+552    0x0000    //TX_BVE_NOISE_FLOOR_0
+553    0x0070    //TX_BVE_NOISE_FLOOR_1
+554    0x0070    //TX_BVE_NOISE_FLOOR_2
+555    0x0010    //TX_BVE_NOISE_FLOOR_3
+556    0x0070    //TX_BVE_NOISE_FLOOR_4
+557    0x00B0    //TX_BVE_NOISE_FLOOR_5
+558    0x0E66    //TX_BVE_NOISE_FLOOR_6
+559    0x0050    //TX_BVE_NOISE_FLOOR_7
+560    0x770A    //TX_BVE_NOISE_FLOOR_8
+561    0x0000    //TX_BVE_NOISE_FLOOR_9
+562    0x0000    //TX_BVE_IN_N
+563    0x0000    //TX_BVE_OUT_N
+564    0x0000    //TX_BVE_MICALPHA_DOWN
+565    0x0000    //TX_PB_RESRV_1
+566    0x0020    //TX_FDEQ_SUBNUM
+567    0x4848    //TX_FDEQ_GAIN_0
+568    0x4848    //TX_FDEQ_GAIN_1
+569    0x4848    //TX_FDEQ_GAIN_2
+570    0x4848    //TX_FDEQ_GAIN_3
+571    0x4848    //TX_FDEQ_GAIN_4
+572    0x4848    //TX_FDEQ_GAIN_5
+573    0x4848    //TX_FDEQ_GAIN_6
+574    0x4848    //TX_FDEQ_GAIN_7
+575    0x4848    //TX_FDEQ_GAIN_8
+576    0x4848    //TX_FDEQ_GAIN_9
+577    0x4848    //TX_FDEQ_GAIN_10
+578    0x4848    //TX_FDEQ_GAIN_11
+579    0x4848    //TX_FDEQ_GAIN_12
+580    0x4848    //TX_FDEQ_GAIN_13
+581    0x4848    //TX_FDEQ_GAIN_14
+582    0x4848    //TX_FDEQ_GAIN_15
+583    0x4848    //TX_FDEQ_GAIN_16
+584    0x4848    //TX_FDEQ_GAIN_17
+585    0x4848    //TX_FDEQ_GAIN_18
+586    0x4848    //TX_FDEQ_GAIN_19
+587    0x4848    //TX_FDEQ_GAIN_20
+588    0x4848    //TX_FDEQ_GAIN_21
+589    0x4848    //TX_FDEQ_GAIN_22
+590    0x4848    //TX_FDEQ_GAIN_23
+591    0x0202    //TX_FDEQ_BIN_0
+592    0x0203    //TX_FDEQ_BIN_1
+593    0x0303    //TX_FDEQ_BIN_2
+594    0x0304    //TX_FDEQ_BIN_3
+595    0x0405    //TX_FDEQ_BIN_4
+596    0x0506    //TX_FDEQ_BIN_5
+597    0x0708    //TX_FDEQ_BIN_6
+598    0x090A    //TX_FDEQ_BIN_7
+599    0x0B0C    //TX_FDEQ_BIN_8
+600    0x0D0E    //TX_FDEQ_BIN_9
+601    0x1013    //TX_FDEQ_BIN_10
+602    0x1719    //TX_FDEQ_BIN_11
+603    0x1B1E    //TX_FDEQ_BIN_12
+604    0x1E1E    //TX_FDEQ_BIN_13
+605    0x1E28    //TX_FDEQ_BIN_14
+606    0x282C    //TX_FDEQ_BIN_15
+607    0x0000    //TX_FDEQ_BIN_16
+608    0x0000    //TX_FDEQ_BIN_17
+609    0x0000    //TX_FDEQ_BIN_18
+610    0x0000    //TX_FDEQ_BIN_19
+611    0x0000    //TX_FDEQ_BIN_20
+612    0x0000    //TX_FDEQ_BIN_21
+613    0x0000    //TX_FDEQ_BIN_22
+614    0x0000    //TX_FDEQ_BIN_23
+615    0x0000    //TX_FDEQ_PADDING
+616    0x0020    //TX_PREEQ_SUBNUM_MIC0
+617    0x4848    //TX_PREEQ_GAIN_MIC0_0
+618    0x4848    //TX_PREEQ_GAIN_MIC0_1
+619    0x4848    //TX_PREEQ_GAIN_MIC0_2
+620    0x4848    //TX_PREEQ_GAIN_MIC0_3
+621    0x4848    //TX_PREEQ_GAIN_MIC0_4
+622    0x4848    //TX_PREEQ_GAIN_MIC0_5
+623    0x4848    //TX_PREEQ_GAIN_MIC0_6
+624    0x4848    //TX_PREEQ_GAIN_MIC0_7
+625    0x4868    //TX_PREEQ_GAIN_MIC0_8
+626    0x6860    //TX_PREEQ_GAIN_MIC0_9
+627    0x6048    //TX_PREEQ_GAIN_MIC0_10
+628    0x4848    //TX_PREEQ_GAIN_MIC0_11
+629    0x4848    //TX_PREEQ_GAIN_MIC0_12
+630    0x4848    //TX_PREEQ_GAIN_MIC0_13
+631    0x4848    //TX_PREEQ_GAIN_MIC0_14
+632    0x4848    //TX_PREEQ_GAIN_MIC0_15
+633    0x4848    //TX_PREEQ_GAIN_MIC0_16
+634    0x4848    //TX_PREEQ_GAIN_MIC0_17
+635    0x4848    //TX_PREEQ_GAIN_MIC0_18
+636    0x4848    //TX_PREEQ_GAIN_MIC0_19
+637    0x4848    //TX_PREEQ_GAIN_MIC0_20
+638    0x4848    //TX_PREEQ_GAIN_MIC0_21
+639    0x4848    //TX_PREEQ_GAIN_MIC0_22
+640    0x4848    //TX_PREEQ_GAIN_MIC0_23
+641    0x0E10    //TX_PREEQ_BIN_MIC0_0
+642    0x1010    //TX_PREEQ_BIN_MIC0_1
+643    0x1010    //TX_PREEQ_BIN_MIC0_2
+644    0x1010    //TX_PREEQ_BIN_MIC0_3
+645    0x1010    //TX_PREEQ_BIN_MIC0_4
+646    0x1010    //TX_PREEQ_BIN_MIC0_5
+647    0x1010    //TX_PREEQ_BIN_MIC0_6
+648    0x1010    //TX_PREEQ_BIN_MIC0_7
+649    0x1010    //TX_PREEQ_BIN_MIC0_8
+650    0x1010    //TX_PREEQ_BIN_MIC0_9
+651    0x1010    //TX_PREEQ_BIN_MIC0_10
+652    0x1010    //TX_PREEQ_BIN_MIC0_11
+653    0x1010    //TX_PREEQ_BIN_MIC0_12
+654    0x1010    //TX_PREEQ_BIN_MIC0_13
+655    0x1010    //TX_PREEQ_BIN_MIC0_14
+656    0x0200    //TX_PREEQ_BIN_MIC0_15
+657    0x0000    //TX_PREEQ_BIN_MIC0_16
+658    0x0000    //TX_PREEQ_BIN_MIC0_17
+659    0x0000    //TX_PREEQ_BIN_MIC0_18
+660    0x0000    //TX_PREEQ_BIN_MIC0_19
+661    0x0000    //TX_PREEQ_BIN_MIC0_20
+662    0x0000    //TX_PREEQ_BIN_MIC0_21
+663    0x0000    //TX_PREEQ_BIN_MIC0_22
+664    0x0000    //TX_PREEQ_BIN_MIC0_23
+665    0x0020    //TX_PREEQ_SUBNUM_MIC1
+666    0x4848    //TX_PREEQ_GAIN_MIC1_0
+667    0x4848    //TX_PREEQ_GAIN_MIC1_1
+668    0x4848    //TX_PREEQ_GAIN_MIC1_2
+669    0x4848    //TX_PREEQ_GAIN_MIC1_3
+670    0x4848    //TX_PREEQ_GAIN_MIC1_4
+671    0x4848    //TX_PREEQ_GAIN_MIC1_5
+672    0x4848    //TX_PREEQ_GAIN_MIC1_6
+673    0x4848    //TX_PREEQ_GAIN_MIC1_7
+674    0x4848    //TX_PREEQ_GAIN_MIC1_8
+675    0x4848    //TX_PREEQ_GAIN_MIC1_9
+676    0x4848    //TX_PREEQ_GAIN_MIC1_10
+677    0x4848    //TX_PREEQ_GAIN_MIC1_11
+678    0x4848    //TX_PREEQ_GAIN_MIC1_12
+679    0x4848    //TX_PREEQ_GAIN_MIC1_13
+680    0x4848    //TX_PREEQ_GAIN_MIC1_14
+681    0x4848    //TX_PREEQ_GAIN_MIC1_15
+682    0x4848    //TX_PREEQ_GAIN_MIC1_16
+683    0x4848    //TX_PREEQ_GAIN_MIC1_17
+684    0x4848    //TX_PREEQ_GAIN_MIC1_18
+685    0x4848    //TX_PREEQ_GAIN_MIC1_19
+686    0x4848    //TX_PREEQ_GAIN_MIC1_20
+687    0x4848    //TX_PREEQ_GAIN_MIC1_21
+688    0x4848    //TX_PREEQ_GAIN_MIC1_22
+689    0x4848    //TX_PREEQ_GAIN_MIC1_23
+690    0x0E10    //TX_PREEQ_BIN_MIC1_0
+691    0x1010    //TX_PREEQ_BIN_MIC1_1
+692    0x1010    //TX_PREEQ_BIN_MIC1_2
+693    0x1010    //TX_PREEQ_BIN_MIC1_3
+694    0x1010    //TX_PREEQ_BIN_MIC1_4
+695    0x1010    //TX_PREEQ_BIN_MIC1_5
+696    0x1010    //TX_PREEQ_BIN_MIC1_6
+697    0x1010    //TX_PREEQ_BIN_MIC1_7
+698    0x1010    //TX_PREEQ_BIN_MIC1_8
+699    0x1010    //TX_PREEQ_BIN_MIC1_9
+700    0x1010    //TX_PREEQ_BIN_MIC1_10
+701    0x1010    //TX_PREEQ_BIN_MIC1_11
+702    0x1010    //TX_PREEQ_BIN_MIC1_12
+703    0x1010    //TX_PREEQ_BIN_MIC1_13
+704    0x1010    //TX_PREEQ_BIN_MIC1_14
+705    0x0200    //TX_PREEQ_BIN_MIC1_15
+706    0x0000    //TX_PREEQ_BIN_MIC1_16
+707    0x0000    //TX_PREEQ_BIN_MIC1_17
+708    0x0000    //TX_PREEQ_BIN_MIC1_18
+709    0x0000    //TX_PREEQ_BIN_MIC1_19
+710    0x0000    //TX_PREEQ_BIN_MIC1_20
+711    0x0000    //TX_PREEQ_BIN_MIC1_21
+712    0x0000    //TX_PREEQ_BIN_MIC1_22
+713    0x0000    //TX_PREEQ_BIN_MIC1_23
+714    0x0020    //TX_PREEQ_SUBNUM_MIC2
+715    0x4848    //TX_PREEQ_GAIN_MIC2_0
+716    0x4848    //TX_PREEQ_GAIN_MIC2_1
+717    0x4848    //TX_PREEQ_GAIN_MIC2_2
+718    0x4848    //TX_PREEQ_GAIN_MIC2_3
+719    0x4848    //TX_PREEQ_GAIN_MIC2_4
+720    0x4848    //TX_PREEQ_GAIN_MIC2_5
+721    0x4848    //TX_PREEQ_GAIN_MIC2_6
+722    0x4848    //TX_PREEQ_GAIN_MIC2_7
+723    0x4848    //TX_PREEQ_GAIN_MIC2_8
+724    0x4848    //TX_PREEQ_GAIN_MIC2_9
+725    0x4848    //TX_PREEQ_GAIN_MIC2_10
+726    0x4848    //TX_PREEQ_GAIN_MIC2_11
+727    0x4848    //TX_PREEQ_GAIN_MIC2_12
+728    0x4848    //TX_PREEQ_GAIN_MIC2_13
+729    0x4848    //TX_PREEQ_GAIN_MIC2_14
+730    0x4848    //TX_PREEQ_GAIN_MIC2_15
+731    0x4848    //TX_PREEQ_GAIN_MIC2_16
+732    0x4848    //TX_PREEQ_GAIN_MIC2_17
+733    0x4848    //TX_PREEQ_GAIN_MIC2_18
+734    0x4848    //TX_PREEQ_GAIN_MIC2_19
+735    0x4848    //TX_PREEQ_GAIN_MIC2_20
+736    0x4848    //TX_PREEQ_GAIN_MIC2_21
+737    0x4848    //TX_PREEQ_GAIN_MIC2_22
+738    0x4848    //TX_PREEQ_GAIN_MIC2_23
+739    0x0E10    //TX_PREEQ_BIN_MIC2_0
+740    0x1010    //TX_PREEQ_BIN_MIC2_1
+741    0x1010    //TX_PREEQ_BIN_MIC2_2
+742    0x1010    //TX_PREEQ_BIN_MIC2_3
+743    0x1010    //TX_PREEQ_BIN_MIC2_4
+744    0x1010    //TX_PREEQ_BIN_MIC2_5
+745    0x1010    //TX_PREEQ_BIN_MIC2_6
+746    0x1010    //TX_PREEQ_BIN_MIC2_7
+747    0x1010    //TX_PREEQ_BIN_MIC2_8
+748    0x1010    //TX_PREEQ_BIN_MIC2_9
+749    0x1010    //TX_PREEQ_BIN_MIC2_10
+750    0x1010    //TX_PREEQ_BIN_MIC2_11
+751    0x1010    //TX_PREEQ_BIN_MIC2_12
+752    0x1010    //TX_PREEQ_BIN_MIC2_13
+753    0x1010    //TX_PREEQ_BIN_MIC2_14
+754    0x0200    //TX_PREEQ_BIN_MIC2_15
+755    0x0000    //TX_PREEQ_BIN_MIC2_16
+756    0x0000    //TX_PREEQ_BIN_MIC2_17
+757    0x0000    //TX_PREEQ_BIN_MIC2_18
+758    0x0000    //TX_PREEQ_BIN_MIC2_19
+759    0x0000    //TX_PREEQ_BIN_MIC2_20
+760    0x0000    //TX_PREEQ_BIN_MIC2_21
+761    0x0000    //TX_PREEQ_BIN_MIC2_22
+762    0x0000    //TX_PREEQ_BIN_MIC2_23
+763    0x0006    //TX_MASKING_ABILITY
+764    0x0800    //TX_NND_WEIGHT
+765    0x0062    //TX_MIC_CALIBRATION_0
+766    0x0062    //TX_MIC_CALIBRATION_1
+767    0x0062    //TX_MIC_CALIBRATION_2
+768    0x0062    //TX_MIC_CALIBRATION_3
+769    0x0046    //TX_MIC_PWR_BIAS_0
+770    0x0046    //TX_MIC_PWR_BIAS_1
+771    0x0046    //TX_MIC_PWR_BIAS_2
+772    0x0046    //TX_MIC_PWR_BIAS_3
+773    0x000C    //TX_GAIN_LIMIT_0
+774    0x000C    //TX_GAIN_LIMIT_1
+775    0x000C    //TX_GAIN_LIMIT_2
+776    0x000C    //TX_GAIN_LIMIT_3
+777    0x7F5B    //TX_BVE_NOVAD0_ALPHADOWN
+778    0x7FDE    //TX_BVE_VAD0_ALPHAUP
+779    0x7F3A    //TX_BVE_VAD0_ALPHADOWN
+780    0x2000    //TX_BVE_GAINWEIGHT_NOFEVADLI
+781    0x7F5B    //TX_BVE_FEVADLI_ALPHA
+782    0x7F19    //TX_BVE_NOVAD0_ALPHAUP
+783    0x3000    //TX_TDDRC_ALPHA_UP_01
+784    0x3000    //TX_TDDRC_ALPHA_UP_02
+785    0x3000    //TX_TDDRC_ALPHA_UP_03
+786    0x3000    //TX_TDDRC_ALPHA_UP_04
+787    0x7EB8    //TX_TDDRC_ALPHA_DWN_01
+788    0x7EB8    //TX_TDDRC_ALPHA_DWN_02
+789    0x7EB8    //TX_TDDRC_ALPHA_DWN_03
+790    0x7EB8    //TX_TDDRC_ALPHA_DWN_04
+791    0x78D6    //TX_TDDRC_TD_DRC_LIMIT
+792    0x0800    //TX_TDDRC_POST_LIMIT_GAIN
+793    0x0000    //TX_TDDRC_RESRV_0
+794    0x0000    //TX_TDDRC_RESRV_1
+795    0x0018    //TX_FDDRC_BAND_MARGIN_0
+796    0x0030    //TX_FDDRC_BAND_MARGIN_1
+797    0x0050    //TX_FDDRC_BAND_MARGIN_2
+798    0x0080    //TX_FDDRC_BAND_MARGIN_3
+799    0x0007    //TX_FDDRC_BLOCK_EXP
+800    0x5000    //TX_FDDRC_THRD_2_0
+801    0x5000    //TX_FDDRC_THRD_2_1
+802    0x5000    //TX_FDDRC_THRD_2_2
+803    0x5000    //TX_FDDRC_THRD_2_3
+804    0x6400    //TX_FDDRC_THRD_3_0
+805    0x6400    //TX_FDDRC_THRD_3_1
+806    0x6400    //TX_FDDRC_THRD_3_2
+807    0x6400    //TX_FDDRC_THRD_3_3
+808    0x2000    //TX_FDDRC_SLANT_0_0
+809    0x2000    //TX_FDDRC_SLANT_0_1
+810    0x2000    //TX_FDDRC_SLANT_0_2
+811    0x2000    //TX_FDDRC_SLANT_0_3
+812    0x5333    //TX_FDDRC_SLANT_1_0
+813    0x5333    //TX_FDDRC_SLANT_1_1
+814    0x5333    //TX_FDDRC_SLANT_1_2
+815    0x5333    //TX_FDDRC_SLANT_1_3
+816    0x0000    //TX_DEADMIC_SILENCE_TH
+817    0x0000    //TX_MIC_DEGRADE_TH
+818    0x0000    //TX_DEADMIC_CNT
+819    0x0000    //TX_MIC_DEGRADE_CNT
+820    0x0000    //TX_FDDRC_RESRV_4
+821    0x0000    //TX_FDDRC_RESRV_5
+822    0x0000    //TX_FDDRC_RESRV_6
+823    0x7FFF    //TX_KS_NOISEPASTE_FACTOR
+824    0x0001    //TX_KS_CONFIG
+825    0x7FFF    //TX_KS_GAIN_MIN
+826    0x0000    //TX_KS_RESRV_0
+827    0x0000    //TX_KS_RESRV_1
+828    0x0000    //TX_KS_RESRV_2
+829    0x7C00    //TX_LAMBDA_PKA_FP
+830    0x2000    //TX_TPKA_FP
+831    0x0080    //TX_MIN_G_FP
+832    0x2000    //TX_MAX_G_FP
+833    0x4848    //TX_FFP_FP_K_METAL
+834    0x4000    //TX_A_POST_FLT_FP
+835    0x0F5C    //TX_RTO_OUTBEAM_TH
+836    0x4CCD    //TX_TPKA_FP_THD
+837    0x0000    //TX_MAX_G_FP_BLK
+838    0x0000    //TX_FFP_FADEIN
+839    0x0000    //TX_FFP_FADEOUT
+840    0x0000    //TX_WHISPERCTH
+841    0x0000    //TX_WHISPERHOLDT
+842    0x0000    //TX_WHISP_ENTHH
+843    0x0000    //TX_WHISP_ENTHL
+844    0x0000    //TX_WHISP_RTOTH
+845    0x0000    //TX_WHISP_RTOTH2
+846    0x0000    //TX_MUTE_PERIOD
+847    0x0000    //TX_FADE_IN_PERIOD
+848    0x0100    //TX_FFP_RESRV_2
+849    0x0020    //TX_FFP_RESRV_3
+850    0x0000    //TX_FFP_RESRV_4
+851    0x0000    //TX_FFP_RESRV_5
+852    0x0000    //TX_FFP_RESRV_6
+853    0x0000    //TX_FILTINDX
+854    0x0000    //TX_TDDRC_THRD_0
+855    0x0000    //TX_TDDRC_THRD_1
+856    0x2000    //TX_TDDRC_THRD_2
+857    0x2000    //TX_TDDRC_THRD_3
+858    0x3000    //TX_TDDRC_SLANT_0
+859    0x6E00    //TX_TDDRC_SLANT_1
+860    0x3000    //TX_TDDRC_ALPHA_UP_00
+861    0x7EB8    //TX_TDDRC_ALPHA_DWN_00
+862    0x0000    //TX_TDDRC_HMNC_FLAG
+863    0x199A    //TX_TDDRC_HMNC_GAIN
+864    0x0000    //TX_TDDRC_SMT_FLAG
+865    0x0CCD    //TX_TDDRC_SMT_W
+866    0x05A0    //TX_TDDRC_DRC_GAIN
+867    0x78D6    //TX_TDDRC_LMT_THRD
+868    0x0000    //TX_TDDRC_LMT_ALPHA
+869    0x0000    //TX_TFMASKLTH
+870    0x0000    //TX_TFMASKLTHL
+871    0x0CCD    //TX_TFMASKHTH
+872    0x0CCD    //TX_TFMASKLTH_BINVAD
+873    0xF333    //TX_TFMASKLTH_NS_EST
+874    0x2CCD    //TX_TFMASKLTH_DOA
+875    0xECCD    //TX_TFMASKTH_BLESSCUT
+876    0x1000    //TX_B_LESSCUT_RTO_MASK
+877    0x3800    //TX_SB_RHO_MEAN_TH_ABN
+878    0x2000    //TX_B_POST_FLT_MASK
+879    0x0000    //TX_B_POST_FLT_MASK1
+880    0x5333    //TX_GAIN_WIND_MASK
+881    0x7FFF    //TX_TFMASK_BFSTRICT_MUSIC
+882    0x0000    //TX_TFMASK_BFSTRICT_NOMUSIC
+883    0x7333    //TX_FASTNS_OUTIN_TH
+884    0x0CCD    //TX_FASTNS_TFMASK_TH
+885    0x0CCD    //TX_FASTNS_TFMASKBIN_TH1
+886    0x0CCD    //TX_FASTNS_TFMASKBIN_TH2
+887    0x0CCD    //TX_FASTNS_TFMASKBIN_TH3
+888    0x0028    //TX_FASTNS_ARSPC_TH
+889    0x8000    //TX_FASTNS_MASK5_TH
+890    0x4848    //TX_POSTSSA_MIN_G_VR_MASK
+891    0x4000    //TX_A_LESSCUT_RTO_MASK
+892    0x1770    //TX_FASTNS_NOISETH
+893    0xC000    //TX_FASTNS_SSA_THLFL
+894    0xC000    //TX_FASTNS_SSA_THHFL
+895    0xCCCC    //TX_FASTNS_SSA_THLFH
+896    0xD999    //TX_FASTNS_SSA_THHFH
+897    0x2339    //TX_SENDFUNC_REG_MICMUTE
+898    0x0021    //TX_SENDFUNC_REG_MICMUTE1
+899    0x02BC    //TX_MICMUTE_RATIO_THR
+900    0x0140    //TX_MICMUTE_AMP_THR
+901    0x0004    //TX_MICMUTE_HPF_IND
+902    0x00C0    //TX_MICMUTE_LOG_EYR_TH
+903    0x0008    //TX_MICMUTE_CVG_TIME
+904    0x0008    //TX_MICMUTE_RELEASE_TIME
+905    0x01FE    //TX_MIC_VOLUME_MIC0MUTE
+906    0x0020    //TX_MICMUTE_EPD_OFFSET_0
+907    0x001E    //TX_MICMUTE_FRQ_AEC_L
+908    0x7999    //TX_MICMUTE_EAD_THR
+909    0x7FFF    //TX_MICMUTE_LAMBDA_CB_NLE
+910    0x7FFF    //TX_MICMUTE_LAMBDA_RE_EST
+911    0x4000    //TX_DTD_THR1_MICMUTE_0
+912    0x7000    //TX_DTD_THR1_MICMUTE_1
+913    0x7FFF    //TX_DTD_THR1_MICMUTE_2
+914    0x7FFF    //TX_DTD_THR1_MICMUTE_3
+915    0x6CCC    //TX_DTD_THR2_MICMUTE_0
+916    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_0
+917    0x0400    //TX_MICMUTE_MIN_EQ_RE_EST_1
+918    0x1000    //TX_MICMUTE_MIN_EQ_RE_EST_2
+919    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_3
+920    0x7FFF    //TX_MICMUTE_MIN_EQ_RE_EST_4
+921    0x4000    //TX_MICMUTE_C_POST_FLT
+922    0x03E8    //TX_MICMUTE_DT_CUT_K
+923    0x0001    //TX_MICMUTE_DT_CUT_THR
+924    0x03E8    //TX_MICMUTE_DT_CUT_K2
+925    0x0001    //TX_MICMUTE_DT_CUT_THR2
+926    0x0064    //TX_MICMUTE_DT2_HOLD_N
+927    0x1000    //TX_MICMUTE_RATIODTH_THCUT
+928    0x1000    //TX_MICMUTE_B_POST_FLT_ECHOL
+929    0x7FFF    //TX_MICMUTE_B_POST_FLT_ECHOH
+930    0x0400    //TX_MICMUTE_C_POST_FLT_MASK
+931    0x7999    //TX_MICMUTE_RATIODTL_CUT_TH
+932    0x0258    //TX_MICMUTE_DT_CUT_K1
+933    0x0800    //TX_MICMUTE_N2_SN_EST
+934    0xFC00    //TX_MICMUTE_THR_SN_EST_0
+935    0x001C    //TX_MICMUTE_MIN_G_CTRL_0
+936    0x6000    //TX_MICMUTE_A_POST_FILT_S_0
+937    0x7000    //TX_MICMUTE_B_POST_FILT_0
+938    0x2710    //TX_MIC1RUB_AMP_THR
+939    0x0010    //TX_MIC1MUTE_RATIO_THR
+940    0x0450    //TX_MIC1MUTE_AMP_THR
+941    0x0008    //TX_MIC1MUTE_CVG_TIME
+942    0x0008    //TX_MIC1MUTE_RELEASE_TIME
+943    0x0000    //TX_AMS_RESRV_01
+944    0x0000    //TX_AMS_RESRV_02
+945    0x0000    //TX_AMS_RESRV_03
+946    0x0000    //TX_AMS_RESRV_04
+947    0x0000    //TX_AMS_RESRV_05
+948    0x0000    //TX_AMS_RESRV_06
+949    0x0000    //TX_AMS_RESRV_07
+950    0x0000    //TX_AMS_RESRV_08
+951    0x0000    //TX_AMS_RESRV_09
+952    0x0000    //TX_AMS_RESRV_10
+953    0x0000    //TX_AMS_RESRV_11
+954    0x0000    //TX_AMS_RESRV_12
+955    0x0000    //TX_AMS_RESRV_13
+956    0x0000    //TX_AMS_RESRV_14
+957    0x0000    //TX_AMS_RESRV_15
+958    0x0000    //TX_AMS_RESRV_16
+959    0x0000    //TX_AMS_RESRV_17
+960    0x0000    //TX_AMS_RESRV_18
+961    0x0000    //TX_AMS_RESRV_19
+#RX
+0    0x002C    //RX_RECVFUNC_MODE_0
+1    0x0000    //RX_RECVFUNC_MODE_1
+2    0x0003    //RX_SAMPLINGFREQ_SIG
+3    0x0003    //RX_SAMPLINGFREQ_PROC
+4    0x000A    //RX_FRAME_SZ
+5    0x0000    //RX_DELAY_OPT
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+10    0x0800    //RX_PGA
+11    0x7FFF    //RX_A_HP
+12    0x0000    //RX_B_PE
+13    0x1800    //RX_THR_PITCH_DET_0
+14    0x1000    //RX_THR_PITCH_DET_1
+15    0x0800    //RX_THR_PITCH_DET_2
+16    0x0008    //RX_PITCH_BFR_LEN
+17    0x0003    //RX_SBD_PITCH_DET
+18    0x0100    //RX_PP_RESRV_0
+19    0x0020    //RX_PP_RESRV_1
+20    0x0400    //RX_N_SN_EST
+21    0x000C    //RX_N2_SN_EST
+22    0x0003    //RX_NS_LVL_CTRL
+23    0x9000    //RX_THR_SN_EST
+24    0x7CCD    //RX_LAMBDA_PFILT
+25    0x000A    //RX_FENS_RESRV_0
+26    0x0190    //RX_FENS_RESRV_1
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+30    0x0002    //RX_EXTRA_NS_L
+31    0x0800    //RX_EXTRA_NS_A
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+35    0x199A    //RX_A_POST_FLT
+36    0x0000    //RX_LMT_THRD
+37    0x4000    //RX_LMT_ALPHA
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+111    0x0002    //RX_FILTINDX
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+125    0x7C00    //RX_LAMBDA_PKA_FP
+126    0x2000    //RX_TPKA_FP
+127    0x2000    //RX_MIN_G_FP
+128    0x0080    //RX_MAX_G_FP
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+131    0x0000    //RX_MAXLEVEL_CNG
+132    0x3000    //RX_BWE_UV_TH
+133    0x3000    //RX_BWE_UV_TH2
+134    0x1800    //RX_BWE_UV_TH3
+135    0x1000    //RX_BWE_V_TH
+136    0x04CD    //RX_BWE_GAIN1_V_TH1
+137    0x0F33    //RX_BWE_GAIN1_V_TH2
+138    0x7333    //RX_BWE_UV_EQ
+139    0x199A    //RX_BWE_V_EQ
+140    0x7333    //RX_BWE_TONE_TH
+141    0x0004    //RX_BWE_UV_HOLD_T
+142    0x6CCD    //RX_BWE_GAIN2_ALPHA
+143    0x799A    //RX_BWE_GAIN3_ALPHA
+144    0x001E    //RX_BWE_CUTOFF
+145    0x3000    //RX_BWE_GAINFILL
+146    0x3200    //RX_BWE_MAXTH_TONE
+147    0x2000    //RX_BWE_EQ_0
+148    0x2000    //RX_BWE_EQ_1
+149    0x2000    //RX_BWE_EQ_2
+150    0x2000    //RX_BWE_EQ_3
+151    0x2000    //RX_BWE_EQ_4
+152    0x2000    //RX_BWE_EQ_5
+153    0x2000    //RX_BWE_EQ_6
+154    0x0000    //RX_BWE_RESRV_0
+155    0x0000    //RX_BWE_RESRV_1
+156    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x000B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0013    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0020    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0036    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x005B    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0099    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+6    0x5000    //RX_TDDRC_ALPHA_UP_1
+7    0x5000    //RX_TDDRC_ALPHA_UP_2
+8    0x5000    //RX_TDDRC_ALPHA_UP_3
+9    0x2000    //RX_TDDRC_ALPHA_UP_4
+27    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+28    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+29    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+32    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+33    0x65AD    //RX_TDDRC_LIMITER_THRD
+34    0x0800    //RX_TDDRC_LIMITER_GAIN
+112    0x0000    //RX_TDDRC_THRD_0
+113    0x0000    //RX_TDDRC_THRD_1
+114    0x1A00    //RX_TDDRC_THRD_2
+115    0x1A00    //RX_TDDRC_THRD_3
+116    0x3000    //RX_TDDRC_SLANT_0
+117    0x7EB8    //RX_TDDRC_SLANT_1
+118    0x5000    //RX_TDDRC_ALPHA_UP_0
+119    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+120    0x0000    //RX_TDDRC_HMNC_FLAG
+121    0x199A    //RX_TDDRC_HMNC_GAIN
+122    0x0001    //RX_TDDRC_SMT_FLAG
+123    0x0CCD    //RX_TDDRC_SMT_W
+124    0x01C8    //RX_TDDRC_DRC_GAIN
+38    0x0020    //RX_FDEQ_SUBNUM
+39    0x4848    //RX_FDEQ_GAIN_0
+40    0x4848    //RX_FDEQ_GAIN_1
+41    0x4848    //RX_FDEQ_GAIN_2
+42    0x4848    //RX_FDEQ_GAIN_3
+43    0x4848    //RX_FDEQ_GAIN_4
+44    0x4848    //RX_FDEQ_GAIN_5
+45    0x4848    //RX_FDEQ_GAIN_6
+46    0x4848    //RX_FDEQ_GAIN_7
+47    0x4848    //RX_FDEQ_GAIN_8
+48    0x4848    //RX_FDEQ_GAIN_9
+49    0x4848    //RX_FDEQ_GAIN_10
+50    0x4848    //RX_FDEQ_GAIN_11
+51    0x4848    //RX_FDEQ_GAIN_12
+52    0x4848    //RX_FDEQ_GAIN_13
+53    0x4848    //RX_FDEQ_GAIN_14
+54    0x4848    //RX_FDEQ_GAIN_15
+55    0x4848    //RX_FDEQ_GAIN_16
+56    0x4848    //RX_FDEQ_GAIN_17
+57    0x4848    //RX_FDEQ_GAIN_18
+58    0x4848    //RX_FDEQ_GAIN_19
+59    0x4848    //RX_FDEQ_GAIN_20
+60    0x4848    //RX_FDEQ_GAIN_21
+61    0x4848    //RX_FDEQ_GAIN_22
+62    0x4848    //RX_FDEQ_GAIN_23
+63    0x0202    //RX_FDEQ_BIN_0
+64    0x0203    //RX_FDEQ_BIN_1
+65    0x0303    //RX_FDEQ_BIN_2
+66    0x0304    //RX_FDEQ_BIN_3
+67    0x0405    //RX_FDEQ_BIN_4
+68    0x0506    //RX_FDEQ_BIN_5
+69    0x0708    //RX_FDEQ_BIN_6
+70    0x090A    //RX_FDEQ_BIN_7
+71    0x0B0C    //RX_FDEQ_BIN_8
+72    0x0D0E    //RX_FDEQ_BIN_9
+73    0x1013    //RX_FDEQ_BIN_10
+74    0x1719    //RX_FDEQ_BIN_11
+75    0x1B1E    //RX_FDEQ_BIN_12
+76    0x1E1E    //RX_FDEQ_BIN_13
+77    0x1E28    //RX_FDEQ_BIN_14
+78    0x282C    //RX_FDEQ_BIN_15
+79    0x0000    //RX_FDEQ_BIN_16
+80    0x0000    //RX_FDEQ_BIN_17
+81    0x0000    //RX_FDEQ_BIN_18
+82    0x0000    //RX_FDEQ_BIN_19
+83    0x0000    //RX_FDEQ_BIN_20
+84    0x0000    //RX_FDEQ_BIN_21
+85    0x0000    //RX_FDEQ_BIN_22
+86    0x0000    //RX_FDEQ_BIN_23
+87    0x4000    //RX_FDEQ_RESRV_0
+88    0x0320    //RX_FDEQ_RESRV_1
+89    0x0018    //RX_FDDRC_BAND_MARGIN_0
+90    0x0030    //RX_FDDRC_BAND_MARGIN_1
+91    0x0050    //RX_FDDRC_BAND_MARGIN_2
+92    0x0080    //RX_FDDRC_BAND_MARGIN_3
+93    0x0007    //RX_FDDRC_BLOCK_EXP
+94    0x5000    //RX_FDDRC_THRD_2_0
+95    0x5000    //RX_FDDRC_THRD_2_1
+96    0x5000    //RX_FDDRC_THRD_2_2
+97    0x5000    //RX_FDDRC_THRD_2_3
+98    0x6400    //RX_FDDRC_THRD_3_0
+99    0x6400    //RX_FDDRC_THRD_3_1
+100    0x6400    //RX_FDDRC_THRD_3_2
+101    0x6400    //RX_FDDRC_THRD_3_3
+102    0x2000    //RX_FDDRC_SLANT_0_0
+103    0x2000    //RX_FDDRC_SLANT_0_1
+104    0x2000    //RX_FDDRC_SLANT_0_2
+105    0x2000    //RX_FDDRC_SLANT_0_3
+106    0x5333    //RX_FDDRC_SLANT_1_0
+107    0x5333    //RX_FDDRC_SLANT_1_1
+108    0x5333    //RX_FDDRC_SLANT_1_2
+109    0x5333    //RX_FDDRC_SLANT_1_3
+110    0x0000    //RX_FDDRC_RESRV_0
+129    0x0100    //RX_SPK_VOL
+130    0x0000    //RX_VOL_RESRV_0
+#RX 2
+157    0x002C    //RX_RECVFUNC_MODE_0
+158    0x0000    //RX_RECVFUNC_MODE_1
+159    0x0003    //RX_SAMPLINGFREQ_SIG
+160    0x0003    //RX_SAMPLINGFREQ_PROC
+161    0x000A    //RX_FRAME_SZ
+162    0x0000    //RX_DELAY_OPT
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+167    0x0800    //RX_PGA
+168    0x7FFF    //RX_A_HP
+169    0x0000    //RX_B_PE
+170    0x1800    //RX_THR_PITCH_DET_0
+171    0x1000    //RX_THR_PITCH_DET_1
+172    0x0800    //RX_THR_PITCH_DET_2
+173    0x0008    //RX_PITCH_BFR_LEN
+174    0x0003    //RX_SBD_PITCH_DET
+175    0x0100    //RX_PP_RESRV_0
+176    0x0020    //RX_PP_RESRV_1
+177    0x0400    //RX_N_SN_EST
+178    0x000C    //RX_N2_SN_EST
+179    0x0003    //RX_NS_LVL_CTRL
+180    0x9000    //RX_THR_SN_EST
+181    0x7CCD    //RX_LAMBDA_PFILT
+182    0x000A    //RX_FENS_RESRV_0
+183    0x0190    //RX_FENS_RESRV_1
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+187    0x0002    //RX_EXTRA_NS_L
+188    0x0800    //RX_EXTRA_NS_A
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+192    0x199A    //RX_A_POST_FLT
+193    0x0000    //RX_LMT_THRD
+194    0x4000    //RX_LMT_ALPHA
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+268    0x0002    //RX_FILTINDX
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+282    0x7C00    //RX_LAMBDA_PKA_FP
+283    0x2000    //RX_TPKA_FP
+284    0x2000    //RX_MIN_G_FP
+285    0x0080    //RX_MAX_G_FP
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+288    0x0000    //RX_MAXLEVEL_CNG
+289    0x3000    //RX_BWE_UV_TH
+290    0x3000    //RX_BWE_UV_TH2
+291    0x1800    //RX_BWE_UV_TH3
+292    0x1000    //RX_BWE_V_TH
+293    0x04CD    //RX_BWE_GAIN1_V_TH1
+294    0x0F33    //RX_BWE_GAIN1_V_TH2
+295    0x7333    //RX_BWE_UV_EQ
+296    0x199A    //RX_BWE_V_EQ
+297    0x7333    //RX_BWE_TONE_TH
+298    0x0004    //RX_BWE_UV_HOLD_T
+299    0x6CCD    //RX_BWE_GAIN2_ALPHA
+300    0x799A    //RX_BWE_GAIN3_ALPHA
+301    0x001E    //RX_BWE_CUTOFF
+302    0x3000    //RX_BWE_GAINFILL
+303    0x3200    //RX_BWE_MAXTH_TONE
+304    0x2000    //RX_BWE_EQ_0
+305    0x2000    //RX_BWE_EQ_1
+306    0x2000    //RX_BWE_EQ_2
+307    0x2000    //RX_BWE_EQ_3
+308    0x2000    //RX_BWE_EQ_4
+309    0x2000    //RX_BWE_EQ_5
+310    0x2000    //RX_BWE_EQ_6
+311    0x0000    //RX_BWE_RESRV_0
+312    0x0000    //RX_BWE_RESRV_1
+313    0x0000    //RX_BWE_RESRV_2
+#VOL    0
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x000B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    1
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0013    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    2
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0020    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    3
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0036    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    4
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x005B    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    5
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0099    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
+#VOL    6
+163    0x5000    //RX_TDDRC_ALPHA_UP_1
+164    0x5000    //RX_TDDRC_ALPHA_UP_2
+165    0x5000    //RX_TDDRC_ALPHA_UP_3
+166    0x2000    //RX_TDDRC_ALPHA_UP_4
+184    0x7EB8    //RX_TDDRC_ALPHA_DWN_1
+185    0x7EB8    //RX_TDDRC_ALPHA_DWN_2
+186    0x7EB8    //RX_TDDRC_ALPHA_DWN_3
+189    0x7EB8    //RX_TDDRC_ALPHA_DWN_4
+190    0x65AD    //RX_TDDRC_LIMITER_THRD
+191    0x0800    //RX_TDDRC_LIMITER_GAIN
+269    0x0000    //RX_TDDRC_THRD_0
+270    0x0000    //RX_TDDRC_THRD_1
+271    0x1A00    //RX_TDDRC_THRD_2
+272    0x1A00    //RX_TDDRC_THRD_3
+273    0x3000    //RX_TDDRC_SLANT_0
+274    0x7EB8    //RX_TDDRC_SLANT_1
+275    0x5000    //RX_TDDRC_ALPHA_UP_0
+276    0x7EB8    //RX_TDDRC_ALPHA_DWN_0
+277    0x0000    //RX_TDDRC_HMNC_FLAG
+278    0x199A    //RX_TDDRC_HMNC_GAIN
+279    0x0001    //RX_TDDRC_SMT_FLAG
+280    0x0CCD    //RX_TDDRC_SMT_W
+281    0x01C8    //RX_TDDRC_DRC_GAIN
+195    0x0020    //RX_FDEQ_SUBNUM
+196    0x4848    //RX_FDEQ_GAIN_0
+197    0x4848    //RX_FDEQ_GAIN_1
+198    0x4848    //RX_FDEQ_GAIN_2
+199    0x4848    //RX_FDEQ_GAIN_3
+200    0x4848    //RX_FDEQ_GAIN_4
+201    0x4848    //RX_FDEQ_GAIN_5
+202    0x4848    //RX_FDEQ_GAIN_6
+203    0x4848    //RX_FDEQ_GAIN_7
+204    0x4848    //RX_FDEQ_GAIN_8
+205    0x4848    //RX_FDEQ_GAIN_9
+206    0x4848    //RX_FDEQ_GAIN_10
+207    0x4848    //RX_FDEQ_GAIN_11
+208    0x4848    //RX_FDEQ_GAIN_12
+209    0x4848    //RX_FDEQ_GAIN_13
+210    0x4848    //RX_FDEQ_GAIN_14
+211    0x4848    //RX_FDEQ_GAIN_15
+212    0x4848    //RX_FDEQ_GAIN_16
+213    0x4848    //RX_FDEQ_GAIN_17
+214    0x4848    //RX_FDEQ_GAIN_18
+215    0x4848    //RX_FDEQ_GAIN_19
+216    0x4848    //RX_FDEQ_GAIN_20
+217    0x4848    //RX_FDEQ_GAIN_21
+218    0x4848    //RX_FDEQ_GAIN_22
+219    0x4848    //RX_FDEQ_GAIN_23
+220    0x0202    //RX_FDEQ_BIN_0
+221    0x0203    //RX_FDEQ_BIN_1
+222    0x0303    //RX_FDEQ_BIN_2
+223    0x0304    //RX_FDEQ_BIN_3
+224    0x0405    //RX_FDEQ_BIN_4
+225    0x0506    //RX_FDEQ_BIN_5
+226    0x0708    //RX_FDEQ_BIN_6
+227    0x090A    //RX_FDEQ_BIN_7
+228    0x0B0C    //RX_FDEQ_BIN_8
+229    0x0D0E    //RX_FDEQ_BIN_9
+230    0x1013    //RX_FDEQ_BIN_10
+231    0x1719    //RX_FDEQ_BIN_11
+232    0x1B1E    //RX_FDEQ_BIN_12
+233    0x1E1E    //RX_FDEQ_BIN_13
+234    0x1E28    //RX_FDEQ_BIN_14
+235    0x282C    //RX_FDEQ_BIN_15
+236    0x0000    //RX_FDEQ_BIN_16
+237    0x0000    //RX_FDEQ_BIN_17
+238    0x0000    //RX_FDEQ_BIN_18
+239    0x0000    //RX_FDEQ_BIN_19
+240    0x0000    //RX_FDEQ_BIN_20
+241    0x0000    //RX_FDEQ_BIN_21
+242    0x0000    //RX_FDEQ_BIN_22
+243    0x0000    //RX_FDEQ_BIN_23
+244    0x4000    //RX_FDEQ_RESRV_0
+245    0x0320    //RX_FDEQ_RESRV_1
+246    0x0018    //RX_FDDRC_BAND_MARGIN_0
+247    0x0030    //RX_FDDRC_BAND_MARGIN_1
+248    0x0050    //RX_FDDRC_BAND_MARGIN_2
+249    0x0080    //RX_FDDRC_BAND_MARGIN_3
+250    0x0007    //RX_FDDRC_BLOCK_EXP
+251    0x5000    //RX_FDDRC_THRD_2_0
+252    0x5000    //RX_FDDRC_THRD_2_1
+253    0x5000    //RX_FDDRC_THRD_2_2
+254    0x5000    //RX_FDDRC_THRD_2_3
+255    0x6400    //RX_FDDRC_THRD_3_0
+256    0x6400    //RX_FDDRC_THRD_3_1
+257    0x6400    //RX_FDDRC_THRD_3_2
+258    0x6400    //RX_FDDRC_THRD_3_3
+259    0x2000    //RX_FDDRC_SLANT_0_0
+260    0x2000    //RX_FDDRC_SLANT_0_1
+261    0x2000    //RX_FDDRC_SLANT_0_2
+262    0x2000    //RX_FDDRC_SLANT_0_3
+263    0x5333    //RX_FDDRC_SLANT_1_0
+264    0x5333    //RX_FDDRC_SLANT_1_1
+265    0x5333    //RX_FDDRC_SLANT_1_2
+266    0x5333    //RX_FDDRC_SLANT_1_3
+267    0x0000    //RX_FDDRC_RESRV_0
+286    0x0100    //RX_SPK_VOL
+287    0x0000    //RX_VOL_RESRV_0
 
diff --git a/audio/felix/tuning/waves/waves_config.ini b/audio/felix/tuning/waves/waves_config.ini
index cf922f6..868bb11 100644
--- a/audio/felix/tuning/waves/waves_config.ini
+++ b/audio/felix/tuning/waves/waves_config.ini
@@ -5,7 +5,6 @@
 # Putting any value other than 1 would be equivalent to not supported.
 ########################################################################################################
 [HAL_SUPPORTED_FEATURES]
-CUSTOM_ACTION_256=0
 CUSTOM_ACTION_257=1
 
 ########################################################################################################
@@ -27,12 +26,19 @@
 # This should be configured by Waves only unless platform vendor is familiar with MPS structure.
 ########################################################################################################
 [HAL_SUPPORTED_PRESETS]
-SPEAKER_MUSIC_UNFOLDED = OM:1,SM:2,OST:OST_SPEAKER
+SPEAKER_MUSIC_FOLDED_THROTTLE= OM:1,SM:3,OST:OST_SPEAKER
+SPEAKER_MUSIC_UNFOLDED_THROTTLE= OM:9,SM:3,OST:OST_SPEAKER
+SPEAKER_MUSIC_CLAMSHELL_THROTTLE= OM:60,SM:3,OST:OST_SPEAKER
+SPEAKER_SAFE_MUSIC_THROTTLE = OM:10,SM:3,OST:OST_SPEAKER
 SPEAKER_MUSIC_FOLDED = OM:1,SM:2,OST:OST_SPEAKER
-SPEAKER_MUSIC = OM:1,SM:2,OST:OST_SPEAKER
+SPEAKER_MUSIC_UNFOLDED = OM:9,SM:2,OST:OST_SPEAKER
+SPEAKER_MUSIC_CLAMSHELL = OM:60,SM:2,OST:OST_SPEAKER
 SPEAKER_SAFE_MUSIC = OM:10,SM:2,OST:OST_SPEAKER
-SPEAKER_SAFE_CALL = OM:10,SM:2,OST:OST_SPEAKER
-HEADSET_MUSIC = OM:2,SM:2
+SPEAKER_MUSIC_RESERVED_UNFOLDED = OM:11,SM:2,OST:OST_SPEAKER
+SPEAKER_MUSIC_RESERVED_CLAMSHELL = OM:12,SM:2,OST:OST_SPEAKER
+SPEAKER_MUSIC_RESERVED_UNFOLDED_THROTTLE = OM:11,SM:3,OST:OST_SPEAKER
+SPEAKER_MUSIC_RESERVED_CLAMSHELL_THROTTLE = OM:12,SM:3,OST:OST_SPEAKER
+
 
 ########################################################################################################
 # This defines available CONTROL configurations. Only define the CONTROL if you need it.
@@ -40,9 +46,7 @@
 # This can be configured by Waves or platform vendor.
 ########################################################################################################
 [HAL_SUPPORTED_CONTROLS]
-SPEAKER_INSTANCE = INSTANCE:1,DEV:0,SR:SR_COMMON,PRESET:SPEAKER_MUSIC|SPEAKER_SAFE_MUSIC|SPEAKER_SAFE_CALL
-A2DP_INSTANCE = INSTANCE:2,DEV:0,SR:SR_COMMON,PRESET:HEADSET_MUSIC
-USB_HEADPHONE_INSTANCE = INSTANCE:4,DEV:0,SR:SR_COMMON,PRESET:HEADSET_MUSIC
+SPEAKER_INSTANCE = INSTANCE:1,DEV:0,SR:SR_COMMON,PRESET:SPEAKER_MUSIC_FOLDED_THROTTLE|SPEAKER_MUSIC_UNFOLDED_THROTTLE|SPEAKER_MUSIC_CLAMSHELL_THROTTLE|SPEAKER_MUSIC_RESERVED_CLAMSHELL_THROTTLE|SPEAKER_MUSIC_RESERVED_UNFOLDED_THROTTLE|SPEAKER_SAFE_MUSIC_THROTTLE|SPEAKER_MUSIC_FOLDED|SPEAKER_MUSIC_UNFOLDED|SPEAKER_MUSIC_CLAMSHELL|SPEAKER_MUSIC_RESERVED_UNFOLDED|SPEAKER_MUSIC_RESERVED_CLAMSHELL|SPEAKER_SAFE_MUSIC
 
 [COEFS_CONVERTER_SETTING]
 AlgFxPath=/vendor/lib/libAlgFx_HiFi3z.so
@@ -55,15 +59,27 @@
 #AudioFormatSampleSize=4
 #AudioFormatIncrement=8
 
-# CUSTOM_ACTION_LR_MIXED (dev/mode)
-[CUSTOM_ACTION_256]
-CASE_1=PRIORITY:0,NUMBERS:2:0|1,PRESET:SPEAKER_MUSIC
-CASE_2=PRIORITY:1,NUMBERS:1|2|4194304:2|3|4,PRESET:SPEAKER_SAFE_CALL
-CASE_3=PRIORITY:2,NUMBERS:1|4194304:0|1,PRESET:SPEAKER_SAFE_MUSIC
-
-# CUSTOM_ACTION_LR_MIXED_FOLDED (dev/mode/folded)
 [CUSTOM_ACTION_257]
-CASE_1=PRIORITY:0,NUMBERS:2:0|1:0,PRESET:SPEAKER_MUSIC_UNFOLDED
-CASE_2=PRIORITY:1,NUMBERS:1|2|4194304:2|3|4:0|1,PRESET:SPEAKER_SAFE_CALL
-CASE_3=PRIORITY:2,NUMBERS:1|4194304:0|1:0|1,PRESET:SPEAKER_SAFE_MUSIC
-CASE_4=PRIORITY:3,NUMBERS:2:0|1:1,PRESET:SPEAKER_MUSIC_FOLDED
+CASE_1=PRIORITY:0,NUMBERS:2:0|1:1|2:0|3:0,PRESET:SPEAKER_MUSIC_FOLDED
+CASE_2=PRIORITY:1,NUMBERS:2:0|1:1|2:1:0,PRESET:SPEAKER_MUSIC_CLAMSHELL
+CASE_3=PRIORITY:2,NUMBERS:2:0|1:1|2:2:0,PRESET:SPEAKER_MUSIC_UNFOLDED
+CASE_4=PRIORITY:3,NUMBERS:1|2|4194304:2|3|4:1|2:0|1|2|3:0|1,PRESET:SPEAKER_SAFE_MUSIC
+CASE_5=PRIORITY:4,NUMBERS:1|4194304:0|1:1|2:0|1|2|3:0|1,PRESET:SPEAKER_SAFE_MUSIC
+CASE_6=PRIORITY:5,NUMBERS:2:0|1:0:0|3:0|1,PRESET:SPEAKER_MUSIC_FOLDED_THROTTLE
+CASE_7=PRIORITY:6,NUMBERS:2:0|1:0:1:0,PRESET:SPEAKER_MUSIC_CLAMSHELL_THROTTLE
+CASE_8=PRIORITY:7,NUMBERS:2:0|1:0:2:0,PRESET:SPEAKER_MUSIC_UNFOLDED_THROTTLE
+CASE_9=PRIORITY:8,NUMBERS:1|2|4194304:2|3|4:0:0|1|2|3:0|1,PRESET:SPEAKER_SAFE_MUSIC_THROTTLE
+CASE_10=PRIORITY:9,NUMBERS:1|4194304:0|1:0:0|1|2|3:0|1,PRESET:SPEAKER_SAFE_MUSIC_THROTTLE
+CASE_11=PRIORITY:10,NUMBERS:2:0|1:1|2:0|2:1,PRESET:SPEAKER_MUSIC_RESERVED_UNFOLDED
+CASE_12=PRIORITY:11,NUMBERS:2:0|1:1|2:1:1,PRESET:SPEAKER_MUSIC_RESERVED_CLAMSHELL
+CASE_13=PRIORITY:12,NUMBERS:2:0|1:0:0|2:1,PRESET:SPEAKER_MUSIC_RESERVED_UNFOLDED_THROTTLE
+CASE_14=PRIORITY:13,NUMBERS:2:0|1:0:1:1,PRESET:SPEAKER_MUSIC_RESERVED_CLAMSHELL_THROTTLE
+
+
+# Action 257 parameters:  audio_devices_t, audio_mode_t, throttle_control_state_t, folded_type_t, sound_usage_t
+# - audio_devices_t : current active device
+# - audio_mode_t : 0 - normal, 1 - incoming, 2 - voice call, 3 - voip
+# - throttle_control_state_t: 0 - Enabled, 1 - Disabled, 2 - Bypassed
+# - folded_type_t: 0 - Close, 1 -Clamshell, 2 - Open, 3 - unknown
+# - sound_usage_t: 0 - Music, 1 - Movie
+
diff --git a/audio/felix/tuning/waves/waves_preset.mps b/audio/felix/tuning/waves/waves_preset.mps
index 0237e66..421611f 100644
--- a/audio/felix/tuning/waves/waves_preset.mps
+++ b/audio/felix/tuning/waves/waves_preset.mps
Binary files differ
diff --git a/bluetooth/bluetooth_power_limits_felix_EU.csv b/bluetooth/bluetooth_power_limits_felix_EU.csv
new file mode 100644
index 0000000..dde97b3
--- /dev/null
+++ b/bluetooth/bluetooth_power_limits_felix_EU.csv
@@ -0,0 +1,67 @@
+Hall,Head,BTHotspot,WIFI5Ghz,HotspotVoice,Cell,IMU,BDR_Single_Chain_0,EDR_Single_Chain_0,BLE_Single_Chain_0,BDR_Single_Chain_1,EDR_Single_Chain_1,BLE_Single_Chain_1,BDR_Dual_Chain_0,EDR_Dual_Chain_0,BLE_Dual_Chain_0,BDR_Dual_Chain_1,EDR_Dual_Chain_1,BLE_Dual_Chain_1
+off,off,off,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,any,any,any,any,off,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,any,any,any,any,off,78,76,36,78,76,36,62,62,24,62,62,24
diff --git a/bluetooth/bluetooth_power_limits_felix_JP.csv b/bluetooth/bluetooth_power_limits_felix_JP.csv
new file mode 100644
index 0000000..dde97b3
--- /dev/null
+++ b/bluetooth/bluetooth_power_limits_felix_JP.csv
@@ -0,0 +1,67 @@
+Hall,Head,BTHotspot,WIFI5Ghz,HotspotVoice,Cell,IMU,BDR_Single_Chain_0,EDR_Single_Chain_0,BLE_Single_Chain_0,BDR_Single_Chain_1,EDR_Single_Chain_1,BLE_Single_Chain_1,BDR_Dual_Chain_0,EDR_Dual_Chain_0,BLE_Dual_Chain_0,BDR_Dual_Chain_1,EDR_Dual_Chain_1,BLE_Dual_Chain_1
+off,off,off,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,off,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,on,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,off,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,on,on,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+off,off,any,any,any,any,off,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,off,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,off,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,off,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,off,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,on,off,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,on,on,on,on,on,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,off,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,off,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,off,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,off,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,on,off,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,on,on,on,on,on,any,78,76,36,78,76,36,62,62,24,62,62,24
+on,off,any,any,any,any,off,78,76,36,78,76,36,62,62,24,62,62,24
diff --git a/bluetooth/bluetooth_power_limits_felix_US.csv b/bluetooth/bluetooth_power_limits_felix_US.csv
new file mode 100644
index 0000000..52882b8
--- /dev/null
+++ b/bluetooth/bluetooth_power_limits_felix_US.csv
@@ -0,0 +1,67 @@
+Hall,Head,BTHotspot,WIFI5Ghz,HotspotVoice,Cell,IMU,BDR_Single_Chain_0,EDR_Single_Chain_0,BLE_Single_Chain_0,BDR_Single_Chain_1,EDR_Single_Chain_1,BLE_Single_Chain_1,BDR_Dual_Chain_0,EDR_Dual_Chain_0,BLE_Dual_Chain_0,BDR_Dual_Chain_1,EDR_Dual_Chain_1,BLE_Dual_Chain_1
+off,off,off,off,off,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+off,off,off,off,off,on,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,off,off,on,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,off,off,on,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,off,off,on,off,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,off,on,off,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,off,off,on,on,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,off,on,on,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,off,on,off,off,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,on,off,off,on,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,on,off,on,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,on,off,on,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,off,on,on,off,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,on,on,off,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,off,on,on,on,off,on,78,76,78,72,72,72,62,62,62,62,62,62
+off,off,on,on,on,on,on,66,66,66,60,60,60,62,62,62,62,62,62
+off,on,off,off,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,off,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,off,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,off,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,on,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,on,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,on,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,off,on,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,off,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,off,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,off,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,off,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,on,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,on,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,on,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,on,on,on,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+off,off,any,any,any,any,off,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,off,off,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,off,off,on,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,off,on,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,off,on,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,off,off,on,off,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,on,off,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,off,off,on,on,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,off,on,on,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,off,on,off,off,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,on,off,off,on,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,on,off,on,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,on,off,on,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,off,on,on,off,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,on,on,off,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,off,on,on,on,off,on,78,76,78,78,76,78,62,62,62,62,62,62
+on,off,on,on,on,on,on,68,68,68,70,70,70,62,62,62,62,62,62
+on,on,off,off,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,off,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,off,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,off,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,on,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,on,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,on,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,off,on,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,off,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,off,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,off,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,off,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,on,off,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,on,off,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,on,on,off,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,on,on,on,on,on,any,44,44,44,54,54,54,56,56,56,56,56,56
+on,off,any,any,any,any,off,78,76,78,78,76,78,62,62,62,62,62,62
diff --git a/bluetooth/bt_vendor_overlay.conf b/bluetooth/bt_vendor_overlay.conf
index 9c44fe0..5685ae7 100644
--- a/bluetooth/bt_vendor_overlay.conf
+++ b/bluetooth/bt_vendor_overlay.conf
@@ -2,3 +2,5 @@
 
 # Uart port name
 UartPort = /dev/ttySAC18
+
+BtOpusEnabled = true
diff --git a/bluetooth/le_audio_codec_capabilities.xml b/bluetooth/le_audio_codec_capabilities.xml
new file mode 100644
index 0000000..89d0de6
--- /dev/null
+++ b/bluetooth/le_audio_codec_capabilities.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!---
+  This is an example to configure LE Audio hardware offload supported capability settings
+  codecConfigurationList:
+    Supported codec capability along with its parameter setting
+
+  strategyConfigurationList:
+     ASE Configuration strategies
+
+  configurationList:
+    For each configuration, there are two attributes
+      - codecConfiguration
+      - strategyConfiguration
+
+  scenarioList:
+    There would be only one `scenarios` group
+    For each scenario, the are two attributes
+      - encode
+      - decode
+    If a scenario is unidirectional, mark another direction as `invalid`
+    The configuration should be chosen from `configurationList`
+-->
+<leAudioOffloadSetting>
+  <scenarioList>
+    <!-- encode only -->
+    <scenario encode="OneChanMono_16_1" decode="invalid"/>
+    <scenario encode="TwoChanStereo_16_1" decode="invalid"/>
+    <scenario encode="OneChanStereo_16_1" decode="invalid"/>
+    <scenario encode="OneChanMono_16_2" decode="invalid"/>
+    <scenario encode="TwoChanStereo_16_2" decode="invalid"/>
+    <scenario encode="OneChanStereo_16_2" decode="invalid"/>
+    <scenario encode="OneChanMono_24_2" decode="invalid"/>
+    <scenario encode="TwoChanStereo_24_2" decode="invalid"/>
+    <scenario encode="OneChanStereo_24_2" decode="invalid"/>
+    <scenario encode="OneChanMono_48_4" decode="invalid"/>
+    <scenario encode="TwoChanStereo_48_4" decode="invalid"/>
+    <scenario encode="OneChanStereo_48_4" decode="invalid"/>
+    <!-- encode and decode -->
+    <scenario encode="OneChanStereo_16_1" decode="OneChanStereo_16_1"/>
+    <scenario encode="OneChanStereo_16_1" decode="OneChanMono_16_1"/>
+    <scenario encode="TwoChanStereo_16_1" decode="OneChanMono_16_1"/>
+    <scenario encode="OneChanMono_16_1" decode="OneChanMono_16_1"/>
+    <scenario encode="OneChanStereo_16_2" decode="OneChanStereo_16_2"/>
+    <scenario encode="OneChanStereo_16_2" decode="OneChanMono_16_2"/>
+    <scenario encode="TwoChanStereo_16_2" decode="OneChanMono_16_2"/>
+    <scenario encode="OneChanMono_16_2" decode="OneChanMono_16_2"/>
+    <scenario encode="TwoChanStereo_32_2" decode="OneChanMono_32_2"/>
+    <scenario encode="OneChanMono_32_2" decode="OneChanMono_32_2"/>
+  </scenarioList>
+  <configurationList>
+    <configuration name="OneChanMono_16_1" codecConfiguration="LC3_16k_1" strategyConfiguration="MONO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="TwoChanStereo_16_1" codecConfiguration="LC3_16k_1" strategyConfiguration="STEREO_TWO_CISES_PER_DEVICE"/>
+    <configuration name="OneChanStereo_16_1" codecConfiguration="LC3_16k_1" strategyConfiguration="STEREO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="OneChanMono_16_2" codecConfiguration="LC3_16k_2" strategyConfiguration="MONO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="TwoChanStereo_16_2" codecConfiguration="LC3_16k_2" strategyConfiguration="STEREO_TWO_CISES_PER_DEVICE"/>
+    <configuration name="OneChanStereo_16_2" codecConfiguration="LC3_16k_2" strategyConfiguration="STEREO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="OneChanMono_24_2" codecConfiguration="LC3_24k_2" strategyConfiguration="MONO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="TwoChanStereo_24_2" codecConfiguration="LC3_24k_2" strategyConfiguration="STEREO_TWO_CISES_PER_DEVICE"/>
+    <configuration name="OneChanStereo_24_2" codecConfiguration="LC3_24k_2" strategyConfiguration="STEREO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="OneChanMono_48_4" codecConfiguration="LC3_48k_4" strategyConfiguration="MONO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="TwoChanStereo_32_2" codecConfiguration="LC3_32k_2" strategyConfiguration="STEREO_TWO_CISES_PER_DEVICE"/>
+    <configuration name="OneChanMono_32_2" codecConfiguration="LC3_32k_2" strategyConfiguration="MONO_ONE_CIS_PER_DEVICE"/>
+    <configuration name="TwoChanStereo_48_4" codecConfiguration="LC3_48k_4" strategyConfiguration="STEREO_TWO_CISES_PER_DEVICE"/>
+    <configuration name="OneChanStereo_48_4" codecConfiguration="LC3_48k_4" strategyConfiguration="STEREO_ONE_CIS_PER_DEVICE"/>
+  </configurationList>
+  <codecConfigurationList>
+    <codecConfiguration name="LC3_16k_1" codec="LC3" samplingFrequency="16000" frameDurationUs="7500" octetsPerCodecFrame="30"/>
+    <codecConfiguration name="LC3_16k_2" codec="LC3" samplingFrequency="16000" frameDurationUs="10000" octetsPerCodecFrame="40"/>
+    <codecConfiguration name="LC3_24k_2" codec="LC3" samplingFrequency="24000" frameDurationUs="10000" octetsPerCodecFrame="60"/>
+    <codecConfiguration name="LC3_32k_2" codec="LC3" samplingFrequency="32000" frameDurationUs="10000" octetsPerCodecFrame="80"/>
+    <codecConfiguration name="LC3_48k_4" codec="LC3" samplingFrequency="48000" frameDurationUs="10000" octetsPerCodecFrame="120"/>
+  </codecConfigurationList>
+  <strategyConfigurationList>
+    <strategyConfiguration name="STEREO_ONE_CIS_PER_DEVICE" audioLocation="STEREO" connectedDevice="2" channelCount="1"/>
+    <strategyConfiguration name="STEREO_TWO_CISES_PER_DEVICE" audioLocation="STEREO" connectedDevice="1" channelCount="2"/>
+    <strategyConfiguration name="MONO_ONE_CIS_PER_DEVICE" audioLocation="MONO" connectedDevice="1" channelCount="1"/>
+  </strategyConfigurationList>
+</leAudioOffloadSetting>
diff --git a/bluetooth/manifest_bluetooth.xml b/bluetooth/manifest_bluetooth.xml
deleted file mode 100644
index 2d055f4..0000000
--- a/bluetooth/manifest_bluetooth.xml
+++ /dev/null
@@ -1,38 +0,0 @@
-<manifest version="1.0" type="device">
-    <hal format="hidl">
-        <name>android.hardware.bluetooth</name>
-        <transport>hwbinder</transport>
-        <version>1.1</version>
-        <interface>
-            <name>IBluetoothHci</name>
-            <instance>default</instance>
-        </interface>
-    </hal>
-    <hal format="hidl">
-        <name>hardware.google.bluetooth.bt_channel_avoidance</name>
-        <transport>hwbinder</transport>
-        <version>1.0</version>
-        <interface>
-            <name>IBTChannelAvoidance</name>
-            <instance>default</instance>
-        </interface>
-    </hal>
-    <hal format="hidl">
-        <name>hardware.google.bluetooth.sar</name>
-        <transport>hwbinder</transport>
-        <version>1.1</version>
-        <interface>
-            <name>IBluetoothSar</name>
-            <instance>default</instance>
-        </interface>
-    </hal>
-    <hal format="hidl">
-        <name>hardware.google.bluetooth.ccc</name>
-        <transport>hwbinder</transport>
-        <version>1.1</version>
-        <interface>
-            <name>IBluetoothCcc</name>
-            <instance>default</instance>
-        </interface>
-    </hal>
-</manifest>
diff --git a/board-info.txt b/board-info.txt
index 585d210..8bf5c66 100644
--- a/board-info.txt
+++ b/board-info.txt
@@ -1 +1,2 @@
 require board=felix
+require partition-exists=vendor_kernel_boot
diff --git a/conf/init.felix.rc b/conf/init.felix.rc
index 1328b9f..891865b 100644
--- a/conf/init.felix.rc
+++ b/conf/init.felix.rc
@@ -1,18 +1,51 @@
 # Felix specific init.rc
 import /vendor/etc/init/hw/init.gs201.rc
 
-on fs
+on init && property:ro.vendor.factory=1
+    import /vendor/etc/init/hw/init.factory.rc
+
+# SFPS Fingerprint
+on post-fs-data
     chown system system /sys/devices/platform/odm/odm:fp_fpc1020/clk_enable
     chown system system /sys/devices/platform/odm/odm:fp_fpc1020/hw_reset
     chown system system /sys/devices/platform/odm/odm:fp_fpc1020/irq
     chown system system /sys/devices/platform/odm/odm:fp_fpc1020/wakeup_enable
-    exec_background - system shell -- /vendor/bin/trusty_apploader /vendor/firmware/1540.app
 
 # Permissions for hwcomposer
+on fs
     chown system system /sys/class/backlight/panel1-backlight/als_table
     chown system system /sys/class/backlight/panel1-backlight/brightness
     chown system system /sys/class/backlight/panel1-backlight/dimming_on
     chown system system /sys/class/backlight/panel1-backlight/hbm_mode
+    chown system system /sys/class/backlight/panel1-backlight/local_hbm_mode
+    chown system system /sys/devices/platform/exynos-drm/secondary-panel/gamma
+    chown system system /sys/devices/platform/exynos-drm/secondary-panel/min_vrefresh
+    chown system system /sys/devices/platform/exynos-drm/secondary-panel/idle_delay_ms
+    chown system system /sys/devices/platform/exynos-drm/secondary-panel/panel_idle
+    chown system system /sys/devices/platform/exynos-drm/secondary-panel/panel_need_handle_idle_exit
+    chown system system /sys/class/dqe1/atc/ambient_light
+    chown system system /sys/class/dqe1/atc/st
+    chown system system /sys/class/dqe1/atc/en
+    chown system system /sys/class/dqe1/atc/lt
+    chown system system /sys/class/dqe1/atc/ns
+    chown system system /sys/class/dqe1/atc/dither
+    chown system system /sys/class/dqe1/atc/pl_w1
+    chown system system /sys/class/dqe1/atc/pl_w2
+    chown system system /sys/class/dqe1/atc/ctmode
+    chown system system /sys/class/dqe1/atc/pp_en
+    chown system system /sys/class/dqe1/atc/upgrade_on
+    chown system system /sys/class/dqe1/atc/tdr_max
+    chown system system /sys/class/dqe1/atc/tdr_min
+    chown system system /sys/class/dqe1/atc/back_light
+    chown system system /sys/class/dqe1/atc/dstep
+    chown system system /sys/class/dqe1/atc/scale_mode
+    chown system system /sys/class/dqe1/atc/threshold_1
+    chown system system /sys/class/dqe1/atc/threshold_2
+    chown system system /sys/class/dqe1/atc/threshold_3
+    chown system system /sys/class/dqe1/atc/gain_limit
+    chown system system /sys/class/dqe1/atc/lt_calc_ab_shift
+    chown system system /sys/devices/platform/1c241000.drmdecon/early_wakeup
+    chmod 0660 /sys/devices/platform/1c241000.drmdecon/early_wakeup
 
 # Touch
 on property:vendor.device.modules.ready=1
@@ -23,14 +56,16 @@
     # Start the twoshay touch service
     start twoshay
 
-# Toggle glove_mode according to touch_sensitivity_mode
+# Toggle glove_mode according to touch_sensitivity_mode, only apply to outer panel
 on property:persist.vendor.touch_sensitivity_mode=0 && property:sys.boot_completed=1
-    write /sys/class/spi_master/spi11/spi11.0/glove_mode 00
-    write /sys/class/spi_master/spi6/spi6.0/glove_mode 00
+    write /sys/devices/virtual/goog_touch_interface/gti.1/force_active 1
+    write /sys/devices/virtual/goog_touch_interface/gti.1/screen_protector_mode_enabled 0
+    write /sys/devices/virtual/goog_touch_interface/gti.1/force_active 0
 
 on property:persist.vendor.touch_sensitivity_mode=1 && property:sys.boot_completed=1
-    write /sys/class/spi_master/spi11/spi11.0/glove_mode 01
-    write /sys/class/spi_master/spi6/spi6.0/glove_mode 01
+    write /sys/devices/virtual/goog_touch_interface/gti.1/force_active 1
+    write /sys/devices/virtual/goog_touch_interface/gti.1/screen_protector_mode_enabled 1
+    write /sys/devices/virtual/goog_touch_interface/gti.1/force_active 0
 
 # Load FPC's internal lib
 on init
@@ -38,6 +73,7 @@
     # NFC streset tool name
     setprop persist.vendor.nfc.streset libstreset21
     setprop persist.vendor.se.streset libstreset21
+    setprop dalvik.vm.dexopt.thermal-cutoff 1
 
 # When ro.build.flavor=factory_felix-userdebug, add vendor/bin/factory to default path
 on init && property:ro.build.flavor=factory_felix-userdebug
@@ -48,7 +84,7 @@
     wait_for_prop vendor.common.modules.ready 1
     start insmod_sh_felix
 
-service insmod_sh_felix /vendor/bin/init.insmod.sh /vendor/etc/init.insmod.felix.cfg
+service insmod_sh_felix /vendor/bin/insmod.sh /vendor/etc/init.insmod.felix.cfg
     class main
     user root
     group root system
@@ -66,6 +102,10 @@
     chmod 0600 /sys/devices/virtual/sec/tsp/cmd
     chown system system /sys/devices/virtual/sec/tsp/cmd
 
+# Thermal
+on property:persist.device_config.vendor_system_native_boot.thermal_proactive_skin=1
+    setprop vendor.thermal.config "thermal_info_config_proactive_skin.json"
+
 # Bluetooth
 on post-fs-data
     chown bluetooth system /proc/bluetooth/timesync
@@ -73,28 +113,6 @@
     # Speaker amp permission
     chmod 644 /mnt/vendor/persist/audio/speaker.cal
 
-# Fingerprint
-on post-fs-data
-    chown system system /dev/goodix_fp
-    exec_background - system shell -- /vendor/bin/trusty_apploader /vendor/firmware/g7.app
-
-# Overrides fingerprint antispoof if following persist sysprops are set
-on boot && property:ro.build.type=userdebug && \
-           property:persist.vendor.fingerprint.disable.fake.override=0
-    setprop vendor.fingerprint.disable.fake ${persist.vendor.fingerprint.disable.fake.override}
-
-on boot && property:ro.build.type=userdebug && \
-           property:persist.vendor.fingerprint.disable.fake.override=1
-    setprop vendor.fingerprint.disable.fake ${persist.vendor.fingerprint.disable.fake.override}
-
-on boot && property:ro.build.type=userdebug && \
-           property:persist.vendor.fingerprint.disable.fake.override=100
-    setprop vendor.fingerprint.disable.fake ${persist.vendor.fingerprint.disable.fake.override}
-
-# Thermal
-on late-init
-    setprop persist.vendor.disable.thermal.control 1
-
 # Hall sensor
 on init && property:ro.bootmode=normal
     write /sys/devices/platform/hall_sensor/enable 0
@@ -106,8 +124,24 @@
 on property:persist.vendor.se.ese2.mode=ctsmode
     write /sys/class/st33spi/st33spi/st33spi_state 33
 
+# Allow secure_element group to read / write ST33 SPI state
+on post-fs-data
+    chown secure_element secure_element  /sys/class/st33spi/st33spi/st33spi_state
+    chmod 0660  /sys/class/st33spi/st33spi/st33spi_state
+
 # charger driver exposes now finer grain control, map demo mode to those properties
 # NOTE: demo mode can only be exit wiping data (which reset the persist properties)
 on property:sys.retaildemo.enabled=1
     setprop persist.vendor.charge.stop.level 35
     setprop persist.vendor.charge.start.level 30
+
+# WiFi
+on post-fs-data
+    setprop wifi.direct.interface p2p-dev-wlan0
+    setprop wifi.aware.interface aware_nmi0
+
+# For Japan sku, always enforce camera shutter sound
+# Since this property is read by the audio server in system service,
+# it should be written by the system init.
+on property:ro.boot.hardware.sku=G0B96
+    setprop audio.camerasound.force true
diff --git a/device-felix.mk b/device-felix.mk
index ccc2155..29ce0f0 100644
--- a/device-felix.mk
+++ b/device-felix.mk
@@ -23,25 +23,27 @@
 $(call inherit-product-if-exists, vendor/google_devices/gs201/proprietary/device-vendor.mk)
 $(call inherit-product-if-exists, vendor/google_devices/felix/proprietary/felix/device-vendor-felix.mk)
 $(call inherit-product-if-exists, vendor/google_devices/felix/proprietary/device-vendor.mk)
+$(call inherit-product-if-exists, vendor/google_devices/felix/proprietary/WallpapersFelix.mk)
 
 DEVICE_PACKAGE_OVERLAYS += device/google/felix/felix/overlay
 
 include device/google/felix/audio/felix/audio-tables.mk
 include device/google/gs201/device-shipping-common.mk
 $(call soong_config_set,fp_hal_feature,pixel_product, product_a)
-include hardware/google/pixel/vibrator/cs40l26/device-stereo.mk
-include device/google/gs101/bluetooth/bluetooth.mk
+include device/google/felix/vibrator/cs40l26/device.mk
+include device/google/gs-common/bcmbt/bluetooth.mk
+include device/google/gs-common/display/dump_second_display.mk
+include device/google/gs-common/touch/gti/gti.mk
+include device/google/gs-common/touch/stm/stm6.mk
 ifeq ($(filter factory_felix, $(TARGET_PRODUCT)),)
-include device/google/gs101/uwb/uwb.mk
 include device/google/felix/uwb/uwb_calibration.mk
 endif
 
+# go/lyric-soong-variables
+$(call soong_config_set,lyric,camera_hardware,felix)
 $(call soong_config_set,lyric,tuning_product,felix)
 $(call soong_config_set,google3a_config,target_device,felix)
 
-BOARD_SEPOLICY_DIRS += \
-    hardware/google/pixel-sepolicy/vibrator/common \
-
 # Init files
 PRODUCT_COPY_FILES += \
 	device/google/felix/conf/init.felix.rc:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.felix.rc
@@ -58,6 +60,9 @@
 PRODUCT_COPY_FILES += \
 	device/google/felix/media_profiles_felix.xml:$(TARGET_COPY_OUT_VENDOR)/etc/media_profiles_V1_0.xml
 
+# Media Performance Class 13
+PRODUCT_PROPERTY_OVERRIDES += ro.odm.build.media_performance_class=33
+
 # Display Config
 PRODUCT_COPY_FILES += \
 	device/google/felix/felix/display_colordata_cal1.pb:$(TARGET_COPY_OUT_VENDOR)/etc/display_colordata_cal1.pb \
@@ -65,11 +70,19 @@
 	device/google/felix/felix/display_golden_cal0.pb:$(TARGET_COPY_OUT_VENDOR)/etc/display_golden_cal0.pb \
 	device/google/felix/felix/display_golden_cal1.pb:$(TARGET_COPY_OUT_VENDOR)/etc/display_golden_cal1.pb
 
-# Display LBE
-PRODUCT_DEFAULT_PROPERTY_OVERRIDES += vendor.display.lbe.supported=1
+# Display
+PRODUCT_DEFAULT_PROPERTY_OVERRIDES += \
+	vendor.display.lbe.supported=1 \
+	vendor.display.async_off.supported=true \
+	ro.surface_flinger.ignore_hdr_camera_layers=true
 
 #config of display brightness dimming
-PRODUCT_DEFAULT_PROPERTY_OVERRIDES += vendor.display.brightness.dimming.usage=1
+PRODUCT_DEFAULT_PROPERTY_OVERRIDES += vendor.display.0.brightness.dimming.usage=1
+PRODUCT_DEFAULT_PROPERTY_OVERRIDES += vendor.display.1.brightness.dimming.usage=2
+
+# Early wake up sysfs path for the secondary display
+PRODUCT_DEFAULT_PROPERTY_OVERRIDES += \
+	vendor.display.secondary_early_wakeup_node=/sys/devices/platform/1c241000.drmdecon/early_wakeup
 
 # NFC
 PRODUCT_COPY_FILES += \
@@ -77,7 +90,6 @@
 	frameworks/native/data/etc/android.hardware.nfc.hce.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.hce.xml \
 	frameworks/native/data/etc/android.hardware.nfc.hcef.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.hcef.xml \
 	frameworks/native/data/etc/com.nxp.mifare.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/com.nxp.mifare.xml \
-	frameworks/native/data/etc/android.hardware.nfc.uicc.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.uicc.xml \
 	frameworks/native/data/etc/android.hardware.nfc.ese.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.ese.xml \
 	device/google/felix/nfc/libnfc-hal-st.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libnfc-hal-st.conf \
 	device/google/felix/nfc/libnfc-nci-felix.conf:$(TARGET_COPY_OUT_PRODUCT)/etc/libnfc-nci.conf
@@ -85,7 +97,7 @@
 PRODUCT_PACKAGES += \
 	NfcNci \
 	Tag \
-	android.hardware.nfc@1.2-service.st
+	android.hardware.nfc-service.st
 
 # SecureElement
 PRODUCT_PACKAGES += \
@@ -99,27 +111,62 @@
 	device/google/felix/nfc/libse-gto-hal2.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libse-gto-hal2.conf
 
 DEVICE_MANIFEST_FILE += \
-	device/google/felix/nfc/manifest_nfc.xml \
 	device/google/felix/nfc/manifest_se.xml
 
+# Thermal Config
+PRODUCT_COPY_FILES += \
+	device/google/felix/thermal_info_config_felix.json:$(TARGET_COPY_OUT_VENDOR)/etc/thermal_info_config.json \
+	device/google/felix/thermal_info_config_proactive_skin_felix.json:$(TARGET_COPY_OUT_VENDOR)/etc/thermal_info_config_proactive_skin.json \
+	device/google/felix/thermal_info_config_charge_felix.json:$(TARGET_COPY_OUT_VENDOR)/etc/thermal_info_config_charge.json
+
 # Power HAL config
 PRODUCT_COPY_FILES += \
 	device/google/felix/powerhint.json:$(TARGET_COPY_OUT_VENDOR)/etc/powerhint.json
 
 # Bluetooth HAL
-DEVICE_MANIFEST_FILE += \
-	device/google/felix/bluetooth/manifest_bluetooth.xml
-PRODUCT_SOONG_NAMESPACES += \
-        vendor/broadcom/bluetooth
-PRODUCT_PACKAGES += \
-	android.hardware.bluetooth@1.1-service.bcmbtlinux \
-	bt_vendor.conf
 PRODUCT_COPY_FILES += \
 	device/google/felix/bluetooth/bt_vendor_overlay.conf:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth/bt_vendor_overlay.conf
 PRODUCT_PROPERTY_OVERRIDES += \
     ro.bluetooth.a2dp_offload.supported=true \
     persist.bluetooth.a2dp_offload.disabled=false \
-    persist.bluetooth.a2dp_offload.cap=sbc-aac-aptx-aptxhd-ldac
+    persist.bluetooth.a2dp_offload.cap=sbc-aac-aptx-aptxhd-ldac-opus
+
+# Bluetooth Tx power caps
+PRODUCT_COPY_FILES += \
+    $(LOCAL_PATH)/bluetooth/bluetooth_power_limits_felix_US.csv:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_power_limits.csv \
+    $(LOCAL_PATH)/bluetooth/bluetooth_power_limits_felix_JP.csv:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_power_limits_JP.csv \
+    $(LOCAL_PATH)/bluetooth/bluetooth_power_limits_felix_EU.csv:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_power_limits_EU.csv \
+    $(LOCAL_PATH)/bluetooth/bluetooth_power_limits_felix_US.csv:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth_power_limits_US.csv
+
+# Spatial Audio
+PRODUCT_PACKAGES += \
+	libspatialaudio
+
+# optimize spatializer effect
+PRODUCT_PROPERTY_OVERRIDES += \
+       audio.spatializer.effect.util_clamp_min=300
+
+# declare use of spatial audio
+PRODUCT_PROPERTY_OVERRIDES += \
+       ro.audio.spatializer_enabled=true \
+       ro.audio.spatializer_transaural_enabled_default=false \
+       persist.vendor.audio.spatializer.speaker_enabled=true
+
+# Bluetooth SAR test tool
+PRODUCT_PACKAGES_DEBUG += \
+    sar_test
+
+# Bluetooth hci_inject test tool
+PRODUCT_PACKAGES_DEBUG += \
+    hci_inject
+
+# Bluetooth
+PRODUCT_PRODUCT_PROPERTIES += \
+    persist.bluetooth.a2dp_aac.vbr_supported=true
+
+# default BDADDR for EVB only
+PRODUCT_PROPERTY_OVERRIDES += \
+	ro.vendor.bluetooth.evb_bdaddr="22:22:22:33:44:55"
 
 # Keymaster HAL
 #LOCAL_KEYMASTER_PRODUCT_PACKAGE ?= android.hardware.keymaster@4.1-service
@@ -151,41 +198,37 @@
 # 	ro.hardware.keystore=software \
 # 	ro.hardware.gatekeeper=software
 
-# default BDADDR for EVB only
-PRODUCT_PROPERTY_OVERRIDES += \
-	ro.vendor.bluetooth.evb_bdaddr="22:22:22:33:44:55"
-
 # PowerStats HAL
 PRODUCT_SOONG_NAMESPACES += \
-    device/google/felix/powerstats/felix
-
-# Remove when b/182979111 is resolved.
-PRODUCT_DEFAULT_PROPERTY_OVERRIDES += ro.surface_flinger.primary_display_orientation=ORIENTATION_90
+    device/google/felix/powerstats/felix \
+    device/google/felix
 
 # Increment the SVN for any official public releases
 PRODUCT_VENDOR_PROPERTIES += \
-    ro.vendor.build.svn=1
+    ro.vendor.build.svn=19
 
 # Vibrator HAL
-PRODUCT_PRODUCT_PROPERTIES +=\
-    ro.vendor.vibrator.hal.long.frequency.shift=0
+PRODUCT_VENDOR_PROPERTIES +=\
+    ro.vendor.vibrator.hal.long.frequency.shift=0 \
+    ro.vendor.vibrator.hal.gpio.num=44 \
+    ro.vendor.vibrator.hal.gpio.shift=2
 ACTUATOR_MODEL := luxshare_ict_lt_xlra1906d
 
+# Fingerprint
+include device/google/gs101/fingerprint/fpc1540/sw42/fpc1540.mk
+FPC_MODULE_TYPE=1542_C
+# Fingerprint config
+include device/google/felix/fingerprint_config.mk
+
+# The default value of this variable is false and should only be set to true when
+# the device allows users to enable the seamless transfer feature.
+PRODUCT_PRODUCT_PROPERTIES += \
+   euicc.seamless_transfer_enabled_in_non_qs=true
+
 # DCK properties based on target
 PRODUCT_PROPERTY_OVERRIDES += \
-    ro.gms.dck.eligible_wcc=2
-
-# Bluetooth SAR test tool
-PRODUCT_PACKAGES_DEBUG += \
-    sar_test
-
-# Bluetooth
-PRODUCT_PRODUCT_PROPERTIES += \
-    persist.bluetooth.a2dp_aac.vbr_supported=true
-
-# Bluetooth HAL
-PRODUCT_PACKAGES += \
-	bt_vendor.conf
+    ro.gms.dck.eligible_wcc=3 \
+    ro.gms.dck.se_capability=1
 
 # Graphics
 PRODUCT_DEFAULT_PROPERTY_OVERRIDES += ro.surface_flinger.enable_frame_rate_override=true
@@ -200,7 +243,8 @@
 
 # SKU specific RROs
 PRODUCT_PACKAGES += \
-    SettingsOverlayGPQ72
+    SettingsOverlayG0B96 \
+    SettingsOverlayG9FPL
 
 # Trusty liboemcrypto.so
 PRODUCT_SOONG_NAMESPACES += vendor/google_devices/felix/prebuilts
@@ -211,8 +255,112 @@
 
 # Set support one-handed mode
 PRODUCT_PRODUCT_PROPERTIES += \
-    ro.support_one_handed_mode=true
+    ro.support_one_handed_mode=false
 
 # Hinge angle sensor
 PRODUCT_COPY_FILES += \
 	frameworks/native/data/etc/android.hardware.sensor.hinge_angle.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.sensor.hinge_angle.xml
+
+# Location
+ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT)))
+    PRODUCT_COPY_FILES += \
+        device/google/felix/location/gps.xml.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/gps.xml \
+        device/google/felix/location/lhd.conf.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/lhd.conf \
+        device/google/felix/location/scd.conf.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/scd.conf
+else
+    PRODUCT_COPY_FILES += \
+        device/google/felix/location/gps_user.xml.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/gps.xml \
+        device/google/felix/location/lhd_user.conf.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/lhd.conf \
+        device/google/felix/location/scd_user.conf.f10:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/scd.conf
+endif
+
+PRODUCT_PACKAGES += \
+        UwbOverlayF10 \
+        WifiOverlay2023Mid_F10
+
+# MIPI Coex Configs
+PRODUCT_COPY_FILES += \
+    device/google/felix/felix/radio/felix_camera_front_inner_mipi_coex_table.csv:$(TARGET_COPY_OUT_VENDOR)/etc/modem/camera_front_inner_mipi_coex_table.csv \
+    device/google/felix/felix/radio/felix_display_secondary_mipi_coex_table.csv:$(TARGET_COPY_OUT_VENDOR)/etc/modem/display_secondary_mipi_coex_table.csv
+
+PRODUCT_SOONG_NAMESPACES += device/google/felix
+
+DEVICE_PRODUCT_COMPATIBILITY_MATRIX_FILE += device/google/felix/device_framework_matrix_product_felix.xml
+
+# Device features
+PRODUCT_COPY_FILES += \
+    frameworks/native/data/etc/handheld_core_hardware.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/handheld_core_hardware.xml
+
+# Increase thread priority for nodes stop
+PRODUCT_VENDOR_PROPERTIES += \
+    persist.vendor.camera.increase_thread_priority_nodes_stop=true
+
+##Audio Vendor property
+PRODUCT_PROPERTY_OVERRIDES += \
+	persist.vendor.audio.cca.enabled=true
+
+# Camera
+PRODUCT_PROPERTY_OVERRIDES += \
+    persist.vendor.camera.adjust_backend_min_freq_for_1p_front_video_1080p_30fps=1 \
+    persist.vendor.camera.extended_launch_boost=1 \
+    persist.vendor.camera.multicam_streaming_boost=1 \
+    persist.vendor.camera.optimized_tnr_freq=1 \
+    persist.vendor.camera.raise_buf_allocation_priority=1 \
+    persist.vendor.camera.start_cpu_throttling_at_moderate_thermal=1 \
+    camera.enable_landscape_to_portrait=true \
+    persist.vendor.camera.debug.bypass_csi_link_error=true \
+    vendor.camera.allow_sensor_binning_aspect_ratio_to_override_itp_output=false \
+    vendor.camera.support_specific_stream_aspect_ratio=0.75
+
+# Enable camera exif model/make reporting
+PRODUCT_VENDOR_PROPERTIES += \
+    persist.vendor.camera.exif_reveal_make_model=true
+
+# Enable front camera always binning for 720P or smaller resolution
+PRODUCT_VENDOR_PROPERTIES += \
+    persist.vendor.camera.front_720P_always_binning=true
+
+# Bluetooth OPUS codec
+PRODUCT_PRODUCT_PROPERTIES += \
+    persist.bluetooth.opus.enabled=true
+
+# WLC userdebug specific
+ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT)))
+    PRODUCT_COPY_FILES += \
+        device/google/gs201/init.hardware.wlc.rc.userdebug:$(TARGET_COPY_OUT_VENDOR)/etc/init/init.wlc.rc
+endif
+
+# Bluetooth LE Audio
+PRODUCT_PRODUCT_PROPERTIES += \
+    ro.bluetooth.leaudio_offload.supported=true \
+    persist.bluetooth.leaudio_offload.disabled=false \
+    ro.bluetooth.leaudio_switcher.supported=true \
+    bluetooth.profile.bap.unicast.client.enabled=true \
+    bluetooth.profile.csip.set_coordinator.enabled=true \
+    bluetooth.profile.hap.client.enabled=true \
+    bluetooth.profile.mcp.server.enabled=true \
+    bluetooth.profile.ccp.server.enabled=true \
+    bluetooth.profile.vcp.controller.enabled=true \
+
+# Override BQR mask to enable LE Audio Choppy report
+ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT)))
+PRODUCT_PRODUCT_PROPERTIES += \
+    persist.bluetooth.bqr.event_mask=262238
+else
+PRODUCT_PRODUCT_PROPERTIES += \
+    persist.bluetooth.bqr.event_mask=94
+endif
+
+# Bluetooth LE Audio CIS handover to SCO
+# Set the property only if the controller doesn't support CIS and SCO
+# simultaneously. More details in b/242908683.
+PRODUCT_PRODUCT_PROPERTIES += \
+    persist.bluetooth.leaudio.notify.idle.during.call=true
+
+# LE Audio Offload Capabilities Setting
+PRODUCT_COPY_FILES += \
+    device/google/felix/bluetooth/le_audio_codec_capabilities.xml:$(TARGET_COPY_OUT_VENDOR)/etc/le_audio_codec_capabilities.xml
+
+# Bluetooth EWP test tool
+PRODUCT_PACKAGES_DEBUG += \
+    ewp_tool
diff --git a/device_framework_matrix_product_felix.xml b/device_framework_matrix_product_felix.xml
new file mode 100644
index 0000000..7f4a680
--- /dev/null
+++ b/device_framework_matrix_product_felix.xml
@@ -0,0 +1,10 @@
+<compatibility-matrix version="1.0" type="framework" level="7">
+    <hal format="aidl" optional="true">
+      <name>com.google.hardware.pixel.display</name>
+        <version>8</version>
+        <interface>
+            <name>IDisplay</name>
+            <instance>secondary</instance>
+        </interface>
+    </hal>
+</compatibility-matrix>
diff --git a/factory-images/generate-factory-images-package.sh b/factory-images/generate-factory-images-package.sh
new file mode 100755
index 0000000..c8058a0
--- /dev/null
+++ b/factory-images/generate-factory-images-package.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+# Copyright 2023 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source ../../../common/clear-factory-images-variables.sh
+BUILD=9548499
+DEVICE=felix
+PRODUCT=felix
+VERSION=td3a.230201.001
+SRCPREFIX=signed-
+BOOTLOADER=felix-1.0-9477737
+RADIO=g5300n-230112-230118-b-9502391
+source ../../../common/generate-factory-images-common.sh
diff --git a/factory_felix.mk b/factory_felix.mk
index 477055c..f689922 100644
--- a/factory_felix.mk
+++ b/factory_felix.mk
@@ -31,4 +31,4 @@
 	ro.vendor.bluetooth.evb_bdaddr="22:22:22:33:44:55"
 
 # Factory binary of camera
-PRODUCT_PACKAGES += fatp_imx363_hat_tool
+PRODUCT_PACKAGES += fatp_f10_wide_hat_tool fatp_f10_tele_hat_tool
diff --git a/felix/BoardConfig.mk b/felix/BoardConfig.mk
index 6f33c15..856eb42 100644
--- a/felix/BoardConfig.mk
+++ b/felix/BoardConfig.mk
@@ -18,8 +18,20 @@
 TARGET_SCREEN_DENSITY := 420
 BOARD_USES_GENERIC_AUDIO := true
 USES_DEVICE_GOOGLE_FELIX := true
+BOARD_KERNEL_CMDLINE += swiotlb=noforce
+
+# Enable load module in parallel
+BOARD_BOOTCONFIG += androidboot.load_modules_parallel=true
+
+# The modules which need to be loaded in sequential
+BOARD_KERNEL_CMDLINE += exynos_drm.load_sequential=1
+BOARD_KERNEL_CMDLINE += panel-samsung-ana6707-f10.load_sequential=1
+
+#Display
+USES_IDISPLAY_INTF_SEC := true
 
 include device/google/gs201/BoardConfig-common.mk
 -include vendor/google_devices/gs201/prebuilts/BoardConfigVendor.mk
 -include vendor/google_devices/felix/proprietary/BoardConfigVendor.mk
 include device/google/felix-sepolicy/felix-sepolicy.mk
+include device/google/felix/wifi/BoardConfig-wifi.mk
diff --git a/felix/display_colordata_cal1.pb b/felix/display_colordata_cal1.pb
index 1bef374..b266f90 100644
--- a/felix/display_colordata_cal1.pb
+++ b/felix/display_colordata_cal1.pb
Binary files differ
diff --git a/felix/display_colordata_dev_cal1.pb b/felix/display_colordata_dev_cal1.pb
index bce867a..fdbdb17 100644
--- a/felix/display_colordata_dev_cal1.pb
+++ b/felix/display_colordata_dev_cal1.pb
Binary files differ
diff --git a/felix/display_golden_cal0.pb b/felix/display_golden_cal0.pb
index c627c02..ab8423d 100644
--- a/felix/display_golden_cal0.pb
+++ b/felix/display_golden_cal0.pb
Binary files differ
diff --git a/felix/display_golden_cal1.pb b/felix/display_golden_cal1.pb
index 65e860a..e5aeb27 100644
--- a/felix/display_golden_cal1.pb
+++ b/felix/display_golden_cal1.pb
Binary files differ
diff --git a/felix/overlay/frameworks/base/core/res/res/values-sw600dp/config.xml b/felix/overlay/frameworks/base/core/res/res/values-sw600dp/config.xml
new file mode 100644
index 0000000..e728229
--- /dev/null
+++ b/felix/overlay/frameworks/base/core/res/res/values-sw600dp/config.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+/*
+** Copyright 2023, The Android Open Source Project
+**
+** Licensed under the Apache License, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+**
+**     http://www.apache.org/licenses/LICENSE-2.0
+**
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+*/
+-->
+
+<resources xmlns:xliff="urn:oasis:names:tc:xliff:document:1.2">
+    <!-- Height of the status bar for the portrait orientation.
+         Do not read this dimen directly. Use {@link SystemBarUtils#getStatusBarHeight} instead.
+         -->
+    <dimen name="status_bar_height_portrait">110px</dimen>
+</resources>
diff --git a/felix/overlay/frameworks/base/core/res/res/values/config.xml b/felix/overlay/frameworks/base/core/res/res/values/config.xml
index 0fbd648..1dae8a8 100644
--- a/felix/overlay/frameworks/base/core/res/res/values/config.xml
+++ b/felix/overlay/frameworks/base/core/res/res/values/config.xml
@@ -35,14 +35,14 @@
 
     <!-- Default screen brightness setting
          Must be in the range specified by minimum and maximum. -->
-    <item name="config_screenBrightnessSettingDefaultFloat" format="float" type="dimen">0.17293233082</item>
+    <item name="config_screenBrightnessSettingDefaultFloat" format="float" type="dimen">0.138</item>
 
     <!-- The default refresh rate. Pixel 6 manages this using the peak refresh rate setting, so set
          this value to 0 so it has no effect. -->
     <integer name="config_defaultRefreshRate">0</integer>
 
     <!-- The default peak refresh rate. -->
-    <integer name="config_defaultPeakRefreshRate">90</integer>
+    <integer name="config_defaultPeakRefreshRate">120</integer>
 
     <!-- Nonlinear coefficients for maximum panel brightness of 500 nits -->
     <string-array name="config_reduceBrightColorsCoefficientsNonlinear">
@@ -74,17 +74,15 @@
 
     <!-- Display cutout configuration -->
     <string translatable="false" name="config_secondaryBuiltInDisplayCutout">
-        M 505,61
-        a 35,35 0 1 0 70,0 35,35 0 1 0 -70,0
-        Z
-        @left
+      m 576.2,66.53 a 36.5,36.5 0 0 1 -36.5,36.5 36.5,36.5 0 0 1 -36.5,-36.5 36.5,36.5 0 0 1 36.5,-36.5 36.5,36.5 0 0 1 36.5,36.5 z
+      @left
     </string>
 
     <string translatable="false" name="config_secondaryBuiltInDisplayCutoutRectApproximation">
-        M 480,0
-        h 110
-        v 110
-        h -110
+        M 503.2,0
+        h 73
+        v 133
+        h 73
         Z
         @left
     </string>
@@ -95,7 +93,9 @@
     <!-- Height of the status bar.
          Do not read this dimen directly. Use {@link SystemBarUtils#getStatusBarHeight} instead.
          -->
-    <dimen name="status_bar_height">110px</dimen>
+    <dimen name="status_bar_height_default">110px</dimen>
+    <dimen name="status_bar_height_portrait">133px</dimen>
+    <dimen name="status_bar_height_landscape">110px</dimen>
 
     <!-- Adjustment for software rounded corners since corners aren't perfectly round. -->
     <dimen name="rounded_corner_radius_adjustment">5px</dimen>
@@ -115,6 +115,7 @@
         <item>4</item>
         <item>8</item>
         <item>12</item>
+        <item>15</item>
         <item>20</item>
         <item>33</item>
         <item>55</item>
@@ -125,10 +126,13 @@
         <item>665</item>
         <item>1097</item>
         <item>1808</item>
-        <item>2981</item>
-        <item>5000</item>
+        <item>3000</item>
+        <item>6000</item>
+        <item>9000</item>
         <item>10000</item>
+        <item>14000</item>
         <item>20000</item>
+        <item>25000</item>
     </integer-array>
 
     <!-- Array of desired screen brightness in nits corresponding to the lux values
@@ -145,27 +149,31 @@
       array. The brightness values must be non-negative and non-decreasing. This must be
       overridden in platform specific overlays -->
     <array name="config_autoBrightnessDisplayValuesNits">
-      <item>5.139055</item>       <!--  0 - 1 -->
-      <item>9.962018965</item>    <!--  1 - 2 -->
-      <item>18.34822964</item>    <!--  2 - 3 -->
-      <item>21.55068128</item>    <!--  3 - 4 -->
-      <item>24.0167788</item>     <!--  4 - 8 -->
-      <item>30.62162162</item>    <!--  8 - 12 -->
-      <item>35.09486396</item>    <!--  12 - 20 -->
-      <item>41.2249643</item>     <!--  20 - 33 -->
-      <item>47.6760716</item>     <!--  33 - 55 -->
-      <item>55.73002427</item>    <!--  55 - 90 -->
-      <item>66.24126116</item>    <!--  90 - 148 -->
-      <item>79.67614115</item>    <!--  148 - 245 -->
-      <item>98.04727274</item>    <!--  245 - 403 -->
-      <item>125.1221991</item>    <!--  403 - 665 -->
-      <item>161.6875093</item>    <!--  665 - 1097 -->
-      <item>208.4885553</item>    <!--  1097 - 1808 -->
-      <item>264.8221315</item>    <!--  1808 - 2981 -->
-      <item>327.8974352</item>    <!--  2981 - 5000 -->
-      <item>401.1676739</item>    <!--  5000 - 10000 -->
-      <item>750.0</item>          <!--  10000 -20000 -->
-      <item>900.0</item>          <!--  20000+ -->
+        <item>5.139055</item>       <!--  0 - 1 -->
+        <item>9.962018965</item>    <!--  1 - 2 -->
+        <item>18.34822964</item>    <!--  2 - 3 -->
+        <item>21.55068128</item>    <!--  3 - 4 -->
+        <item>24.0167788</item>     <!--  4 - 8 -->
+        <item>32.5</item>           <!--  8 - 12 -->
+        <item>46</item>             <!--  12 - 15 -->
+        <item>53.26923077</item>    <!--  15 - 20 -->
+        <item>54.61538462</item>    <!--  20 - 33 -->
+        <item>58.11538462</item>    <!--  33 - 55 -->
+        <item>62.1394</item>        <!--  55 - 90 -->
+        <item>67.13133333</item>    <!--  90 - 148 -->
+        <item>79.67614115</item>    <!--  148 - 245 -->
+        <item>98.04727274</item>    <!--  245 - 403 -->
+        <item>125.1221991</item>    <!--  403 - 665 -->
+        <item>161.6875093</item>    <!--  665 - 1097 -->
+        <item>208.4885553</item>    <!--  1097 - 1808 -->
+        <item>264.8221315</item>    <!--  1808 - 3000 -->
+        <item>328.5869521</item>    <!--  3000 - 6000 -->
+        <item>627.4315413</item>    <!--  6000 - 9000 -->
+        <item>826.8584866</item>    <!--  9000 - 10000 -->
+        <item>867.85582302</item>   <!--  10000 -14000 -->
+        <item>1041.39662279</item>  <!--  14000 -20000 -->
+        <item>1227.52633489</item>  <!--  20000 -25000 -->
+        <item>1331.28933608</item>  <!--  25000+ -->
     </array>
 
     <!-- Stability requirements in milliseconds for accepting a new brightness level.  This is used
@@ -173,19 +181,16 @@
          when adapting to brighter or darker environments.  This parameter controls how quickly
          brightness changes occur in response to an observed change in light level that exceeds the
          hysteresis threshold. -->
-    <integer name="config_autoBrightnessBrighteningLightDebounce">2000</integer>
+    <integer name="config_autoBrightnessBrighteningLightDebounce">1000</integer>
     <integer name="config_autoBrightnessDarkeningLightDebounce">4000</integer>
 
-    <!-- Type of the udfps long press sensor. Empty if long press is not supported. -->
-    <string name="config_dozeUdfpsLongPressSensorType" translatable="false">com.google.sensor.long_press</string>
-
     <!-- MMS user agent string -->
-    <string name="config_mms_user_agent" translatable="false">gb7n6</string>
+    <string name="config_mms_user_agent" translatable="false">g9fpl</string>
     <!-- MMS user agent profile url -->
-    <string name="config_mms_user_agent_profile_url" translatable="false">http://www.gstatic.com/android/sms/GB7N6.xml</string>
+    <string name="config_mms_user_agent_profile_url" translatable="false">http://www.gstatic.com/android/sms/G9FPL.xml</string>
 
-    <!-- Type of the quick pickup sensor. Empty if quick pickup is not supported. -->
-    <string name="config_quickPickupSensorType" translatable="false">com.google.sensor.quick_pickup</string>
+    <!-- The max vibration strength allowed in audio haptic channels. -->
+    <item name="config_hapticChannelMaxVibrationAmplitude" format="float" type="dimen">0.39</item>
 
     <!-- Not allow to switch to higher refresh rate when display brightness setting is
          equal or less than this value -->
@@ -199,7 +204,7 @@
     </integer-array>
 
     <!-- default refresh rate in the zone defined by birghtness and ambient thresholds -->
-    <integer name="config_defaultRefreshRateInZone">90</integer>
+    <integer name="config_defaultRefreshRateInZone">120</integer>
 
     <!-- The device states (supplied by DeviceStateManager) that should be treated as folded by the
          display fold controller. -->
@@ -213,19 +218,25 @@
     <!-- Indicates whether to enable hinge angle sensor when using unfold animation -->
     <bool name="config_unfoldTransitionHingeAngle">true</bool>
 
+    <!-- Timeout for receiving the keyguard drawn event from System UI.  -->
+    <integer name="config_keyguardDrawnTimeout">1700</integer>
+
+    <!-- If face auth sends the user directly to home/last open app, or stays on keyguard by default-->
+    <bool name="config_faceAuthDismissesKeyguard">true</bool>
+
     <bool name="config_supportsConcurrentInternalDisplays">false</bool>
 
     <!-- Radius of the software rounded corners at the top of primary display in its natural
         orientation. If zero, the value of rounded_corner_radius is used. -->
     <dimen name="rounded_corner_radius_top">52px</dimen>
     <!-- For secondary display -->
-    <dimen name="secondary_rounded_corner_radius_top">52px</dimen>
+    <dimen name="secondary_rounded_corner_radius_top">91px</dimen>
 
     <!-- Radius of the software rounded corners at the bottom of primary display in its natural
         orientation. If zero, the value of rounded_corner_radius is used. -->
     <dimen name="rounded_corner_radius_bottom">48px</dimen>
     <!-- For secondary display -->
-    <dimen name="secondary_rounded_corner_radius_bottom">48px</dimen>
+    <dimen name="secondary_rounded_corner_radius_bottom">91px</dimen>
 
     <!-- Top adjustment for the software rounded corners since corners are not perfectly
         round.  This value is used when retrieving the "radius" of the top rounded corner in cases
@@ -233,8 +244,6 @@
         rounded_corner_radius_top to more accurately provide a "radius" for the top rounded corners.
          -->
     <dimen name="rounded_corner_radius_top_adjustment">5px</dimen>
-    <!-- For secondary display -->
-    <dimen name="secondary_rounded_corner_radius_top_adjustment">5px</dimen>
 
     <!-- Bottom adjustment for the software rounded corners since corners are not perfectly
         round.  This value is used when retrieving the "radius" of the bottom rounded corner in
@@ -242,15 +251,132 @@
         rounded_corner_radius_bottom to more accurately provide a "radius" for the bottom rounded
         corners. -->
     <dimen name="rounded_corner_radius_bottom_adjustment">4px</dimen>
-    <!-- For secondary display -->
-    <dimen name="secondary_rounded_corner_radius_bottom_adjustment">4px</dimen>
-
-    <!-- the number of the max cached processes in the system. -->
-    <integer name="config_customizedMaxCachedProcesses">64</integer>
 
     <string-array name="config_displayUniqueIdArray" translatable="false">
         <item>"local:4619827677550801152"</item>
         <item>"local:4619827677550801153"</item>
     </string-array>
 
+    <!-- Boolean indicating if restoring network selection should be skipped -->
+    <!-- The restoring is handled by modem if it is true -->
+    <bool translatable="false" name="skip_restoring_network_selection">true</bool>
+
+    <integer-array name="config_ambientThresholdLevels">
+        <item>2</item>
+        <item>3</item>
+        <item>4</item>
+        <item>5</item>
+        <item>6</item>
+        <item>7</item>
+        <item>8</item>
+        <item>9</item>
+        <item>10</item>
+        <item>20</item>
+        <item>30</item>
+        <item>40</item>
+        <item>50</item>
+        <item>60</item>
+        <item>70</item>
+        <item>80</item>
+        <item>90</item>
+        <item>100</item>
+        <item>200</item>
+        <item>300</item>
+        <item>400</item>
+        <item>500</item>
+        <item>1000</item>
+        <item>2000</item>
+        <item>3000</item>
+        <item>4000</item>
+    </integer-array>
+
+    <integer-array name="config_ambientBrighteningThresholds">
+        <item>5186</item>
+        <item>4333</item>
+        <item>3666</item>
+        <item>2999</item>
+        <item>2759</item>
+        <item>2519</item>
+        <item>2279</item>
+        <item>2039</item>
+        <item>1799</item>
+        <item>799</item>
+        <item>527</item>
+        <item>499</item>
+        <item>470</item>
+        <item>517</item>
+        <item>565</item>
+        <item>612</item>
+        <item>660</item>
+        <item>708</item>
+        <item>742</item>
+        <item>636</item>
+        <item>582</item>
+        <item>549</item>
+        <item>369</item>
+        <item>294</item>
+        <item>269</item>
+        <item>220</item>
+        <item>220</item>
+    </integer-array>
+
+    <integer-array name="config_ambientDarkeningThresholds">
+        <item>525</item>
+        <item>683</item>
+        <item>666</item>
+        <item>650</item>
+        <item>640</item>
+        <item>630</item>
+        <item>620</item>
+        <item>610</item>
+        <item>600</item>
+        <item>500</item>
+        <item>500</item>
+        <item>440</item>
+        <item>385</item>
+        <item>382</item>
+        <item>379</item>
+        <item>376</item>
+        <item>373</item>
+        <item>371</item>
+        <item>367</item>
+        <item>387</item>
+        <item>397</item>
+        <item>403</item>
+        <item>380</item>
+        <item>345</item>
+        <item>333</item>
+        <item>283</item>
+        <item>283</item>
+    </integer-array>
+
+    <!-- A string config in svg path format for the main display shape.
+         (@see https://www.w3.org/TR/SVG/paths.html#PathData).
+
+         This config must be set unless:
+         1. {@link Configuration#isScreenRound} is true which means the display shape is circular
+            and the system will auto-generate a circular shape.
+         2. The display has no rounded corner and the system will auto-generate a rectangular shape.
+         (@see DisplayShape#createDefaultDisplayShape)
+
+         Note: If the display supports multiple resolutions, please define the path config based on
+         the highest resolution so that it can be scaled correctly in each resolution. -->
+    <string name="config_mainDisplayShape">M 100 0 C 85.508984 0.17732943 53.048104 0.19614615 50.220703 0.3125 C 46.59154 0.46184817 43.772284 0.73295581 41.220703 1.1679688 C 38.669124 1.6029816 37.395897 1.9206529 34.921875 2.7285156 C 32.447853 3.5363783 30.703329 4.1333351 26.476562 6.1855469 C 22.249798 8.2377586 19.650733 10.036004 17.412109 11.853516 C 15.173487 13.671026 13.194311 15.829318 11.78125 17.480469 C 10.368189 19.131618 9.7124678 20.077609 8.4746094 22.052734 C 7.2367508 24.027858 6.4508163 25.499897 5.3867188 28 C 4.3226211 30.500103 3.0570154 34.426858 2.375 36.919922 C 1.6929846 39.412984 1.4802708 40.78808 1.1132812 42.880859 C 0.7462918 44.973638 0.57743581 46.240459 0.38867188 49.041016 C 0.16693043 52.330833 0.48349037 76.000048 0 100 L 0 1744 C 0.46414424 1767.04 0.16213582 1789.7617 0.375 1792.9199 C 0.5562164 1795.6085 0.71800182 1796.8249 1.0703125 1798.834 C 1.4226231 1800.8431 1.6265082 1802.1633 2.28125 1804.5566 C 2.9359817 1806.9499 4.1503451 1810.719 5.171875 1813.1191 C 6.1934148 1815.5192 6.9464267 1816.9339 8.1347656 1818.8301 C 9.3231146 1820.7261 9.9520539 1821.6336 11.308594 1823.2188 C 12.665132 1824.8037 14.56772 1826.8763 16.716797 1828.6211 C 18.865874 1830.3659 21.360274 1832.0924 25.417969 1834.0625 C 29.475665 1836.0326 31.150324 1836.6054 33.525391 1837.3809 C 35.900446 1838.1565 37.122749 1838.4613 39.572266 1838.8789 C 42.021789 1839.2966 44.72889 1839.5579 48.212891 1839.7012 C 50.927192 1839.813 82.088619 1839.8298 96 1840 L 2112 1840 C 2125.9114 1839.8298 2157.0728 1839.813 2159.7871 1839.7012 C 2163.2712 1839.5579 2165.9782 1839.2966 2168.4277 1838.8789 C 2170.8772 1838.4613 2172.0995 1838.1565 2174.4746 1837.3809 C 2176.8496 1836.6054 2178.5243 1836.0326 2182.582 1834.0625 C 2186.6397 1832.0924 2189.1341 1830.3659 2191.2832 1828.6211 C 2193.4322 1826.8763 2195.3349 1824.8037 2196.6914 1823.2188 C 2198.048 1821.6336 2198.6769 1820.7261 2199.8652 1818.8301 C 2201.0536 1816.9339 2201.8066 1815.5192 2202.8281 1813.1191 C 2203.8497 1810.719 2205.064 1806.9499 2205.7188 1804.5566 C 2206.3733 1802.1633 2206.5774 1800.8431 2206.9297 1798.834 C 2207.282 1796.8249 2207.4458 1795.6085 2207.627 1792.9199 C 2207.8398 1789.7617 2207.536 1767.04 2208 1744 L 2208 100 C 2207.5164 76.000048 2207.833 52.330827 2207.6113 49.041016 C 2207.4225 46.24046 2207.2537 44.973645 2206.8867 42.880859 C 2206.5197 40.788083 2206.3071 39.412986 2205.625 36.919922 C 2204.943 34.426856 2203.6774 30.500104 2202.6133 28 C 2201.5492 25.499896 2200.7632 24.02785 2199.5254 22.052734 C 2198.2875 20.077608 2197.6317 19.131615 2196.2188 17.480469 C 2194.8058 15.829311 2192.8265 13.671032 2190.5879 11.853516 C 2188.3492 10.036008 2185.7502 8.2377527 2181.5234 6.1855469 C 2177.2967 4.1333309 2175.5521 3.536384 2173.0781 2.7285156 C 2170.6041 1.9206572 2169.3309 1.6029878 2166.7793 1.1679688 C 2164.2278 0.73295958 2161.4085 0.4618497 2157.7793 0.3125 C 2154.9519 0.19615024 2122.491 0.17732964 2108 0 L 100 0 z</string>
+
+    <!-- A string config in svg path format for the secondary display shape.
+         (@see https://www.w3.org/TR/SVG/paths.html#PathData).
+
+         This config must be set unless:
+         1. {@link Configuration#isScreenRound} is true which means the display shape is circular
+            and the system will auto-generate a circular shape.
+         2. The display has no rounded corner and the system will auto-generate a rectangular shape.
+         (@see DisplayShape#createDefaultDisplayShape)
+
+         Note: If the display supports multiple resolutions, please define the path config based on
+         the highest resolution so that it can be scaled correctly in each resolution. -->
+    <string name="config_secondaryDisplayShape">M 0 0 L 0 2092 L 1080 2092 L 1080 0 L 0 0 z M 0.00390625 0.01953125 L 124 0.01953125 C 120.62607 0.01953125 117.25272 0.062897597 113.87891 0.083984375 C 110.51044 0.15345796 107.14189 0.22554494 103.77344 0.29492188 C 100.41579 0.46723528 97.056902 0.63807032 93.699219 0.81054688 C 90.373874 1.1394815 87.049926 1.4682676 83.724609 1.796875 C 80.442364 2.3249488 77.159199 2.8527856 73.876953 3.3808594 C 70.680994 4.1567209 67.48502 4.933117 64.289062 5.7089844 C 61.206262 6.7649688 58.123836 7.8209034 55.041016 8.8769531 C 52.114502 10.229372 49.188251 11.581215 46.261719 12.933594 C 43.523829 14.593085 40.784745 16.252586 38.046875 17.912109 C 35.54087 19.873307 33.035436 21.835687 30.529297 23.796875 C 28.281876 26.043695 26.03451 28.29034 23.787109 30.537109 C 21.825326 33.047838 19.864128 35.557471 17.902344 38.068359 C 16.242372 40.800045 14.581846 43.531987 12.921875 46.263672 C 11.568993 49.19466 10.216047 52.125655 8.8632812 55.056641 C 7.807047 58.133103 6.7516762 61.210488 5.6953125 64.287109 C 4.9192068 67.487547 4.1432437 70.688232 3.3671875 73.888672 C 2.8389878 77.164433 2.3096105 80.440872 1.78125 83.716797 C 1.4522193 87.04105 1.12363 90.364877 0.79492188 93.689453 C 0.62263364 97.046037 0.44979383 100.40305 0.27734375 103.75977 C 0.20771199 107.1272 0.13750064 110.49376 0.068359375 113.86133 C 0.058717095 115.40631 0.01391657 122.4354 0.00390625 123.98047 C -0.0079363164 125.80834 0.015313378 -1.8083189 0.00390625 0.01953125 z M 956 0.01953125 L 1079.998 0.01953125 C 1079.9867 -1.8083196 1080.0071 125.80834 1079.9961 123.98047 C 1079.9861 122.4354 1079.9436 115.40631 1079.9336 113.86133 C 1079.8645 110.49376 1079.7927 107.1272 1079.7227 103.75977 C 1079.5502 100.40304 1079.3774 97.046035 1079.2051 93.689453 C 1078.8763 90.364875 1078.5477 87.041057 1078.2188 83.716797 C 1077.6905 80.440877 1077.163 77.164434 1076.6348 73.888672 L 1074.3066 64.287109 C 1073.2502 61.21048 1072.1929 58.133106 1071.1367 55.056641 C 1069.784 52.125655 1068.431 49.194657 1067.0781 46.263672 C 1065.418 43.531978 1063.7596 40.800035 1062.0996 38.068359 C 1060.1378 35.557468 1058.1747 33.047839 1056.2129 30.537109 C 1053.9655 28.290338 1051.7181 26.0437 1049.4707 23.796875 C 1046.9646 21.83568 1044.4591 19.873293 1041.9531 17.912109 C 1039.2153 16.252583 1036.4761 14.593089 1033.7383 12.933594 C 1030.8117 11.581217 1027.8856 10.229372 1024.959 8.8769531 C 1021.8762 7.8209026 1018.7938 6.7649692 1015.7109 5.7089844 C 1012.515 4.933117 1009.3189 4.1567207 1006.123 3.3808594 C 1002.8407 2.8527853 999.55759 2.324948 996.27539 1.796875 C 992.95004 1.4682674 989.62616 1.1394813 986.30078 0.81054688 C 982.94306 0.63807038 979.58423 0.46723542 976.22656 0.29492188 C 972.85807 0.22554451 969.48959 0.15345499 966.12109 0.083984375 C 962.74726 0.062904417 959.37395 0.01953125 956 0.01953125 z M 0.015625 1968 C 0.032745156 1971.3738 0.080078125 1974.7472 0.080078125 1978.1211 C 0.14382551 1981.4895 0.22555626 1984.8582 0.29101562 1988.2266 C 0.46100867 1991.5841 0.63698941 1994.941 0.80859375 1998.2988 C 1.1371999 2001.624 1.4647043 2004.9502 1.7949219 2008.2754 C 2.3229272 2011.5576 2.8526128 2014.8388 3.3789062 2018.1211 C 4.1553555 2021.3171 4.9304814 2024.513 5.7070312 2027.709 C 6.7632439 2030.7917 7.817277 2033.8762 8.875 2036.959 C 10.227391 2039.8856 11.578141 2042.8119 12.931641 2045.7383 C 14.591489 2048.4762 16.250812 2051.2132 17.910156 2053.9512 C 19.871723 2056.4573 21.833647 2058.9628 23.794922 2061.4688 C 26.041892 2063.7161 28.288387 2065.9635 30.535156 2068.2109 C 33.045978 2070.1727 35.557338 2072.1358 38.068359 2074.0977 C 40.800032 2075.7577 43.532001 2077.4162 46.263672 2079.0762 C 49.195245 2080.4289 52.125269 2081.7819 55.056641 2083.1348 C 58.133233 2084.191 61.210316 2085.2486 64.287109 2086.3047 C 67.48757 2087.0807 70.68811 2087.8567 73.888672 2088.6328 C 77.164765 2089.1611 80.440704 2089.6885 83.716797 2090.2168 C 87.041127 2090.5453 90.366976 2090.8741 93.691406 2091.2031 C 97.048366 2091.3756 100.40486 2091.5484 103.76172 2091.7207 C 107.12946 2091.7898 110.49741 2091.8597 113.86523 2091.9297 C 115.62196 2091.9407 122.22756 2091.9801 123.98438 2091.9941 C 125.60072 2092.0064 -1.6007186 2091.9941 0.015625 2091.9941 L 0.015625 1968 z M 1079.9844 1968 L 1079.9844 2091.9941 C 1081.6008 2091.9941 954.39928 2092.0064 956.01562 2091.9941 C 957.77244 2091.9801 964.37804 2091.9407 966.13477 2091.9297 C 969.50259 2091.8597 972.87054 2091.7898 976.23828 2091.7207 C 979.59514 2091.5484 982.95164 2091.3756 986.30859 2091.2031 C 989.63302 2090.8741 992.95888 2090.5453 996.2832 2090.2168 C 999.5593 2089.6885 1002.8352 2089.1611 1006.1113 2088.6328 C 1009.3119 2087.8567 1012.5124 2087.0807 1015.7129 2086.3047 C 1018.7897 2085.2486 1021.8668 2084.191 1024.9434 2083.1348 C 1027.8748 2081.7819 1030.8048 2080.4289 1033.7363 2079.0762 C 1036.468 2077.4162 1039.1999 2075.7577 1041.9316 2074.0977 C 1044.4426 2072.1358 1046.9539 2070.1727 1049.4648 2068.2109 C 1051.7115 2065.9635 1053.9581 2063.7161 1056.2051 2061.4688 C 1058.1664 2058.9628 1060.1282 2056.4573 1062.0898 2053.9512 C 1063.7491 2051.2132 1065.4086 2048.4762 1067.0684 2045.7383 C 1068.4219 2042.8119 1069.7726 2039.8856 1071.125 2036.959 C 1072.1828 2033.8762 1073.2368 2030.7917 1074.293 2027.709 C 1075.0695 2024.513 1075.8447 2021.3171 1076.6211 2018.1211 C 1077.1474 2014.8388 1077.6771 2011.5576 1078.2051 2008.2754 C 1078.5353 2004.9502 1078.8627 2001.624 1079.1914 1998.2988 C 1079.363 1994.941 1079.539 1991.5841 1079.709 1988.2266 C 1079.774 1984.8582 1079.8561 1981.4895 1079.9199 1978.1211 C 1079.9199 1974.7472 1079.9674 1971.3738 1079.9844 1968 z</string>
+
+    <!-- Whether we should persist the brightness value in nits for the default display even if
+         the underlying display device changes. -->
+    <bool name="config_persistBrightnessNitsForDefaultDisplay">true</bool>
 </resources>
diff --git a/felix/overlay/frameworks/base/core/res/res/xml/irq_device_map.xml b/felix/overlay/frameworks/base/core/res/res/xml/irq_device_map.xml
new file mode 100644
index 0000000..9b3e461
--- /dev/null
+++ b/felix/overlay/frameworks/base/core/res/res/xml/irq_device_map.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+**
+** Copyright 2023, The Android Open Source Project
+**
+** Licensed under the Apache License, Version 2.0 (the "License")
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+**
+**     http://www.apache.org/licenses/LICENSE-2.0
+**
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+*/
+-->
+<irq-device-map>
+    <device name="rtc-alarm0">
+        <subsystem>Alarm</subsystem>
+    </device>
+    <device name="dhdpcie_host_wake">
+        <subsystem>Wifi</subsystem>
+    </device>
+    <device name="cp2ap_wakeup">
+        <subsystem>Cellular_data</subsystem>
+    </device>
+    <device name="MAILBOX_AOCF12APx1100">
+        <subsystem>Sound_trigger</subsystem>
+    </device>
+    <device name="MAILBOX_AOCA322APx100">
+        <subsystem>Sensor</subsystem>
+    </device>
+</irq-device-map>
+
diff --git a/felix/overlay/frameworks/base/core/res/res/xml/power_profile.xml b/felix/overlay/frameworks/base/core/res/res/xml/power_profile.xml
index 2fe2aeb..b633087 100644
--- a/felix/overlay/frameworks/base/core/res/res/xml/power_profile.xml
+++ b/felix/overlay/frameworks/base/core/res/res/xml/power_profile.xml
@@ -17,6 +17,7 @@
 */
 -->
 <device name="Android">
+    <item name="battery.capacity">4727</item>
     <!-- Number of cores each CPU cluster contains -->
     <array name="cpu.clusters.cores">
       <value>4</value> <!-- Cluster 0 has 4 cores (cpu0, cpu1, cpu2, cpu3) -->
@@ -24,113 +25,129 @@
       <value>2</value> <!-- Cluster 2 has 2 cores (cpu6, cpu7) -->
     </array>
 
-    <item name="cpu.suspend">4.35</item>
-    <item name="cpu.idle">5.78</item>
-    <item name="cpu.active">2.35</item>
-    <item name="cpu.cluster_power.cluster0">32.58</item>
-    <item name="cpu.cluster_power.cluster1">6.44</item>
-    <item name="cpu.cluster_power.cluster2">0</item>
+    <item name="cpu.suspend">13.3</item>
+    <item name="cpu.idle">35.6</item>
+    <item name="cpu.active">8.2</item>
+    <item name="cpu.cluster_power.cluster0">0</item>
+    <item name="cpu.cluster_power.cluster1">1.16</item>
+    <item name="cpu.cluster_power.cluster2">1.53</item>
 
+    <!-- Different CPU speeds as reported in
+         /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies -->
     <array name="cpu.core_speeds.cluster0">
-      <value>300000</value>
-      <value>574000</value>
-      <value>738000</value>
-      <value>930000</value>
-      <value>1098000</value>
-      <value>1197000</value>
-      <value>1328000</value>
-      <value>1401000</value>
-      <value>1598000</value>
-      <value>1704000</value>
-      <value>1803000</value>
-      <value>1950000</value>
-      <value>2024000</value>
+      <value>300000</value> <!-- 300 MHz CPU speed -->
+      <value>574000</value> <!-- 574 MHz CPU speed -->
+      <value>738000</value> <!-- 738 MHz CPU speed -->
+      <value>930000</value> <!-- 930 MHz CPU speed -->
+      <value>1098000</value> <!-- 1098 MHz CPU speed -->
+      <value>1197000</value> <!-- 1197 MHz CPU speed -->
+      <value>1328000</value> <!-- 1328 MHz CPU speed -->
+      <value>1401000</value> <!-- 1401 MHz CPU speed -->
+      <value>1598000</value> <!-- 1598 MHz CPU speed -->
+      <value>1704000</value> <!-- 1704 MHz CPU speed -->
+      <value>1803000</value> <!-- 1803 MHz CPU speed -->
     </array>
 
+    <!-- Different CPU speeds as reported in
+         /sys/devices/system/cpu/cpufreq/policy4/scaling_available_frequencies -->
     <array name="cpu.core_speeds.cluster1">
-      <value>400000</value>
-      <value>553000</value>
-      <value>696000</value>
-      <value>799000</value>
-      <value>910000</value>
-      <value>1024000</value>
-      <value>1197000</value>
-      <value>1328000</value>
-      <value>1491000</value>
-      <value>1663000</value>
-      <value>1836000</value>
-      <value>1999000</value>
-      <value>2130000</value>
-      <value>2253000</value>
+      <value>400000</value> <!-- 400 MHz CPU speed -->
+      <value>553000</value> <!-- 553 MHz CPU speed -->
+      <value>696000</value> <!-- 696 MHz CPU speed -->
+      <value>799000</value> <!-- 799 MHz CPU speed -->
+      <value>910000</value> <!-- 910 MHz CPU speed -->
+      <value>1024000</value> <!-- 1024 MHz CPU speed -->
+      <value>1197000</value> <!-- 1197 MHz CPU speed -->
+      <value>1328000</value> <!-- 1328 MHz CPU speed -->
+      <value>1491000</value> <!-- 1491 MHz CPU speed -->
+      <value>1663000</value> <!-- 1663 MHz CPU speed -->
+      <value>1836000</value> <!-- 1836 MHz CPU speed -->
+      <value>1999000</value> <!-- 1999 MHz CPU speed -->
+      <value>2130000</value> <!-- 2130 MHz CPU speed -->
+      <value>2253000</value> <!-- 2253 MHz CPU speed -->
+      <value>2348000</value> <!-- 2348 MHz CPU speed -->
     </array>
 
+    <!-- Different CPU speeds as reported in
+         /sys/devices/system/cpu/cpufreq/policy6/scaling_available_frequencies -->
     <array name="cpu.core_speeds.cluster2">
-      <value>500000</value>
-      <value>851000</value>
-      <value>984000</value>
-      <value>1106000</value>
-      <value>1277000</value>
-      <value>1426000</value>
-      <value>1582000</value>
-      <value>1745000</value>
-      <value>1826000</value>
-      <value>2048000</value>
-      <value>2188000</value>
-      <value>2252000</value>
-      <value>2401000</value>
-      <value>2507000</value>
-      <value>2630000</value>
+      <value>500000</value> <!-- 500 MHz CPU speed -->
+      <value>851000</value> <!-- 851 MHz CPU speed -->
+      <value>984000</value> <!-- 984 MHz CPU speed -->
+      <value>1106000</value> <!-- 1106 MHz CPU speed -->
+      <value>1277000</value> <!-- 1277 MHz CPU speed -->
+      <value>1426000</value> <!-- 1426 MHz CPU speed -->
+      <value>1582000</value> <!-- 1582 MHz CPU speed -->
+      <value>1745000</value> <!-- 1745 MHz CPU speed -->
+      <value>1826000</value> <!-- 1826 MHz CPU speed -->
+      <value>2048000</value> <!-- 2048 MHz CPU speed -->
+      <value>2188000</value> <!-- 2188 MHz CPU speed -->
+      <value>2252000</value> <!-- 2252 MHz CPU speed -->
+      <value>2401000</value> <!-- 2401 MHz CPU speed -->
+      <value>2507000</value> <!-- 2507 MHz CPU speed -->
+      <value>2630000</value> <!-- 2630 MHz CPU speed -->
+      <value>2704000</value> <!-- 2704 MHz CPU speed -->
+      <value>2802000</value> <!-- 2802 MHz CPU speed -->
+      <value>2850000</value> <!-- 2850 MHz CPU speed -->
     </array>
 
+    <!-- Additional power used by a CPU core from cluster 0 when running at
+         different speeds, excluding cluster and active cost -->
     <array name="cpu.core_power.cluster0">
-      <value>13.58</value>
-      <value>38.22</value>
-      <value>48.59</value>
-      <value>64.02</value>
-      <value>79.69</value>
-      <value>89.66</value>
-      <value>105.64</value>
-      <value>113.30</value>
-      <value>142.24</value>
-      <value>158.91</value>
-      <value>180.73</value>
-      <value>229.19</value>
-      <value>266.66</value>
+      <value>4.71</value> <!-- 300 MHz CPU speed -->
+      <value>10.24</value> <!-- 574 MHz CPU speed -->
+      <value>13.43</value> <!-- 738 MHz CPU speed -->
+      <value>17.54</value> <!-- 930 MHz CPU speed -->
+      <value>20.79</value> <!-- 1098 MHz CPU speed -->
+      <value>22.82</value> <!-- 1197 MHz CPU speed -->
+      <value>25.55</value> <!-- 1328 MHz CPU speed -->
+      <value>27.03</value> <!-- 1401 MHz CPU speed -->
+      <value>38.2</value> <!-- 1598 MHz CPU speed -->
+      <value>46.69</value> <!-- 1704 MHz CPU speed -->
+      <value>60.01</value> <!-- 1803 MHz CPU speed -->
     </array>
 
+    <!-- Additional power used by a CPU core from cluster 1 when running at
+         different speeds, excluding cluster and active cost -->
     <array name="cpu.core_power.cluster1">
-      <value>59.00</value>
-      <value>87.69</value>
-      <value>114.54</value>
-      <value>134.19</value>
-      <value>157.72</value>
-      <value>184.69</value>
-      <value>229.99</value>
-      <value>264.08</value>
-      <value>316.56</value>
-      <value>375.74</value>
-      <value>450.94</value>
-      <value>529.79</value>
-      <value>603.34</value>
-      <value>684.48</value>
+      <value>8.03</value> <!-- 400 MHz CPU speed -->
+      <value>9.37</value> <!-- 553 MHz CPU speed -->
+      <value>11.14</value> <!-- 696 MHz CPU speed -->
+      <value>12.65</value> <!-- 799 MHz CPU speed -->
+      <value>14.5</value> <!-- 910 MHz CPU speed -->
+      <value>16.33</value> <!-- 1024 MHz CPU speed -->
+      <value>19.81</value> <!-- 1197 MHz CPU speed -->
+      <value>22.79</value> <!-- 1328 MHz CPU speed -->
+      <value>27.68</value> <!-- 1491 MHz CPU speed -->
+      <value>33.78</value> <!-- 1663 MHz CPU speed -->
+      <value>40.65</value> <!-- 1836 MHz CPU speed -->
+      <value>49.57</value> <!-- 1999 MHz CPU speed -->
+      <value>59.19</value> <!-- 2130 MHz CPU speed -->
+      <value>70.22</value> <!-- 2253 MHz CPU speed -->
+      <value>81</value> <!-- 2348 MHz CPU speed -->
     </array>
 
+    <!-- Additional power used by a CPU core from cluster 2 when running at
+         different speeds, excluding cluster and active cost -->
     <array name="cpu.core_power.cluster2">
-      <value>199.11</value>
-      <value>332.32</value>
-      <value>389.40</value>
-      <value>452.85</value>
-      <value>547.22</value>
-      <value>629.93</value>
-      <value>735.84</value>
-      <value>861.23</value>
-      <value>946.15</value>
-      <value>1137.98</value>
-      <value>1318.48</value>
-      <value>1396.56</value>
-      <value>1583.05</value>
-      <value>1811.61</value>
-      <value>2050.00</value>
+      <value>13.16</value> <!-- 500 MHz CPU speed -->
+      <value>19.29</value> <!-- 851 MHz CPU speed -->
+      <value>22.53</value> <!-- 984 MHz CPU speed -->
+      <value>26.11</value> <!-- 1106 MHz CPU speed -->
+      <value>31.73</value> <!-- 1277 MHz CPU speed -->
+      <value>38.12</value> <!-- 1426 MHz CPU speed -->
+      <value>45.44</value> <!-- 1582 MHz CPU speed -->
+      <value>53.15</value> <!-- 1745 MHz CPU speed -->
+      <value>57.1</value> <!-- 1826 MHz CPU speed -->
+      <value>71.92</value> <!-- 2048 MHz CPU speed -->
+      <value>83.89</value> <!-- 2188 MHz CPU speed -->
+      <value>90.36</value> <!-- 2252 MHz CPU speed -->
+      <value>108.58</value> <!-- 2401 MHz CPU speed -->
+      <value>129.22</value> <!-- 2507 MHz CPU speed -->
+      <value>147.88</value> <!-- 2630 MHz CPU speed -->
+      <value>164.96</value> <!-- 2704 MHz CPU speed -->
+      <value>188.15</value> <!-- 2802 MHz CPU speed -->
+      <value>202.77</value> <!-- 2850 MHz CPU speed -->
     </array>
 
     <!-- Additional power used when screen is ambient mode -->
@@ -156,15 +173,15 @@
     <item name="audio">75</item>
 
     <!-- Cellular modem related values.-->
-    <item name="modem.controller.sleep">0</item>
-    <item name="modem.controller.idle">156</item>
-    <item name="modem.controller.rx">145</item>
+    <item name="modem.controller.sleep">2.5</item>
+    <item name="modem.controller.idle">4.5</item>
+    <item name="modem.controller.rx">169</item>
     <array name="modem.controller.tx"> <!-- Strength 0 to 4 -->
-        <value>153</value>
-        <value>212</value>
-        <value>292</value>
-        <value>359</value>
-        <value>471</value>
+        <value>223</value>
+        <value>243</value>
+        <value>298</value>
+        <value>573</value>
+        <value>668</value>
     </array>
     <item name="modem.controller.voltage">3700</item>
 
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp-land/dimens.xml b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp-land/dimens.xml
new file mode 100644
index 0000000..d805e45
--- /dev/null
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp-land/dimens.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+ * Copyright (c) 2023, The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*/
+-->
+<resources>
+    <!-- Weather clock smartspace scaling to apply for the weather clock on tablets -->
+    <item name="weather_clock_smartspace_scale" type="dimen" format="float">0.85</item>
+    <dimen name="weather_clock_smartspace_translateX">-40dp</dimen>
+    <dimen name="weather_clock_smartspace_translateY">-26dp</dimen>
+</resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp/dimens.xml b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp/dimens.xml
new file mode 100644
index 0000000..d6c2dbb
--- /dev/null
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values-sw600dp/dimens.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+ * Copyright (c) 2023, The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*/
+-->
+<resources>
+    <!-- Weather clock smartspace scaling to apply for the weather clock on tablets -->
+    <dimen name="weather_clock_smartspace_translateX">-8dp</dimen>
+    <dimen name="weather_clock_smartspace_translateY">-16dp</dimen>
+</resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values/dimens.xml b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values/dimens.xml
new file mode 100644
index 0000000..d930b35
--- /dev/null
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res-keyguard/values/dimens.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+ * Copyright (c) 2023, The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*/
+-->
+<resources>
+    <!-- Weather clock smartspace positioning to apply for the weather clock on tablets -->
+    <dimen name="weather_clock_smartspace_translateX">-15dp</dimen>
+    <dimen name="weather_clock_smartspace_translateY">-26dp</dimen>
+</resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_bottom_secondary.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_bottom_secondary.xml
index 0b94bd0..5c2baed 100644
--- a/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_bottom_secondary.xml
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_bottom_secondary.xml
@@ -12,13 +12,13 @@
     limitations under the License.
 -->
 <vector xmlns:android="http://schemas.android.com/apk/res/android"
-    android:width="104px"
-    android:height="104px"
-    android:viewportWidth="104"
-    android:viewportHeight="104">
+    android:width="124px"
+    android:height="124px"
+    android:viewportWidth="124"
+    android:viewportHeight="124">
 
     <path
         android:fillColor="#000000"
-        android:pathData="M 104,0 C 86,0.036 61,0.26 51,0.7 48.43,0.82 45.77,1.16 43.81,1.42 41.66,1.7 38.64,2.35 36.36,3.06 34.07,3.77 31.98,4.52 27.59,6.65 23.21,8.79 20.47,10.65 18.19,12.53 c -2.32,1.89 -4.38,4.13 -5.84,5.84 -1.47,1.71 -2.15,2.69 -3.43,4.74 C 7.63,25.16 6.82,26.69 5.71,29.28 4.61,31.88 3.3,35.95 2.59,38.54 1.88,41.13 1.66,42.61 1.28,45 0.9,46.82 0.73,48 0.53,51 0.29,54.45 0.02,78 0,104 V 0 Z" />
+        android:pathData="m -0.2595961,0.2591722 c -1.605,0 124.7041761,-0.01235 123.0991761,2.75e-4 -1.7445,0.01372 -8.30417,0.05292 -10.04857,0.06376 -3.3442,0.06884 -6.6881,0.139273 -10.0322,0.207628 -3.333302,0.170329 -6.666902,0.340978 -10.000302,0.511466 -3.3011,0.32529 -6.6023,0.650099 -9.9033,0.975068 -3.2531,0.522192 -6.5062,1.044224 -9.7593,1.566576 -3.1781,0.767279 -6.3565,1.534558 -9.5345,2.30179 -3.0552,1.044223 -6.1103,2.088686 -9.1653,3.133022 -2.9108,1.3374958 -5.8211,2.6747658 -8.7321,4.0121508 -2.7125,1.641095 -5.4253,3.282173 -8.1378,4.923267 -2.4934,1.939474 -4.9871,3.878963 -7.4803,5.818437 -2.231,2.221843 -4.462,4.443751 -6.6932,6.665614 -1.947504,2.47764 -3.895104,4.955266 -5.842904,7.432875 -1.6477,2.706737 -3.2956,5.413473 -4.9438,8.120226 -1.344,2.89325 -2.6855001,5.786468 -4.0284001,8.679701 -1.0503,3.047762 -2.0975,6.09551 -3.1463,9.143256 -0.7711,3.159613 -1.5405,6.319272 -2.3115,9.478881 -0.5226,3.24492 -1.0486,6.4898 -1.5729,9.734716 -0.3279,3.2875 -0.6526,6.57502 -0.9789,9.86256 -0.1704,3.31949 -0.3442,6.63898 -0.513,9.958439 -0.065,3.33016 -0.1461,6.66029 -0.2094,9.99044 0,3.33548 -0.048,6.67092 -0.065,10.00642 z" />
 </vector>
 
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_top_secondary.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_top_secondary.xml
index 7731c14..cf558a7 100644
--- a/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_top_secondary.xml
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/drawable/rounded_corner_top_secondary.xml
@@ -12,13 +12,13 @@
     limitations under the License.
 -->
 <vector xmlns:android="http://schemas.android.com/apk/res/android"
-    android:width="104px"
-    android:height="104px"
-    android:viewportWidth="104"
-    android:viewportHeight="104">
+    android:width="124px"
+    android:height="124px"
+    android:viewportWidth="124"
+    android:viewportHeight="124">
 
     <path
         android:fillColor="#000000"
-        android:pathData="M 104,0 C 86,0 61,0.26 51,0.7 48.43,0.82 45.77,1.16 43.81,1.42 41.66,1.7 38.64,2.35 36.36,3.06 34.07,3.77 31.98,4.52 27.59,6.65 23.21,8.79 20.47,10.65 18.19,12.53 c -2.32,1.89 -4.38,4.13 -5.84,5.84 -1.47,1.71 -2.15,2.69 -3.43,4.74 C 7.63,25.16 6.82,26.69 5.71,29.28 4.61,31.88 3.3,35.95 2.59,38.54 1.88,41.13 1.66,42.61 1.28,45 0.9,46.82 0.73,48 0.53,51 0.29,54.45 0,78 0,104 V 0 Z" />
+        android:pathData="m 122.58619,3.1999995e-5 c -3.33555,0 -6.67094,0.04334 -10.0064,0.06428 -3.33016,0.06899 -6.66029,0.139606 -9.99045,0.2085 -3.319464,0.171114 -6.638954,0.342375 -9.958454,0.513651 -3.28753,0.326645 -6.575051,0.652803 -9.862553,0.979123 -3.244921,0.524398 -6.489794,1.048633 -9.734715,1.573031 -3.159614,0.770461 -6.319272,1.540922 -9.478886,2.311389 -3.047745,1.048634 -6.095492,2.097377 -9.143254,3.146076 -2.893234,1.343005 -5.786451,2.685914 -8.679702,4.02888 -2.706754,1.64794 -5.41349,3.295865 -8.120226,4.943837 -2.477509,1.947547 -4.955135,3.895118 -7.432775,5.842655 -2.221863,2.231181 -4.443771,4.462284 -6.665614,6.693415 -1.939474,2.493252 -3.878963,4.986664 -5.818437,7.480076 -1.641094,2.712671 -3.282172,5.425344 -4.923267,8.138016 -1.337496,2.910586 -2.674769,5.821332 -4.012151,8.731916 -1.044223,3.055047 -2.088671,6.110095 -3.133022,9.165301 -0.76728,3.17816 -1.534559,6.356323 -2.30179,9.534484 -0.522193,3.25296 -1.044224,6.506078 -1.566576,9.759199 -0.325289,3.301114 -0.650098,6.602388 -0.975068,9.903822 -0.170329,3.333219 -0.340977,6.666605 -0.511466,9.999957 -0.06884,3.344 -0.139273,6.68795 -0.207628,10.03208 C 0.05422341,114.58394 0.00989647,121.56369 0,123.098 -0.0117079,124.91315 0.01100341,-1.8151271 -2.74e-4,0 Z" />
 </vector>
 
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw410dp-land/dimen.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw410dp-land/dimen.xml
new file mode 100644
index 0000000..b590d1c
--- /dev/null
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw410dp-land/dimen.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+ * Copyright (c) 2023, The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*/
+-->
+
+<resources>
+    <!-- Auth credential PIN/PATTERN/PASSWORD -->
+    <dimen name="biometric_auth_pattern_view_size">248dp</dimen>
+    <dimen name="biometric_auth_pattern_view_max_size">348dp</dimen>
+</resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp-land/styles.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp-land/styles.xml
new file mode 100644
index 0000000..b104587
--- /dev/null
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp-land/styles.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Copyright (C) 2023 The Android Open Source Project
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+
+<resources xmlns:android="http://schemas.android.com/apk/res/android">
+
+    <style name="AuthCredentialPatternContainerStyle">
+        <item name="android:gravity">center</item>
+        <item name="android:maxHeight">@dimen/biometric_auth_pattern_view_max_size</item>
+        <item name="android:maxWidth">@dimen/biometric_auth_pattern_view_max_size</item>
+        <item name="android:minHeight">@dimen/biometric_auth_pattern_view_size</item>
+        <item name="android:minWidth">@dimen/biometric_auth_pattern_view_size</item>
+        <item name="android:paddingVertical">40dp</item>
+    </style>
+
+</resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp/dimens.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp/dimens.xml
index 1a3f800..292de87 100644
--- a/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp/dimens.xml
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/values-sw600dp/dimens.xml
@@ -23,4 +23,8 @@
 
     <!-- Location on the screen of the center of the physical fingerprint sensor -->
     <dimen name="physical_fingerprint_sensor_center_screen_location_x">2208px</dimen>
+
+    <!-- Lock pattern view size, align sysui biometric_auth_pattern_view_size -->
+    <dimen name="biometric_auth_pattern_view_size">298dp</dimen>
+    <dimen name="biometric_auth_pattern_view_max_size">348dp</dimen>
 </resources>
diff --git a/felix/overlay/frameworks/base/packages/SystemUI/res/values/config.xml b/felix/overlay/frameworks/base/packages/SystemUI/res/values/config.xml
index c438da7..16d2bb7 100644
--- a/felix/overlay/frameworks/base/packages/SystemUI/res/values/config.xml
+++ b/felix/overlay/frameworks/base/packages/SystemUI/res/values/config.xml
@@ -75,13 +75,10 @@
 
     <!-- Configure 13px of extra protection around the front-facing camera -->
     <string translatable="false" name="config_frontBuiltInDisplayCutoutProtection">
-        M 494,65
-        a 46,46 0 1 0 92,0
-        a 46,46 0 1 0 -92,0
-        Z
+      m 589.2,66.53 a 49.5,49.5 0 0 1 -49.5,49.5 49.5,49.5 0 0 1 -49.5,-49.5 49.5,49.5 0 0 1 49.5,-49.5 49.5,49.5 0 0 1 49.5,49.5 z
     </string>
 
-    <!-- Camera 1 is the front camera on barbet -->
+    <!-- Camera 0 is the front camera -->
     <string translatable="false" name="config_protectedCameraId">1</string>
 
     <!-- Comma-separated list of packages to exclude from camera protection. In our case,
@@ -89,5 +86,58 @@
     <string translatable="false" name="config_cameraProtectionExcludedPackages">com.google.android.as</string>
 
     <bool name="config_enableDisplayCutoutProtection">true</bool>
+
+    <!-- Type of a sensor that provides a low-power estimate of the desired display
+         brightness, suitable to listen to while the device is asleep (e.g. during
+         always-on display) -->
+    <string name="doze_brightness_sensor_type" translatable="false">com.google.sensor.binned_brightness</string>
+
+    <!-- Doze: can we assume the pickup sensor includes a proximity check? -->
+    <bool name="doze_pickup_performs_proximity_check">true</bool>
+
+    <!-- Doze: whether the double tap sensor reports 2D touch coordinates -->
+    <bool name="doze_double_tap_reports_touch_coordinates">true</bool>
+
+    <!-- Doze: Table that translates sensor values from the doze_brightness_sensor_type sensor
+               to brightness values; -1 means keeping the current brightness. -->
+    <integer-array name="config_doze_brightness_sensor_to_brightness">
+        <item>-1</item> <!-- 0: OFF -->
+        <item>3</item>  <!-- 1: NIGHT -->
+        <item>3</item>  <!-- 2: LOW -->
+        <item>13</item> <!-- 3: HIGH -->
+        <item>13</item> <!-- 4: SUN -->
+    </integer-array>
+
+    <!-- Doze: Table that translates sensor values from the doze_brightness_sensor_type sensor
+               to an opacity value for a black scrim that is overlaid in AOD1.
+               Valid range is from 0 (transparent) to 255 (opaque).
+               -1 means keeping the current opacity. -->
+    <integer-array name="config_doze_brightness_sensor_to_scrim_opacity">
+        <item>-1</item>   <!-- 0: OFF -->
+        <item>133</item>  <!-- 1: NIGHT -->
+        <item>0</item>    <!-- 2: LOW -->
+        <item>0</item>    <!-- 3: HIGH -->
+        <item>0</item>    <!-- 4: SUN -->
+    </integer-array>
+
+    <!-- Doze: Name of a sensor per posture state that provides a low-power estimate of the desired
+               display brightness, suitable to listen to while the device is asleep (e.g. during
+               always-on display) -->
+    <string-array name="doze_brightness_sensor_name_posture_mapping" translatable="false">
+        <item></item> <!-- UNKNOWN -->
+        <item>Binned Brightness 1 (wake-up)</item> <!-- CLOSED -->
+        <item>Binned Brightness 0 (wake-up)</item> <!-- HALF_OPENED -->
+        <item>Binned Brightness 0 (wake-up)</item> <!-- OPENED -->
+    </string-array>
+
+    <!-- Whether to only support face auth on specific posture, default 0(DEVICE_POSTURE_UNKNOWN)
+         to support face all postures.
+         0 : DEVICE_POSTURE_UNKNOWN
+         1 : DEVICE_POSTURE_CLOSED
+         2 : DEVICE_POSTURE_HALF_OPENED
+         3 : DEVICE_POSTURE_OPENED
+         4 : DEVICE_POSTURE_FLIPPED
+    -->
+    <integer name="config_face_auth_supported_posture">1</integer>
 </resources>
 
diff --git a/felix/overlay/packages/apps/Nfc/res/values/config.xml b/felix/overlay/packages/apps/Nfc/res/values/config.xml
index 201f9d1..5e89b28 100644
--- a/felix/overlay/packages/apps/Nfc/res/values/config.xml
+++ b/felix/overlay/packages/apps/Nfc/res/values/config.xml
@@ -16,8 +16,20 @@
 <resources>
   <bool name="nfcc_always_on_allowed">true</bool>
   <string-array name="config_skuSupportsSecureNfc" translatable="false">
-    <item>GFQM1</item>
-    <item>GPQ72</item>
-    <item>GNA8F</item>
+    <item>G9FPL</item>
+    <item>G0B96</item>
   </string-array>
+  <bool name="tag_intent_app_pref_supported">true</bool>
+  <!-- NFC Antenna Location API -->
+  <integer name="device_width">160</integer>
+  <integer name="device_height">140</integer>
+  <bool name="device_foldable">true</bool>
+  <integer-array name="antenna_x">
+    <item>90</item>
+    <item>30</item>
+  </integer-array>
+  <integer-array name="antenna_y">
+    <item>103</item>
+    <item>103</item>
+  </integer-array>
 </resources>
diff --git a/felix/overlay/packages/apps/OMA-DM/DMService/res/values/config.xml b/felix/overlay/packages/apps/OMA-DM/DMService/res/values/config.xml
new file mode 100644
index 0000000..25f2ef3
--- /dev/null
+++ b/felix/overlay/packages/apps/OMA-DM/DMService/res/values/config.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- These resources are around just to allow their values to be customized
+     for different hardware and product builds. -->
+<resources xmlns:xliff="urn:oasis:names:tc:xliff:document:1.2">
+
+    <!-- set this to ./DevInfo/Mod -->
+    <string translatable="false" name="config_devinfo_model">G9FPL</string>
+</resources>
diff --git a/felix/overlay/packages/apps/Settings/res/values/config.xml b/felix/overlay/packages/apps/Settings/res/values/config.xml
new file mode 100644
index 0000000..2bec86e
--- /dev/null
+++ b/felix/overlay/packages/apps/Settings/res/values/config.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<resources xmlns:xliff="urn:oasis:names:tc:xliff:document:1.2">
+    <!--Whether the Face enroll confirmation page show finish large icon. -->
+    <bool name="config_face_enroll_confirmation_show_illustration">false</bool>
+</resources>
diff --git a/felix/overlay/packages/apps/Settings/res/values/dimens.xml b/felix/overlay/packages/apps/Settings/res/values/dimens.xml
new file mode 100755
index 0000000..e6b49b4
--- /dev/null
+++ b/felix/overlay/packages/apps/Settings/res/values/dimens.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Copyright (C) 2023 The Android Open Source Project
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+
+<resources>
+    <!-- Biometrics Face enroll education dimensions-->
+    <dimen name="face_enroll_icon_large_width">200dp</dimen>
+    <dimen name="face_enroll_icon_large_height">200dp</dimen>
+    <dimen name="illustration_lottie_height">330dp</dimen>
+    <dimen name="illustration_accessibility_margin_top">-24dp</dimen>
+    <dimen name="face_enroll_education_lottie_frame_margin_top">-36dp</dimen>
+    <dimen name="lottie_animation_view_margin_top">-64dp</dimen>
+    <dimen name="limited_vision_button_frame_margin_top">-36dp</dimen>
+    <dimen name="limited_vision_button_margin_top">12dp</dimen>
+    <dimen name="limited_vision_button_margin_bottom">12dp</dimen>
+    <dimen name="limited_vision_button_toggle_margin_top">-28dp</dimen>
+</resources>
diff --git a/felix/overlay_packages/SettingsOverlayGPQ72/Android.bp b/felix/overlay_packages/SettingsOverlayG0B96/Android.bp
similarity index 78%
copy from felix/overlay_packages/SettingsOverlayGPQ72/Android.bp
copy to felix/overlay_packages/SettingsOverlayG0B96/Android.bp
index 93a1620..f39ee73 100644
--- a/felix/overlay_packages/SettingsOverlayGPQ72/Android.bp
+++ b/felix/overlay_packages/SettingsOverlayG0B96/Android.bp
@@ -3,6 +3,6 @@
 }
 
 runtime_resource_overlay {
-    name: "SettingsOverlayGPQ72",
+    name: "SettingsOverlayG0B96",
     product_specific: true,
 }
diff --git a/felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml b/felix/overlay_packages/SettingsOverlayG0B96/AndroidManifest.xml
similarity index 75%
rename from felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml
rename to felix/overlay_packages/SettingsOverlayG0B96/AndroidManifest.xml
index 10bf5a3..bd79323 100644
--- a/felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml
+++ b/felix/overlay_packages/SettingsOverlayG0B96/AndroidManifest.xml
@@ -1,9 +1,9 @@
 <?xml version="1.0" encoding="utf-8"?>
 <manifest xmlns:android="http://schemas.android.com/apk/res/android"
-    package="com.android.settings.overlay.gpq72">
+    package="com.android.settings.overlay.g0b96">
     <application android:hasCode="false" />
     <overlay android:targetPackage="com.android.settings"
              android:requiredSystemPropertyName="ro.boot.hardware.sku"
-             android:requiredSystemPropertyValue="GPQ72"
+             android:requiredSystemPropertyValue="G0B96"
              android:isStatic="true" />
 </manifest>
diff --git a/felix/overlay_packages/SettingsOverlayG0B96/res/drawable/regulatory_info.png b/felix/overlay_packages/SettingsOverlayG0B96/res/drawable/regulatory_info.png
new file mode 100644
index 0000000..81d2764
--- /dev/null
+++ b/felix/overlay_packages/SettingsOverlayG0B96/res/drawable/regulatory_info.png
Binary files differ
diff --git a/felix/overlay_packages/SettingsOverlayGPQ72/Android.bp b/felix/overlay_packages/SettingsOverlayG9FPL/Android.bp
similarity index 78%
rename from felix/overlay_packages/SettingsOverlayGPQ72/Android.bp
rename to felix/overlay_packages/SettingsOverlayG9FPL/Android.bp
index 93a1620..c9270b2 100644
--- a/felix/overlay_packages/SettingsOverlayGPQ72/Android.bp
+++ b/felix/overlay_packages/SettingsOverlayG9FPL/Android.bp
@@ -3,6 +3,6 @@
 }
 
 runtime_resource_overlay {
-    name: "SettingsOverlayGPQ72",
+    name: "SettingsOverlayG9FPL",
     product_specific: true,
 }
diff --git a/felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml b/felix/overlay_packages/SettingsOverlayG9FPL/AndroidManifest.xml
similarity index 75%
copy from felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml
copy to felix/overlay_packages/SettingsOverlayG9FPL/AndroidManifest.xml
index 10bf5a3..d065089 100644
--- a/felix/overlay_packages/SettingsOverlayGPQ72/AndroidManifest.xml
+++ b/felix/overlay_packages/SettingsOverlayG9FPL/AndroidManifest.xml
@@ -1,9 +1,9 @@
 <?xml version="1.0" encoding="utf-8"?>
 <manifest xmlns:android="http://schemas.android.com/apk/res/android"
-    package="com.android.settings.overlay.gpq72">
+    package="com.android.settings.overlay.g9fpl">
     <application android:hasCode="false" />
     <overlay android:targetPackage="com.android.settings"
              android:requiredSystemPropertyName="ro.boot.hardware.sku"
-             android:requiredSystemPropertyValue="GPQ72"
+             android:requiredSystemPropertyValue="G9FPL"
              android:isStatic="true" />
 </manifest>
diff --git a/felix/overlay_packages/SettingsOverlayG9FPL/res/drawable/regulatory_info.png b/felix/overlay_packages/SettingsOverlayG9FPL/res/drawable/regulatory_info.png
new file mode 100644
index 0000000..f69084e
--- /dev/null
+++ b/felix/overlay_packages/SettingsOverlayG9FPL/res/drawable/regulatory_info.png
Binary files differ
diff --git a/felix/overlay_packages/SettingsOverlayGPQ72/res/drawable/regulatory_info.png b/felix/overlay_packages/SettingsOverlayGPQ72/res/drawable/regulatory_info.png
deleted file mode 100644
index f2b2358..0000000
--- a/felix/overlay_packages/SettingsOverlayGPQ72/res/drawable/regulatory_info.png
+++ /dev/null
Binary files differ
diff --git a/felix/radio/felix_camera_front_inner_mipi_coex_table.csv b/felix/radio/felix_camera_front_inner_mipi_coex_table.csv
new file mode 100644
index 0000000..a3312b6
--- /dev/null
+++ b/felix/radio/felix_camera_front_inner_mipi_coex_table.csv
@@ -0,0 +1,3 @@
+706560,718850
+
+2427000,2442000,706560
diff --git a/felix/radio/felix_display_secondary_mipi_coex_table.csv b/felix/radio/felix_display_secondary_mipi_coex_table.csv
new file mode 100644
index 0000000..e28cbcc
--- /dev/null
+++ b/felix/radio/felix_display_secondary_mipi_coex_table.csv
@@ -0,0 +1,7 @@
+730000,670000
+
+1810000,1835000,670000
+720000,740000,670000
+0,710000,730000
+750000,1800000,730000
+1845000,50000000,730000
diff --git a/fingerprint_config.mk b/fingerprint_config.mk
new file mode 100644
index 0000000..1f9b521
--- /dev/null
+++ b/fingerprint_config.mk
@@ -0,0 +1,11 @@
+# Factory build, use HIDL hal & extension so that we can use Test tool
+ifneq ( ,$(findstring factory, $(TARGET_PRODUCT)))
+GOOGLE_CONFIG_FP_STATUS=1
+FPC_CONFIG_TRUSTY_CLEAN_TA=1
+else
+# Non factory build, use fingerprint AIDL version
+GOOGLE_CONFIG_POWER_NODE=/dev/input/event2
+GOOGLE_CONFIG_DP_COUNT=2
+GOOGLE_CONFIG_FP_STATUS=1
+GOOGLE_CONFIG_TOUCH_TO_UNLOCK_ANYTIME=1
+endif
diff --git a/init.insmod.felix.cfg b/init.insmod.felix.cfg
index dba37ec..5693443 100644
--- a/init.insmod.felix.cfg
+++ b/init.insmod.felix.cfg
@@ -8,11 +8,12 @@
 # Modules here will be loaded *after* all common modules
 modprobe|bcmdhd4389.ko
 modprobe|snd-soc-cs35l41-i2c.ko
+modprobe|fst2.ko
 modprobe|ftm5.ko
-modprobe|sec_touch.ko
-modprobe|cl_dsp.ko
-modprobe|input-cs40l26-i2c.ko
+modprobe|cs40l26-i2c.ko
 modprobe|snd-soc-cs40l26.ko
 
 # All device specific modules loaded
 setprop|vendor.device.modules.ready
+setprop|vendor.all.modules.ready
+setprop|vendor.all.devices.ready
diff --git a/location/gps.xml.f10 b/location/gps.xml.f10
new file mode 100644
index 0000000..6e005ae
--- /dev/null
+++ b/location/gps.xml.f10
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="utf-8"?>
+<glgps xmlns="http://www.glpals.com/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.glpals.com/ glconfig.xsd" >
+  <hal
+       PortName="/dev/ttyBCM"
+       BaudRate="921600"
+       GpioNStdbyPath="/sys/devices/platform/10940000.spi/spi_master/spi5/spi5.0/nstandby"
+       CustGpioDelayMs="250"
+       LogEnabled="true"
+       Log="JAVA"
+       SecondaryConfigPath="/data/vendor/gps/overlay/gps_overlay.xml"
+       LogDirectory="/sdcard/gps/broadcom/storage/"
+       CtrlPipe="/data/vendor/gps/glgpsctrl"
+       NmeaOutName="/data/vendor/gps/nmea_out"
+
+       acSuplServer="supl.google.com"
+       SuplPort="7275"
+       SuplLogEnable="true"
+       SuplLogFullName="/data/vendor/gps/suplflow.txt"
+       tlsEnable="true"
+
+       SuplSslMethod="SSLv23_NO_TLSv1_2"
+       SuplEnable="true"
+       SuplUseApn="false"
+       SuplUseApnNI="true"
+       SuplUseFwCellInfo="false"
+       SuplDummyCellInfo ="true"
+       SuplTlsCertDirPath="/etc/security/cacerts"
+       SuplTlsCertPath="/vendor/etc/gnss/gps.cer"
+       SuplUT1Seconds="20"
+       SuplUT2Seconds="20"
+       SuplUT3Seconds="20"
+       TcpConnectionTimeout="20"
+       SuplLppCapable="true"
+       SuplEcidCapable="true"
+       SuplVersion="2"
+       SuplMinorVersion="0"
+       SuplOtdoaCapable="true"
+       SuplOtdoaCapable2="true"
+       SuplGlonassCapable = "true"
+       SuplGalileoCapable = "true"
+       SuplBdsCapable = "true"
+       SuplMgpsCapable = "true"
+
+       RtoEnable="true"
+       RtiEnable="true"
+       HttpSyncLto="true"
+       LtoFileName="lto2.dat"
+       LtoDir="/data/vendor/gps/"
+       LtoSyncThresholdDays="1"
+
+       GnssYearOfHardware="2020"
+       CpGuardTimeSec="1"
+       CpLppGuardTimeSec="1"
+       IgnoreInjectedSystemTime="true"
+
+       AttributionAppPkgName="com.google.android.carrierlocation"
+
+       AssertEnabled="true"
+       CpLppeCancelDbhOnAgnssProvideLoc="true"
+       CpLppeUseAgnssLocForEmptyDbh="true"
+       ReAidingOnHotStart="false"
+       ReAidingIntervalSec="1200"
+       RuntimeSwLteFilterEnable="true"
+       PpsDevice="/sys/class/pps/pps0/assert_elapsed"
+  />
+
+  <gll
+       PpsEnable="true"
+       LogPriMask="LOG_INFO"
+       LogFacMask="LOG_NMEA | LOG_GLLIOS | LOG_GLLAPI"
+       FrqPlan="FRQ_PLAN_26MHZ_2PPM_49_152MHZ_300PPB"
+       MultiCarrRFMode="GL_MULTI_CARR_RF_MODE_L1_L5"
+       MultiCarrLnaMask="L1_EXT_ON|L5_EXT_ON"
+       RfType="GL_RF_4776_BRCM"
+       ExtL5Bias="13.0"
+
+       WarmStandbyTimeout1Seconds="10"
+       WarmStandbyTimeout2Seconds="15"
+
+       EnableGnssPropagateInStandby="true"
+
+       RfPathLossDb_Ap="2.9"
+       RfPathLossDb_Cp="2.9"
+       RfPathLossDb_Ap_L5="3.7"
+       RfPathLossDb_Cp_L5="3.7"
+       OnChipGpsCarrierType="3,2,3,3,2,3,2,3,3,3,1,2,1,3,2,1,2,3,1,1,1,1,3,3,3,3,3,1,2,3,2,3"
+
+       EnableOnChipStopNotification="2"
+       PowerMode="3"
+       MinGpsWeekNumber="2216"
+       OnChipAccMask="50"
+  />
+
+  <gll_features
+       EnableNicAutoSwitch="true"
+       EnableNavic="true"
+  />
+
+</glgps>
+
diff --git a/location/gps_user.xml.f10 b/location/gps_user.xml.f10
new file mode 100644
index 0000000..02afd01
--- /dev/null
+++ b/location/gps_user.xml.f10
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="utf-8"?>
+<glgps xmlns="http://www.glpals.com/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.glpals.com/ glconfig.xsd" >
+  <hal
+       PortName="/dev/ttyBCM"
+       BaudRate="921600"
+       GpioNStdbyPath="/sys/devices/platform/10940000.spi/spi_master/spi5/spi5.0/nstandby"
+       CustGpioDelayMs="250"
+       LogEnabled="false"
+       Log="JAVA"
+       LogDirectory="/sdcard/gps/broadcom/storage/"
+       CtrlPipe="/data/vendor/gps/glgpsctrl"
+       NmeaOutName="/data/vendor/gps/nmea_out"
+
+       acSuplServer="supl.google.com"
+       SuplPort="7275"
+       SuplLogEnable="false"
+       SuplLogFullName="/data/vendor/gps/suplflow.txt"
+       tlsEnable="true"
+
+       SuplSslMethod="SSLv23_NO_TLSv1_2"
+       SuplEnable="true"
+       SuplUseApn="false"
+       SuplUseApnNI="true"
+       SuplUseFwCellInfo="false"
+       SuplDummyCellInfo ="true"
+       SuplTlsCertDirPath="/etc/security/cacerts"
+       SuplTlsCertPath="/vendor/etc/gnss/gps.cer"
+       SuplUT1Seconds="20"
+       SuplUT2Seconds="20"
+       SuplUT3Seconds="20"
+       TcpConnectionTimeout="20"
+       SuplLppCapable="true"
+       SuplEcidCapable="true"
+       SuplVersion="2"
+       SuplMinorVersion="0"
+       SuplOtdoaCapable="true"
+       SuplOtdoaCapable2="true"
+       SuplGlonassCapable = "true"
+       SuplGalileoCapable = "true"
+       SuplBdsCapable = "true"
+       SuplMgpsCapable = "true"
+
+       RtoEnable="true"
+       RtiEnable="true"
+       HttpSyncLto="true"
+       LtoFileName="lto2.dat"
+       LtoDir="/data/vendor/gps/"
+       LtoSyncThresholdDays="1"
+
+       GnssYearOfHardware="2020"
+       CpGuardTimeSec="1"
+       CpLppGuardTimeSec="1"
+       IgnoreInjectedSystemTime="true"
+
+       AttributionAppPkgName="com.google.android.carrierlocation"
+
+       AssertEnabled="false"
+       CpLppeCancelDbhOnAgnssProvideLoc="true"
+       CpLppeUseAgnssLocForEmptyDbh="true"
+       ReAidingOnHotStart="false"
+       ReAidingIntervalSec="1200"
+       RuntimeSwLteFilterEnable="true"
+       PpsDevice="/sys/class/pps/pps0/assert_elapsed"
+  />
+
+  <gll
+       PpsEnable="true"
+       LogPriMask="LOG_INFO"
+       LogFacMask="LOG_NMEA | LOG_GLLIOS | LOG_GLLAPI"
+       FrqPlan="FRQ_PLAN_26MHZ_2PPM_49_152MHZ_300PPB"
+       MultiCarrRFMode="GL_MULTI_CARR_RF_MODE_L1_L5"
+       MultiCarrLnaMask="L1_EXT_ON|L5_EXT_ON"
+       RfType="GL_RF_4776_BRCM"
+       ExtL5Bias="13.0"
+
+       WarmStandbyTimeout1Seconds="10"
+       WarmStandbyTimeout2Seconds="15"
+
+       EnableGnssPropagateInStandby="true"
+
+       RfPathLossDb_Ap="2.9"
+       RfPathLossDb_Cp="2.9"
+       RfPathLossDb_Ap_L5="3.7"
+       RfPathLossDb_Cp_L5="3.7"
+       OnChipGpsCarrierType="3,2,3,3,2,3,2,3,3,3,1,2,1,3,2,1,2,3,1,1,1,1,3,3,3,3,3,1,2,3,2,3"
+
+       EnableOnChipStopNotification="0"
+       PowerMode="3"
+       MinGpsWeekNumber="2216"
+       OnChipAccMask="50"
+  />
+
+  <gll_features
+       EnableNicAutoSwitch="true"
+       EnableNavic="true"
+  />
+
+</glgps>
+
diff --git a/location/lhd.conf.f10 b/location/lhd.conf.f10
new file mode 100644
index 0000000..c000d58
--- /dev/null
+++ b/location/lhd.conf.f10
@@ -0,0 +1,34 @@
+LheName=bbd
+
+LheRsmResetTimeoutMS=10000
+GpioNStdbyPath=/sys/devices/platform/10940000.spi/spi_master/spi5/spi5.0/nstandby
+
+LhePatch=/vendor/firmware/SensorHub.patch
+Lhe477xDebugFlags=RPC:FACILITY=65535-dKP+CUST+LHE:STDOUT_PUTS:STDOUT_LOG
+LheConsole=/data/vendor/gps/LheConsole
+
+LogEnabled=true
+Log=JAVA
+LogDirectory=/sdcard/gps/broadcom/storage
+
+LheBbdPacket=/dev/ttyBCM
+
+LheBbdControl=/dev/bbd_control
+
+# LheBbdSensor=/dev/bbd_sensor
+
+LheFailSafe=/data/vendor/gps/logs/esw-crash-dump.txt
+LogLevel=*:I
+
+NvStorageDir=/data/vendor/gps/
+
+# Enable BBD debugging at these stages:
+# LheDriverDebugFlags=PATCH_BBD:LHE_BBD:FSC_BBD
+
+LheAutoBaudDelayMS=10
+TrafficLogEnabled=false
+SecondaryConfigPath=/data/vendor/gps/overlay/lhd_overlay.conf
+
+SkipSensorWakeLock=true
+LoggerWakeLockEnable=false
+PpsEnable=true
diff --git a/location/lhd_user.conf.f10 b/location/lhd_user.conf.f10
new file mode 100644
index 0000000..682d03a
--- /dev/null
+++ b/location/lhd_user.conf.f10
@@ -0,0 +1,32 @@
+LheName=bbd
+
+LheRsmResetTimeoutMS=10000
+GpioNStdbyPath=/sys/devices/platform/10940000.spi/spi_master/spi5/spi5.0/nstandby
+
+LhePatch=/vendor/firmware/SensorHub.patch
+Lhe477xDebugFlags=RPC:FACILITY=65535-dKP+CUST+LHE:STDOUT_PUTS:STDOUT_LOG
+# LheConsole=/data/vendor/gps/LheConsole
+
+LogEnabled=false
+Log=JAVA
+LogDirectory=/sdcard/gps/broadcom/storage
+
+LheBbdPacket=/dev/ttyBCM
+
+LheBbdControl=/dev/bbd_control
+
+# LheBbdSensor=/dev/bbd_sensor
+
+# LheFailSafe=/data/vendor/gps/esw-crash-dump.txt
+
+NvStorageDir=/data/vendor/gps/
+
+# Enable BBD debugging at these stages:
+# LheDriverDebugFlags=PATCH_BBD:LHE_BBD:FSC_BBD
+
+LheAutoBaudDelayMS=10
+TrafficLogEnabled=false
+
+SkipSensorWakeLock=true
+LoggerWakeLockEnable=false
+PpsEnable=true
diff --git a/location/scd.conf.f10 b/location/scd.conf.f10
new file mode 100644
index 0000000..43f9cd2
--- /dev/null
+++ b/location/scd.conf.f10
@@ -0,0 +1,6 @@
+LogEnabled=true
+Log=JAVA
+LogDirectory=/sdcard/gps/broadcom/storage
+NvStorageDir=/data/vendor/gps/
+TcpConnectionTimeout=20
+SecondaryConfigPath=/data/vendor/gps/overlay/scd_overlay.conf
diff --git a/location/scd_user.conf.f10 b/location/scd_user.conf.f10
new file mode 100644
index 0000000..e75f209
--- /dev/null
+++ b/location/scd_user.conf.f10
@@ -0,0 +1,5 @@
+LogEnabled=false
+Log=JAVA
+LogDirectory=/sdcard/gps/broadcom/storage
+NvStorageDir=/data/vendor/gps/
+TcpConnectionTimeout=20
diff --git a/manifest.xml b/manifest.xml
index 73b4e42..6068981 100644
--- a/manifest.xml
+++ b/manifest.xml
@@ -114,15 +114,6 @@
        <fqname>@1.3::IDevice/google-edgetpu</fqname>
     </hal>
     <hal format="hidl">
-       <name>android.hardware.nfc</name>
-       <transport>hwbinder</transport>
-       <version>1.2</version>
-       <interface>
-           <name>INfc</name>
-           <instance>default</instance>
-       </interface>
-    </hal>
-    <hal format="hidl">
         <name>android.hardware.health</name>
         <transport>hwbinder</transport>
         <version>2.1</version>
@@ -131,19 +122,18 @@
             <instance>default</instance>
         </interface>
     </hal>
-    <hal format="hidl">
-      <name>vendor.google.google_battery</name>
-      <transport>hwbinder</transport>
-      <version>1.2</version>
-      <interface>
-        <name>IGoogleBattery</name>
-        <instance>default</instance>
-      </interface>
+    <hal format="aidl">
+        <name>vendor.google.google_battery</name>
+        <version>2</version>
+        <interface>
+            <name>IGoogleBattery</name>
+            <instance>default</instance>
+        </interface>
     </hal>
     <hal format="hidl">
        <name>vendor.google.whitechapel.audio.audioext</name>
        <transport>hwbinder</transport>
-       <version>3.0</version>
+       <version>4.0</version>
        <interface>
            <name>IAudioExt</name>
            <instance>default</instance>
diff --git a/media_profiles_felix.xml b/media_profiles_felix.xml
index ee7a033..baf8de1 100644
--- a/media_profiles_felix.xml
+++ b/media_profiles_felix.xml
@@ -256,9 +256,9 @@
 
         <EncoderProfile quality="highspeedlow" fileFormat="mp4" duration="60">
             <Video codec="h264"
-                   bitRate="72000000"
-                   width="1920"
-                   height="1080"
+                   bitRate="42000000"
+                   width="1280"
+                   height="720"
                    frameRate="240" />
 
             <!-- audio setting is ignored -->
@@ -296,6 +296,20 @@
                    channels="1" />
         </EncoderProfile>
 
+        <EncoderProfile quality="highspeed720p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="42000000"
+                   width="1280"
+                   height="720"
+                   frameRate="240" />
+
+            <!-- audio setting is ignored -->
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
         <ImageEncoding quality="90" />
         <ImageEncoding quality="80" />
         <ImageEncoding quality="70" />
@@ -1016,190 +1030,6 @@
 
         <EncoderProfile quality="2160p" fileFormat="mp4" duration="60">
             <Video codec="h264"
-                   bitRate="48000000"
-                   width="3840"
-                   height="2160"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="1080p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="22000000"
-                   width="1920"
-                   height="1080"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="720p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="12000000"
-                   width="1280"
-                   height="720"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="480p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="6000000"
-                   width="720"
-                   height="480"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="cif" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="1200000"
-                   width="352"
-                   height="288"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="qvga" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="512000"
-                   width="320"
-                   height="240"
-                   frameRate="30" />
-
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="qcif" fileFormat="3gp" duration="60">
-            <Video codec="h264"
-                   bitRate="128000"
-                   width="176"
-                   height="144"
-                   frameRate="30" />
-
-            <Audio codec="amrnb"
-                   bitRate="12200"
-                   sampleRate="8000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapse2160p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="48000000"
-                   width="3840"
-                   height="2160"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapse1080p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="22000000"
-                   width="1920"
-                   height="1080"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapse720p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="12000000"
-                   width="1280"
-                   height="720"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapse480p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="6000000"
-                   width="720"
-                   height="480"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapsecif" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="1200000"
-                   width="352"
-                   height="288"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="aac"
-                   bitRate="96000"
-                   sampleRate="48000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <EncoderProfile quality="timelapseqcif" fileFormat="mp4" duration="60">
-            <Video codec="h264"
-                   bitRate="192000"
-                   width="176"
-                   height="144"
-                   frameRate="30" />
-
-            <!-- Audio settings are not used for timealpse video recording -->
-            <Audio codec="amrnb"
-                   bitRate="12200"
-                   sampleRate="8000"
-                   channels="1" />
-        </EncoderProfile>
-
-        <ImageEncoding quality="90" />
-        <ImageEncoding quality="80" />
-        <ImageEncoding quality="70" />
-        <ImageDecoding memCap="20000000" />
-
-    </CamcorderProfiles>
-
-    <CamcorderProfiles cameraId="6">
-
-        <EncoderProfile quality="2160p" fileFormat="mp4" duration="60">
-            <Video codec="h264"
                    bitRate="72000000"
                    width="3840"
                    height="2160"
@@ -1291,9 +1121,37 @@
 
         <EncoderProfile quality="timelapse2160p" fileFormat="mp4" duration="60">
             <Video codec="h264"
-                   bitRate="48000000"
+                   bitRate="72000000"
                    width="3840"
                    height="2160"
+                   frameRate="60" />
+
+            <!-- Audio settings are not used for timealpse video recording -->
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="timelapse1080p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="33000000"
+                   width="1920"
+                   height="1080"
+                   frameRate="60" />
+
+            <!-- Audio settings are not used for timealpse video recording -->
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="timelapse720p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="12000000"
+                   width="1280"
+                   height="720"
                    frameRate="30" />
 
             <!-- Audio settings are not used for timealpse video recording -->
@@ -1303,6 +1161,135 @@
                    channels="1" />
         </EncoderProfile>
 
+        <EncoderProfile quality="timelapse480p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="6000000"
+                   width="720"
+                   height="480"
+                   frameRate="30" />
+
+            <!-- Audio settings are not used for timealpse video recording -->
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="timelapsecif" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="1200000"
+                   width="352"
+                   height="288"
+                   frameRate="30" />
+
+            <!-- Audio settings are not used for timealpse video recording -->
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="timelapseqcif" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="192000"
+                   width="176"
+                   height="144"
+                   frameRate="30" />
+
+            <!-- Audio settings are not used for timealpse video recording -->
+            <Audio codec="amrnb"
+                   bitRate="12200"
+                   sampleRate="8000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <ImageEncoding quality="90" />
+        <ImageEncoding quality="80" />
+        <ImageEncoding quality="70" />
+        <ImageDecoding memCap="20000000" />
+
+    </CamcorderProfiles>
+
+    <CamcorderProfiles cameraId="6">
+
+        <EncoderProfile quality="1080p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="22000000"
+                   width="1920"
+                   height="1080"
+                   frameRate="30" />
+
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="720p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="12000000"
+                   width="1280"
+                   height="720"
+                   frameRate="30" />
+
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="480p" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="6000000"
+                   width="720"
+                   height="480"
+                   frameRate="30" />
+
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="cif" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="1200000"
+                   width="352"
+                   height="288"
+                   frameRate="30" />
+
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="qvga" fileFormat="mp4" duration="60">
+            <Video codec="h264"
+                   bitRate="512000"
+                   width="320"
+                   height="240"
+                   frameRate="30" />
+
+            <Audio codec="aac"
+                   bitRate="96000"
+                   sampleRate="48000"
+                   channels="1" />
+        </EncoderProfile>
+
+        <EncoderProfile quality="qcif" fileFormat="3gp" duration="60">
+            <Video codec="h264"
+                   bitRate="128000"
+                   width="176"
+                   height="144"
+                   frameRate="30" />
+
+            <Audio codec="amrnb"
+                   bitRate="12200"
+                   sampleRate="8000"
+                   channels="1" />
+        </EncoderProfile>
+
         <EncoderProfile quality="timelapse1080p" fileFormat="mp4" duration="60">
             <Video codec="h264"
                    bitRate="22000000"
diff --git a/nfc/libnfc-hal-st.conf b/nfc/libnfc-hal-st.conf
index 0035a70..b7599c7 100644
--- a/nfc/libnfc-hal-st.conf
+++ b/nfc/libnfc-hal-st.conf
@@ -60,8 +60,8 @@
 NCI_HAL_MODULE="nfc_nci.st21nfc"
 
 ###############################################################################
-# White list to be set at startup.
-DEVICE_HOST_WHITE_LIST={02:C0}
+# Allow list to be set at startup.
+DEVICE_HOST_ALLOW_LIST={02:C0}
 
 ###############################################################################
 # BAIL OUT value for P2P
diff --git a/nfc/manifest_nfc.xml b/nfc/manifest_nfc.xml
deleted file mode 100644
index bf6b7cc..0000000
--- a/nfc/manifest_nfc.xml
+++ /dev/null
@@ -1,11 +0,0 @@
-<manifest version="1.0" type="device">
-  <hal format="hidl">
-    <name>android.hardware.nfc</name>
-    <transport>hwbinder</transport>
-    <version>1.2</version>
-    <interface>
-      <name>INfc</name>
-      <instance>default</instance>
-      </interface>
-  </hal>
-</manifest>
diff --git a/powerhint.json b/powerhint.json
index 99a2355..46de73c 100644
--- a/powerhint.json
+++ b/powerhint.json
@@ -1,10 +1,25 @@
 {
   "Nodes": [
     {
+      "Name": "GPUMinFreq",
+      "Path": "/sys/devices/platform/28000000.mali/hint_min_freq",
+      "Values": [
+        "848000",
+        "762000",
+        "572000",
+        "471000",
+        "302000",
+        "202000"
+      ],
+      "ResetOnInit": true
+    },
+    {
       "Name": "MemFreq",
       "Path": "/sys/devices/platform/17000010.devfreq_mif/devfreq/17000010.devfreq_mif/min_freq",
       "Values": [
         "3172000",
+        "1539000",
+        "1352000",
         "1014000",
         "421000"
       ],
@@ -40,6 +55,7 @@
       "Path": "/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq",
       "Values": [
         "9999999",
+        "1401000",
         "1197000",
         "0"
       ],
@@ -50,6 +66,8 @@
       "Path": "/sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq",
       "Values": [
         "9999999",
+        "2253000",
+        "2130000",
         "1024000",
         "1197000",
         "1491000",
@@ -67,6 +85,9 @@
       "Path": "/sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq",
       "Values": [
         "9999999",
+        "2253000",
+        "2130000",
+        "1836000",
         "1197000",
         "0"
       ],
@@ -77,6 +98,9 @@
       "Path": "/sys/devices/system/cpu/cpu6/cpufreq/scaling_max_freq",
       "Values": [
         "9999999",
+        "2704000",
+        "2507000",
+        "2252000",
         "984000",
         "1426000",
         "1826000",
@@ -94,20 +118,30 @@
       "Path": "/sys/devices/system/cpu/cpu6/cpufreq/scaling_min_freq",
       "Values": [
         "9999999",
+        "2704000",
+        "2507000",
+        "2252000",
+        "1826000",
         "1106000",
         "0"
       ],
       "ResetOnInit": true
     },
     {
-      "Name": "GPUMinFreq",
-      "Path": "/sys/devices/platform/28000000.mali/hint_min_freq",
+      "Name": "GPUDvfsPeriod",
+      "Path": "/sys/devices/platform/28000000.mali/dvfs_period",
       "Values": [
-        "762000",
-        "471000",
-        "400000",
-        "302000",
-        "151000"
+        "10",
+        "20"
+      ],
+      "ResetOnInit": true
+    },
+    {
+      "Name": "ReducePreferIdle",
+      "Path": "/proc/vendor_sched/reduce_prefer_idle",
+      "Values": [
+        "0",
+        "1"
       ],
       "ResetOnInit": true
     },
@@ -116,7 +150,17 @@
       "Path": "/proc/vendor_sched/util_threshold",
       "Values": [
         "1280",
-        "1100"
+        "1100 1078 1024"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": true
+    },
+    {
+      "Name": "CPUDVFSHeadroom",
+      "Path": "/proc/vendor_sched/dvfs_headroom",
+      "Values": [
+        "1280",
+        "1100 1078 1024"
       ],
       "DefaultIndex": 0,
       "ResetOnInit": true
@@ -125,8 +169,18 @@
       "Name": "MIFTargetLoad",
       "Path": "/sys/class/devfreq/17000010.devfreq_mif/interactive/target_load",
       "Values": [
-        "20 5 80",
-        "20 10 80"
+        "20 10 80",
+        "80 10 80",
+        "60 10 40"
+      ],
+      "ResetOnInit": true
+    },
+    {
+      "Name": "CAMUClampBoost",
+      "Path": "/proc/vendor_sched/cam_uclamp_min",
+      "Values": [
+        "764",
+        "0"
       ],
       "ResetOnInit": true
     },
@@ -134,22 +188,17 @@
       "Name": "TAUClampBoost",
       "Path": "/proc/vendor_sched/ta_uclamp_min",
       "Values": [
-        "553",
-        "158",
-        "108",
-        "1",
-        "157",
-        "42"
+        "764",
+        "1"
       ],
       "ResetOnInit": true
     },
     {
-      "Name": "SFUClampBoost",
-      "Path": "/proc/vendor_sched/sf_uclamp_min",
+      "Name": "FGUClampBoost",
+      "Path": "/proc/vendor_sched/fg_uclamp_min",
       "Values": [
-        "125",
-        "65",
-        "30"
+        "159",
+        "0"
       ],
       "ResetOnInit": true
     },
@@ -157,13 +206,22 @@
       "Name": "MLUclampBoost",
       "Path": "/proc/vendor_sched/nnapi_uclamp_min",
       "Values": [
-          "154",
-          "512"
+          "225",
+          "813"
       ],
       "DefaultIndex": 0,
       "ResetOnInit": true
     },
     {
+      "Name": "PMQoSCpuDmaLatency",
+      "Path": "/dev/cpu_dma_latency",
+      "Values": [
+        "44",
+        "1000"
+      ],
+      "HoldFd": true
+    },
+    {
       "Name": "CDPreferIdle",
       "Path": "/proc/vendor_sched/cam_prefer_idle",
       "Values": [
@@ -176,26 +234,18 @@
       "Name": "CDCpuset",
       "Path": "/dev/cpuset/camera-daemon/cpus",
       "Values": [
+        "0-3",
         "4-7",
         "0-7"
       ],
       "ResetOnInit": true
     },
     {
-      "Name": "RestrictedCpuset",
-      "Path": "/dev/cpuset/restricted/cpus",
-      "Values": [
-        "0-3",
-        "0-7"
-      ],
-      "ResetOnInit": false
-    },
-    {
       "Name": "CDHighCpusetCpus",
       "Path": "/dev/cpuset/camera-daemon-high-group/cpus",
       "Values": [
-        "6-7",
-        "0-7"
+        "0-3",
+        "6-7"
       ],
       "ResetOnInit": true
     },
@@ -203,8 +253,8 @@
       "Name": "CDMidCpusetCpus",
       "Path": "/dev/cpuset/camera-daemon-mid-group/cpus",
       "Values": [
-        "4-5",
-        "0-7"
+        "0-3",
+        "4-5"
       ],
       "ResetOnInit": true
     },
@@ -212,8 +262,8 @@
       "Name": "CDMidHighCpusetCpus",
       "Path": "/dev/cpuset/camera-daemon-mid-high-group/cpus",
       "Values": [
-        "4-7",
-        "0-7"
+        "0-3",
+        "4-7"
       ],
       "ResetOnInit": true
     },
@@ -239,9 +289,10 @@
       "Name": "FGPreferIdle",
       "Path": "/proc/vendor_sched/fg_prefer_idle",
       "Values": [
-        "0",
-        "1"
+        "1",
+        "0"
       ],
+      "DefaultIndex": 0,
       "ResetOnInit": true
     },
     {
@@ -254,6 +305,15 @@
       "ResetOnInit": true
     },
     {
+      "Name": "NPITaskPacking",
+      "Path": "/proc/vendor_sched/npi_packing",
+      "Values": [
+        "0",
+        "1"
+      ],
+      "ResetOnInit": true
+    },
+    {
       "Name": "DisplayWakeup",
       "Path": "/sys/devices/platform/1c240000.drmdecon/early_wakeup",
       "Values": [
@@ -281,19 +341,41 @@
       "Type": "Property"
     },
     {
+      "Name": "PowerHALCameraRunning",
+      "Path": "vendor.powerhal.camerarunning",
+      "Values": [
+        "1",
+        "0"
+      ],
+      "Type": "Property",
+      "ResetOnInit": true
+    },
+    {
       "Name": "INTCAMFreq",
       "Path": "/sys/devices/platform/17000030.devfreq_intcam/devfreq/17000030.devfreq_intcam/min_freq",
       "Values": [
         "664000",
+        "233000",
         "67000"
       ],
       "ResetOnInit": true
     },
     {
+      "Name": "TNRMaxFreq",
+      "Path": "/sys/devices/platform/17000060.devfreq_tnr/devfreq/17000060.devfreq_tnr/max_freq",
+      "Values": [
+        "664000",
+        "67000"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": true
+    },
+    {
       "Name": "TNRFreq",
       "Path": "/sys/devices/platform/17000060.devfreq_tnr/devfreq/17000060.devfreq_tnr/min_freq",
       "Values": [
         "664000",
+        "233000",
         "67000"
       ],
       "ResetOnInit": true
@@ -302,7 +384,7 @@
       "Name": "BigControlTempSet",
       "Path": "/dev/thermal/tz-by-name/BIG/trip_point_2_temp",
       "Values": [
-        "90000",
+        "100000",
         "80000"
       ],
       "DefaultIndex": 0,
@@ -312,7 +394,7 @@
       "Name": "MidControlTempSet",
       "Path": "/dev/thermal/tz-by-name/MID/trip_point_2_temp",
       "Values": [
-        "90000",
+        "100000",
         "80000"
       ],
       "DefaultIndex": 0,
@@ -322,7 +404,7 @@
       "Name": "LittleControlTempSet",
       "Path": "/dev/thermal/tz-by-name/LITTLE/trip_point_2_temp",
       "Values": [
-        "95000",
+        "100000",
         "80000"
       ],
       "DefaultIndex": 0,
@@ -332,7 +414,27 @@
       "Name": "G3dControlTempSet",
       "Path": "/dev/thermal/tz-by-name/G3D/trip_point_2_temp",
       "Values": [
-        "90000",
+        "100000",
+        "80000"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": false
+    },
+    {
+      "Name": "TpuControlTempSet",
+      "Path": "/dev/thermal/tz-by-name/TPU/trip_point_2_temp",
+      "Values": [
+        "100000",
+        "80000"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": false
+    },
+    {
+      "Name": "AurControlTempSet",
+      "Path": "/dev/thermal/tz-by-name/AUR/trip_point_2_temp",
+      "Values": [
+        "100000",
         "80000"
       ],
       "DefaultIndex": 0,
@@ -342,7 +444,7 @@
       "Name": "BigSwitchOnTempSet",
       "Path": "/dev/thermal/tz-by-name/BIG/trip_point_1_temp",
       "Values": [
-        "70000",
+        "80000",
         "60000"
       ],
       "DefaultIndex": 0,
@@ -352,7 +454,7 @@
       "Name": "MidSwitchOnTempSet",
       "Path": "/dev/thermal/tz-by-name/MID/trip_point_1_temp",
       "Values": [
-        "70000",
+        "80000",
         "60000"
       ],
       "DefaultIndex": 0,
@@ -362,7 +464,7 @@
       "Name": "LittleSwitchOnTempSet",
       "Path": "/dev/thermal/tz-by-name/LITTLE/trip_point_1_temp",
       "Values": [
-        "70000",
+        "80000",
         "60000"
       ],
       "DefaultIndex": 0,
@@ -372,36 +474,163 @@
       "Name": "G3dSwitchOnTempSet",
       "Path": "/dev/thermal/tz-by-name/G3D/trip_point_1_temp",
       "Values": [
-        "70000",
+        "80000",
         "60000"
       ],
       "DefaultIndex": 0,
       "ResetOnInit": false
+    },
+    {
+      "Name": "TpuSwitchOnTempSet",
+      "Path": "/dev/thermal/tz-by-name/TPU/trip_point_1_temp",
+      "Values": [
+        "80000",
+        "60000"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": false
+    },
+    {
+      "Name": "AurSwitchOnTempSet",
+      "Path": "/dev/thermal/tz-by-name/AUR/trip_point_1_temp",
+      "Values": [
+        "80000",
+        "60000"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": false
+    },
+    {
+      "Name": "CPU_LITTLE_TSKIN_BYPASS",
+      "Path": "/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote_bypass",
+      "Values": [
+        "0",
+        "1"
+      ],
+      "DefaultIndex": 0
+    },
+    {
+      "Name": "CPU_MID_TSKIN_BYPASS",
+      "Path": "/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote_bypass",
+      "Values": [
+        "0",
+        "1"
+      ],
+      "DefaultIndex": 0
+    },
+    {
+      "Name": "CPU_BIG_TSKIN_BYPASS",
+      "Path": "/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote_bypass",
+      "Values": [
+        "0",
+        "1"
+      ],
+      "DefaultIndex": 0
+    },
+    {
+      "Name": "TRUSTY_VIRTIO_HIGH",
+      "Path": "/sys/module/trusty_virtio/parameters/use_high_wq",
+      "Values": [
+        "1",
+        "0"
+      ]
+    },
+    {
+      "Name": "TRUSTY_HIGH",
+      "Path": "/sys/module/trusty_core/parameters/use_high_wq",
+      "Values": [
+        "1",
+        "0"
+      ]
+    },
+    {
+      "Name": "PMU_POLL",
+      "Path": "/proc/vendor_sched/pmu_poll_enable",
+      "Values": [
+        "0",
+        "1"
+      ],
+      "DefaultIndex": 0
+    },
+    {
+      "Name": "Dex2oatThreads",
+      "Path": "vendor.powerhal.dalvik.vm.dex2oat-threads",
+      "Values": [
+        "1",
+        "2",
+        "4",
+        "6",
+        "8"
+      ],
+      "Type": "Property"
+    },
+    {
+      "Name": "Dex2oatCPUSet",
+      "Path": "vendor.powerhal.dalvik.vm.dex2oat-cpu-set",
+      "Values": [
+        "0,1,2,3",
+        "0,1,2,3,4,5,6,7"
+      ],
+      "Type": "Property"
+    },
+    {
+      "Name": "Dex2oatGroup",
+      "Path": "/proc/vendor_sched/dex2oat_ug",
+      "Values": [
+        "1",
+        "0"
+      ],
+      "DefaultIndex": 0,
+      "ResetOnInit": true
     }
   ],
   "Actions": [
     {
-      "PowerHint": "INTERACTION",
-      "Node": "SFUClampBoost",
-      "Duration": 5000,
-      "Value": "65"
+      "PowerHint": "CDCPUSET_RESTRICTED",
+      "Node": "CDCpuset",
+      "Duration": 1000,
+      "Value": "0-3"
     },
     {
-      "PowerHint": "LAUNCH_120FPS",
-      "Node": "SFUClampBoost",
+      "PowerHint": "CDHIGHCPUSETCPUS_RESTRICTED",
+      "Node": "CDHighCpusetCpus",
       "Duration": 1000,
-      "Value": "125"
+      "Value": "0-3"
+    },
+    {
+      "PowerHint": "CDMIDCPUSETCPUS_RESTRICTED",
+      "Node": "CDMidCpusetCpus",
+      "Duration": 1000,
+      "Value": "0-3"
+    },
+    {
+      "PowerHint": "CDMIDHIGHCPUSETCPUS_RESTRICTED",
+      "Node": "CDMidHighCpusetCpus",
+      "Duration": 1000,
+      "Value": "0-3"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Node": "ReducePreferIdle",
+      "Duration": 5000,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "LAUNCH_GPU",
+      "Node": "GPUDvfsPeriod",
+      "Duration": 1000,
+      "Value": "10"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Node": "FGPreferIdle",
+      "Duration": 5000,
+      "Value": "1"
     },
     {
       "PowerHint": "LAUNCH",
       "Type": "DoHint",
-      "Value": "LAUNCH_120FPS"
-    },
-    {
-      "PowerHint": "LAUNCH",
-      "Node": "SFUClampBoost",
-      "Duration": 5000,
-      "Value": "65"
+      "Value": "LAUNCH_GPU"
     },
     {
       "PowerHint": "LAUNCH",
@@ -425,7 +654,13 @@
       "PowerHint": "LAUNCH",
       "Node": "TAUClampBoost",
       "Duration": 5000,
-      "Value": "553"
+      "Value": "764"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Node": "FGUClampBoost",
+      "Duration": 5000,
+      "Value": "159"
     },
     {
       "PowerHint": "LAUNCH",
@@ -434,6 +669,71 @@
       "Value": "3172000"
     },
     {
+      "PowerHint": "LAUNCH",
+      "Node": "NPITaskPacking",
+      "Duration": 5000,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Type": "DoHint",
+      "EnableProperty": "vendor.powerhal.camerarunning",
+      "Value": "CDCPUSET_RESTRICTED"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Type": "DoHint",
+      "EnableProperty": "vendor.powerhal.camerarunning",
+      "Value": "CDHIGHCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Type": "DoHint",
+      "EnableProperty": "vendor.powerhal.camerarunning",
+      "Value": "CDMIDCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Type": "DoHint",
+      "EnableProperty": "vendor.powerhal.camerarunning",
+      "Value": "CDMIDHIGHCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "LAUNCH",
+      "Type": "DoHint",
+      "Value": "LAUNCH_EXTEND"
+    },
+    {
+      "PowerHint": "LAUNCH_EXTEND",
+      "Node": "CPUBigClusterMaxFreq",
+      "Duration": 2000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "LAUNCH_EXTEND",
+      "Node": "CPUMidClusterMaxFreq",
+      "Duration": 2000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "LAUNCH_EXTEND",
+      "Node": "CPULittleClusterMaxFreq",
+      "Duration": 2000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "CPU_LOAD_RESET",
+      "Node": "GPUMinFreq",
+      "Duration": 50,
+      "Value": "302000"
+    },
+    {
+      "PowerHint": "CPU_LOAD_RESET",
+      "Node": "MemFreq",
+      "Duration": 33,
+      "Value": "1014000"
+    },
+    {
       "PowerHint": "CAMERA_LAUNCH",
       "Node": "MemFreq",
       "Duration": 1000,
@@ -449,7 +749,7 @@
       "PowerHint": "CAMERA_LAUNCH",
       "Node": "CPUBigClusterMinFreq",
       "Duration": 1000,
-      "Value": "9999999"
+      "Value": "1826000"
     },
     {
       "PowerHint": "CAMERA_LAUNCH",
@@ -461,7 +761,7 @@
       "PowerHint": "CAMERA_LAUNCH",
       "Node": "CPUMidClusterMinFreq",
       "Duration": 1000,
-      "Value": "9999999"
+      "Value": "1836000"
     },
     {
       "PowerHint": "CAMERA_LAUNCH",
@@ -473,7 +773,19 @@
       "PowerHint": "CAMERA_LAUNCH",
       "Node": "CPULittleClusterMinFreq",
       "Duration": 1000,
-      "Value": "9999999"
+      "Value": "1401000"
+    },
+    {
+      "PowerHint": "CAMERA_LAUNCH",
+      "Node": "CAMUClampBoost",
+      "Duration": 1000,
+      "Value": "764"
+    },
+    {
+      "PowerHint": "CAMERA_LAUNCH",
+      "Node": "NPITaskPacking",
+      "Duration": 1000,
+      "Value": "0"
     },
     {
       "PowerHint": "CAMERA_LAUNCH",
@@ -500,6 +812,12 @@
       "Value": "9999999"
     },
     {
+      "PowerHint": "CAMERA_LAUNCH_EXTENDED",
+      "Node": "NPITaskPacking",
+      "Duration": 2000,
+      "Value": "0"
+    },
+    {
       "PowerHint": "CAMERA_THERMAL_CPU_THROTTLE",
       "Node": "CPUBigClusterMaxFreq",
       "Duration": 1000,
@@ -521,13 +839,13 @@
       "PowerHint": "CAMERA_CAPTURE_CPU_THROTTLE",
       "Node": "CPUBigClusterMaxFreq",
       "Duration": 1000,
-      "Value": "1426000"
+      "Value": "1826000"
     },
     {
       "PowerHint": "CAMERA_CAPTURE_CPU_THROTTLE",
       "Node": "CPUMidClusterMaxFreq",
       "Duration": 1000,
-      "Value": "1197000"
+      "Value": "1491000"
     },
     {
       "PowerHint": "CAMERA_CAPTURE_CPU_THROTTLE",
@@ -551,7 +869,7 @@
       "PowerHint": "CAMERA_SHOT",
       "Node": "CPUBigClusterMinFreq",
       "Duration": 300,
-      "Value": "9999999"
+      "Value": "1826000"
     },
     {
       "PowerHint": "CAMERA_SHOT",
@@ -563,7 +881,7 @@
       "PowerHint": "CAMERA_SHOT",
       "Node": "CPUMidClusterMinFreq",
       "Duration": 300,
-      "Value": "9999999"
+      "Value": "1836000"
     },
     {
       "PowerHint": "CAMERA_BACKEND_BOOST",
@@ -590,6 +908,108 @@
       "Value": "664000"
     },
     {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK1",
+      "Node": "TAPreferHighCap",
+      "Duration": 3000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK1",
+      "Node": "CPUBigClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "2704000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK1",
+      "Node": "CPUBigClusterMinFreq",
+      "Duration": 3000,
+      "Value": "2704000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK2",
+      "Node": "TAPreferHighCap",
+      "Duration": 3000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK2",
+      "Node": "CPUBigClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "2507000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK2",
+      "Node": "CPUBigClusterMinFreq",
+      "Duration": 3000,
+      "Value": "2507000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK3",
+      "Node": "TAPreferHighCap",
+      "Duration": 3000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK3",
+      "Node": "CPUBigClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "2252000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_BIGCPU_RANK3",
+      "Node": "CPUBigClusterMinFreq",
+      "Duration": 3000,
+      "Value": "2252000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK1",
+      "Node": "CPUMidClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK1",
+      "Node": "CPUMidClusterMinFreq",
+      "Duration": 3000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK2",
+      "Node": "CPUMidClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "2253000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK2",
+      "Node": "CPUMidClusterMinFreq",
+      "Duration": 3000,
+      "Value": "2253000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK3",
+      "Node": "CPUMidClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "2130000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_MIDCPU_RANK3",
+      "Node": "CPUMidClusterMinFreq",
+      "Duration": 3000,
+      "Value": "2130000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_LITTLECPU_RANK1",
+      "Node": "CPULittleClusterMaxFreq",
+      "Duration": 3000,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_LITTLECPU_RANK1",
+      "Node": "CPULittleClusterMinFreq",
+      "Duration": 3000,
+      "Value": "9999999"
+    },
+    {
       "PowerHint": "GCA_CAMERA_SHOT_BIGCPU",
       "Node": "TAPreferHighCap",
       "Duration": 3000,
@@ -653,7 +1073,7 @@
       "PowerHint": "GCA_CAMERA_SHOT_ALLCPU",
       "Node": "CPUBigClusterMinFreq",
       "Duration": 3000,
-      "Value": "9999999"
+      "Value": "1826000"
     },
     {
       "PowerHint": "GCA_CAMERA_SHOT_ALLCPU",
@@ -665,7 +1085,7 @@
       "PowerHint": "GCA_CAMERA_SHOT_ALLCPU",
       "Node": "CPUMidClusterMinFreq",
       "Duration": 3000,
-      "Value": "9999999"
+      "Value": "1836000"
     },
     {
       "PowerHint": "GCA_CAMERA_SHOT_ALLCPU",
@@ -677,7 +1097,19 @@
       "PowerHint": "GCA_CAMERA_SHOT_ALLCPU",
       "Node": "CPULittleClusterMinFreq",
       "Duration": 3000,
-      "Value": "9999999"
+      "Value": "1401000"
+    },
+    {
+      "PowerHint": "GCA_CAMERA_SHOT_GPU_EXTREME",
+      "Node": "GPUMinFreq",
+      "Duration": 3000,
+      "Value": "848000"
+    },
+    {
+      "PowerHint": "CAMERA_STREAMING_EXTREME",
+      "Node": "PowerHALCameraRunning",
+      "Duration": 0,
+      "Value": "1"
     },
     {
       "PowerHint": "CAMERA_STREAMING_EXTREME",
@@ -705,12 +1137,6 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_EXTREME",
-      "Node": "GPUMinFreq",
-      "Duration": 0,
-      "Value": "302000"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_EXTREME",
       "Node": "MemFreq",
       "Duration": 0,
       "Value": "1014000"
@@ -719,7 +1145,7 @@
       "PowerHint": "CAMERA_STREAMING_EXTREME",
       "Node": "MIFTargetLoad",
       "Duration": 0,
-      "Value": "20 10 80"
+      "Value": "80 10 80"
     },
     {
       "PowerHint": "CAMERA_STREAMING_EXTREME",
@@ -735,27 +1161,27 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_EXTREME",
-      "Node": "CDHighCpusetCpus",
+      "Node": "NPITaskPacking",
       "Duration": 0,
-      "Value": "6-7"
+      "Value": "0"
     },
     {
-      "PowerHint": "CAMERA_STREAMING_EXTREME",
-      "Node": "CDMidCpusetCpus",
+      "PowerHint": "CAMERA_STREAMING_HIGH",
+      "Node": "PowerHALCameraRunning",
       "Duration": 0,
-      "Value": "4-5"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_EXTREME",
-      "Node": "CDMidHighCpusetCpus",
-      "Duration": 0,
-      "Value": "4-7"
+      "Value": "1"
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
       "Node": "CPUUtilThreshold",
       "Duration": 0,
-      "Value": "1100"
+      "Value": "1100 1078 1024"
+    },
+    {
+      "PowerHint": "CAMERA_STREAMING_HIGH",
+      "Node": "CPUDVFSHeadroom",
+      "Duration": 0,
+      "Value": "1100 1078 1024"
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
@@ -783,21 +1209,15 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
-      "Node": "GPUMinFreq",
-      "Duration": 0,
-      "Value": "302000"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_HIGH",
       "Node": "MemFreq",
       "Duration": 0,
-      "Value": "1014000"
+      "Value": "1539000"
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
       "Node": "MIFTargetLoad",
       "Duration": 0,
-      "Value": "20 10 80"
+      "Value": "80 10 80"
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
@@ -813,21 +1233,15 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_HIGH",
-      "Node": "CDHighCpusetCpus",
+      "Node": "NPITaskPacking",
       "Duration": 0,
-      "Value": "6-7"
+      "Value": "0"
     },
     {
-      "PowerHint": "CAMERA_STREAMING_HIGH",
-      "Node": "CDMidCpusetCpus",
+      "PowerHint": "CAMERA_STREAMING_STANDARD",
+      "Node": "PowerHALCameraRunning",
       "Duration": 0,
-      "Value": "4-5"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_HIGH",
-      "Node": "CDMidHighCpusetCpus",
-      "Duration": 0,
-      "Value": "4-7"
+      "Value": "1"
     },
     {
       "PowerHint": "CAMERA_STREAMING_STANDARD",
@@ -843,6 +1257,12 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_STANDARD",
+      "Node": "CDPreferIdle",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "CAMERA_STREAMING_STANDARD",
       "Node": "CPUBigClusterMaxFreq",
       "Duration": 0,
       "Value": "1826000"
@@ -861,15 +1281,9 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_STANDARD",
-      "Node": "GPUMinFreq",
-      "Duration": 0,
-      "Value": "302000"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_STANDARD",
       "Node": "MemFreq",
       "Duration": 0,
-      "Value": "1014000"
+      "Value": "1352000"
     },
     {
       "PowerHint": "CAMERA_STREAMING_STANDARD",
@@ -879,21 +1293,15 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_STANDARD",
-      "Node": "CDHighCpusetCpus",
+      "Node": "NPITaskPacking",
       "Duration": 0,
-      "Value": "6-7"
+      "Value": "0"
     },
     {
-      "PowerHint": "CAMERA_STREAMING_STANDARD",
-      "Node": "CDMidCpusetCpus",
+      "PowerHint": "CAMERA_STREAMING_LOW",
+      "Node": "PowerHALCameraRunning",
       "Duration": 0,
-      "Value": "4-5"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_STANDARD",
-      "Node": "CDMidHighCpusetCpus",
-      "Duration": 0,
-      "Value": "4-7"
+      "Value": "1"
     },
     {
       "PowerHint": "CAMERA_STREAMING_LOW",
@@ -933,12 +1341,6 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_LOW",
-      "Node": "GPUMinFreq",
-      "Duration": 0,
-      "Value": "302000"
-    },
-    {
-      "PowerHint": "CAMERA_STREAMING_LOW",
       "Node": "MemFreq",
       "Duration": 0,
       "Value": "1014000"
@@ -951,21 +1353,77 @@
     },
     {
       "PowerHint": "CAMERA_STREAMING_LOW",
-      "Node": "CDHighCpusetCpus",
+      "Node": "NPITaskPacking",
       "Duration": 0,
-      "Value": "6-7"
+      "Value": "0"
     },
     {
-      "PowerHint": "CAMERA_STREAMING_LOW",
-      "Node": "CDMidCpusetCpus",
+      "PowerHint": "CAMERA_MULTI_CAM_STREAMING",
+      "Node": "CPUBigClusterMaxFreq",
       "Duration": 0,
-      "Value": "4-5"
+      "Value": "9999999"
     },
     {
-      "PowerHint": "CAMERA_STREAMING_LOW",
-      "Node": "CDMidHighCpusetCpus",
+      "PowerHint": "CAMERA_MULTI_CAM_STREAMING",
+      "Node": "CPUMidClusterMaxFreq",
       "Duration": 0,
-      "Value": "4-7"
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "CAMERA_MULTI_CAM_STREAMING",
+      "Node": "CPULittleClusterMaxFreq",
+      "Duration": 0,
+      "Value": "9999999"
+    },
+    {
+      "PowerHint": "CAMERA_VIDEO_RECORDING",
+      "Type": "MaskHint",
+      "Value": "CDCPUSET_RESTRICTED"
+    },
+    {
+      "PowerHint": "CAMERA_VIDEO_RECORDING",
+      "Type": "MaskHint",
+      "Value": "CDHIGHCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "CAMERA_VIDEO_RECORDING",
+      "Type": "MaskHint",
+      "Value": "CDMIDCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "CAMERA_VIDEO_RECORDING",
+      "Type": "MaskHint",
+      "Value": "CDMIDHIGHCPUSETCPUS_RESTRICTED"
+    },
+    {
+      "PowerHint": "CAMERA_GPU_HIGH",
+      "Node": "GPUMinFreq",
+      "Duration": 0,
+      "Value": "572000"
+    },
+    {
+      "PowerHint": "CAMERA_GPU_STANDARD",
+      "Node": "GPUMinFreq",
+      "Duration": 0,
+      "Value": "302000"
+    },
+    {
+      "PowerHint": "CAMERA_ADJUST_BACKEND_MIN_FREQ",
+      "Node": "INTCAMFreq",
+      "Duration": 0,
+      "Value": "233000"
+    },
+    {
+      "PowerHint": "CAMERA_ADJUST_BACKEND_MIN_FREQ",
+      "Node": "TNRFreq",
+      "Duration": 0,
+      "Value": "233000"
+    },
+    {
+      "PowerHint": "CAMERA_TNR_LOW",
+      "Node": "TNRMaxFreq",
+      "Duration": 0,
+      "Value": "67000"
     },
     {
       "PowerHint": "FIXED_PERFORMANCE",
@@ -1094,79 +1552,94 @@
       "Value": "2401000"
     },
     {
+      "PowerHint": "LOW_POWER",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "BigControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "MidControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "LittleControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "G3dControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "BigSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "MidSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "LittleSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "G3dSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "LOW_POWER",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
       "PowerHint": "REFRESH_120FPS",
       "Node": "TAUClampBoost",
       "Duration": 0,
-      "Value": "157"
+      "Value": "1"
     },
     {
       "PowerHint": "REFRESH_60FPS",
       "Node": "TAUClampBoost",
       "Duration": 0,
-      "Value": "42"
-    },
-    {
-      "PowerHint": "REFRESH_60FPS",
-      "Type": "MaskHint",
-      "Value": "LAUNCH_120FPS"
-    },
-    {
-      "PowerHint": "ADPF_DISABLE_TA_BOOST",
-      "Node": "TAUClampBoost",
-      "Duration": 0,
       "Value": "1"
     },
     {
       "PowerHint": "ADPF_DISABLE_TA_BOOST",
-      "Type": "MaskHint",
-      "Value": "BOOST_DISPLAY"
-    },
-    {
-      "PowerHint": "ADPF_DISABLE_TA_BOOST",
-      "Type": "EndHint",
-      "Value": "BOOST_120HZ"
-    },
-    {
-      "PowerHint": "ADPF_DISABLE_TA_BOOST",
-      "Type": "EndHint",
-      "Value": "BOOST_60HZ"
-    },
-    {
-      "PowerHint": "BOOST_DISPLAY",
-      "Type": "DoHint",
-      "Value": "BOOST_120HZ"
-    },
-    {
-      "PowerHint": "BOOST_DISPLAY",
-      "Type": "DoHint",
-      "Value": "BOOST_60HZ"
-    },
-    {
-      "PowerHint": "INTERACTION",
-      "Type": "DoHint",
-      "Value": "BOOST_DISPLAY"
-    },
-    {
-      "PowerHint": "BOOST_120HZ",
       "Node": "TAUClampBoost",
-      "Duration": 200,
-      "Value": "158"
-    },
-    {
-      "PowerHint": "BOOST_60HZ",
-      "Node": "TAUClampBoost",
-      "Duration": 200,
-      "Value": "108"
-    },
-    {
-      "PowerHint": "REFRESH_120FPS",
-      "Type": "MaskHint",
-      "Value": "BOOST_60HZ"
-    },
-    {
-      "PowerHint": "REFRESH_60FPS",
-      "Type": "MaskHint",
-      "Value": "BOOST_120HZ"
+      "Duration": 0,
+      "Value": "1"
     },
     {
       "PowerHint": "DISPLAY_IDLE",
@@ -1183,21 +1656,6 @@
     {
       "PowerHint": "DISPLAY_IDLE",
       "Type": "EndHint",
-      "Value": "INTERACTION"
-    },
-    {
-      "PowerHint": "DISPLAY_IDLE",
-      "Type": "EndHint",
-      "Value": "BOOST_120HZ"
-    },
-    {
-      "PowerHint": "DISPLAY_IDLE",
-      "Type": "EndHint",
-      "Value": "BOOST_60HZ"
-    },
-    {
-      "PowerHint": "DISPLAY_IDLE",
-      "Type": "EndHint",
       "Value": "DISPLAY_UPDATE_IMMINENT"
     },
     {
@@ -1207,11 +1665,6 @@
       "Value": "1"
     },
     {
-      "PowerHint": "DISPLAY_UPDATE_IMMINENT",
-      "Type": "DoHint",
-      "Value": "BOOST_DISPLAY"
-    },
-    {
       "PowerHint": "THERMAL_FLASH_LED_REDUCE_CRITICAL",
       "Node": "LimitFlashCurrent",
       "Duration": 0,
@@ -1233,57 +1686,507 @@
       "PowerHint": "EXPENSIVE_RENDERING",
       "Node": "GPUMinFreq",
       "Duration": 0,
-      "Value": "400000"
+      "Value": "572000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "BigControlTempSet",
       "Duration": 0,
       "Value": "80000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "MidControlTempSet",
       "Duration": 0,
       "Value": "80000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "LittleControlTempSet",
       "Duration": 0,
       "Value": "80000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "G3dControlTempSet",
       "Duration": 0,
       "Value": "80000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "BigSwitchOnTempSet",
       "Duration": 0,
       "Value": "60000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "MidSwitchOnTempSet",
       "Duration": 0,
       "Value": "60000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "LittleSwitchOnTempSet",
       "Duration": 0,
       "Value": "60000"
     },
     {
-      "PowerHint": "THERMAL_VIRTUAL-SKIN_SEVERE",
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
       "Node": "G3dSwitchOnTempSet",
       "Duration": 0,
       "Value": "60000"
     },
     {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "AurSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "Dex2oatThreads",
+      "Duration": 0,
+      "Value": "4"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "Dex2oatCPUSet",
+      "Duration": 0,
+      "Value": "0,1,2,3"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_LIGHT",
+      "Node": "Dex2oatGroup",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "BigControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "MidControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "LittleControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "G3dControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "BigSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "MidSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "LittleSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "G3dSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "AurSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "Dex2oatThreads",
+      "Duration": 0,
+      "Value": "4"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "Dex2oatCPUSet",
+      "Duration": 0,
+      "Value": "0,1,2,3"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_MODERATE",
+      "Node": "Dex2oatGroup",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "BigControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "MidControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "LittleControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "G3dControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "BigSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "MidSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "LittleSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "G3dSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "AurSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "Dex2oatThreads",
+      "Duration": 0,
+      "Value": "2"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "Dex2oatCPUSet",
+      "Duration": 0,
+      "Value": "0,1,2,3"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_SEVERE",
+      "Node": "Dex2oatGroup",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "BigControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "MidControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "LittleControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "G3dControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "BigSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "MidSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "LittleSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "G3dSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "AurSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "Dex2oatThreads",
+      "Duration": 0,
+      "Value": "2"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "Dex2oatCPUSet",
+      "Duration": 0,
+      "Value": "0,1,2,3"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_CRITICAL",
+      "Node": "Dex2oatGroup",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "PMU_POLL",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "CPU_LITTLE_TSKIN_BYPASS",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "CPU_MID_TSKIN_BYPASS",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "CPU_BIG_TSKIN_BYPASS",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "BigControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "MidControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "LittleControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "G3dControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "TpuControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "AurControlTempSet",
+      "Duration": 0,
+      "Value": "80000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "BigSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "MidSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "LittleSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "G3dSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "TpuSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "AurSwitchOnTempSet",
+      "Duration": 0,
+      "Value": "60000"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "Dex2oatThreads",
+      "Duration": 0,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "Dex2oatCPUSet",
+      "Duration": 0,
+      "Value": "0,1,2,3"
+    },
+    {
+      "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY",
+      "Node": "Dex2oatGroup",
+      "Duration": 0,
+      "Value": "0"
+    },
+    {
       "PowerHint": "FACE_UNLOCK_BOOST",
       "Node": "CPUBigClusterMaxFreq",
       "Duration": 1000,
@@ -1291,9 +2194,21 @@
     },
     {
       "PowerHint": "FACE_UNLOCK_BOOST",
-      "Node": "CPUBigClusterMinFreq",
+      "Node": "CPU_LITTLE_TSKIN_BYPASS",
       "Duration": 1000,
-      "Value": "9999999"
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FACE_UNLOCK_BOOST",
+      "Node": "CPU_MID_TSKIN_BYPASS",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FACE_UNLOCK_BOOST",
+      "Node": "CPU_BIG_TSKIN_BYPASS",
+      "Duration": 1000,
+      "Value": "1"
     },
     {
       "PowerHint": "FP_BOOST",
@@ -1308,22 +2223,46 @@
       "Value": "9999999"
     },
     {
+      "PowerHint": "FP_BOOST",
+      "Node": "CPU_LITTLE_TSKIN_BYPASS",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FP_BOOST",
+      "Node": "CPU_MID_TSKIN_BYPASS",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FP_BOOST",
+      "Node": "CPU_BIG_TSKIN_BYPASS",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FP_BOOST",
+      "Node": "TRUSTY_VIRTIO_HIGH",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
+      "PowerHint": "FP_BOOST",
+      "Node": "TRUSTY_HIGH",
+      "Duration": 1000,
+      "Value": "1"
+    },
+    {
       "PowerHint": "ML_ACC",
       "Node": "MLUclampBoost",
       "Duration": 2000,
-      "Value": "512"
+      "Value": "813"
     },
     {
-      "PowerHint": "DEVICE_IDLE",
-      "Node": "RestrictedCpuset",
-      "Duration": 0,
-      "Value": "0-3"
-    },
-    {
-      "PowerHint": "DISPLAY_INACTIVE",
-      "Node": "RestrictedCpuset",
-      "Duration": 0,
-      "Value": "0-3"
+      "PowerHint": "ML_ACC",
+      "Node": "PMQoSCpuDmaLatency",
+      "Duration": 2000,
+      "Value": "44"
     }
   ],
   "AdpfConfig": [
@@ -1332,15 +2271,15 @@
       "PID_On": true,
       "PID_Po": 2.0,
       "PID_Pu": 1.0,
-      "PID_I": 0.001,
+      "PID_I": 0.0,
       "PID_I_Init": 200,
       "PID_I_High": 512,
       "PID_I_Low": -30,
       "PID_Do": 500.0,
       "PID_Du": 0.0,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 5,
-      "UclampMin_High": 384,
+      "UclampMin_Init": 232,
+      "UclampMin_High": 480,
       "UclampMin_Low": 2,
       "SamplingWindow_P": 1,
       "SamplingWindow_I": 0,
@@ -1356,15 +2295,15 @@
       "PID_On": true,
       "PID_Po": 2.0,
       "PID_Pu": 1.0,
-      "PID_I": 0.001,
+      "PID_I": 0.0,
       "PID_I_Init": 200,
       "PID_I_High": 512,
       "PID_I_Low": -30,
       "PID_Do": 500.0,
       "PID_Du": 0.0,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 5,
-      "UclampMin_High": 384,
+      "UclampMin_Init": 162,
+      "UclampMin_High": 480,
       "UclampMin_Low": 2,
       "SamplingWindow_P": 1,
       "SamplingWindow_I": 0,
@@ -1380,15 +2319,15 @@
       "PID_On": true,
       "PID_Po": 2.0,
       "PID_Pu": 1.0,
-      "PID_I": 0.001,
+      "PID_I": 0.0,
       "PID_I_Init": 200,
       "PID_I_High": 512,
       "PID_I_Low": -30,
       "PID_Do": 500.0,
       "PID_Du": 0.0,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 5,
-      "UclampMin_High": 384,
+      "UclampMin_Init": 162,
+      "UclampMin_High": 480,
       "UclampMin_Low": 2,
       "SamplingWindow_P": 1,
       "SamplingWindow_I": 0,
@@ -1414,9 +2353,9 @@
       "SamplingWindow_I": 1,
       "SamplingWindow_D": 1,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 0,
-      "UclampMin_High": 157,
-      "UclampMin_Low": 157,
+      "UclampMin_Init": 250,
+      "UclampMin_High": 197,
+      "UclampMin_Low": 197,
       "ReportingRateLimitNs": 1,
       "EarlyBoost_On": false,
       "EarlyBoost_TimeFactor": 0.0,
@@ -1438,9 +2377,9 @@
       "SamplingWindow_I": 1,
       "SamplingWindow_D": 1,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 0,
-      "UclampMin_High": 42,
-      "UclampMin_Low": 42,
+      "UclampMin_Init": 250,
+      "UclampMin_High": 53,
+      "UclampMin_Low": 53,
       "ReportingRateLimitNs": 1,
       "EarlyBoost_On": false,
       "EarlyBoost_TimeFactor": 0.0,
@@ -1462,7 +2401,7 @@
       "SamplingWindow_I": 1,
       "SamplingWindow_D": 1,
       "UclampMin_On": true,
-      "UclampMin_Granularity": 0,
+      "UclampMin_Init": 250,
       "UclampMin_High": 0,
       "UclampMin_Low": 0,
       "ReportingRateLimitNs": 1,
diff --git a/powerstats/felix/Android.bp b/powerstats/felix/Android.bp
index b7c146f..6a46051 100644
--- a/powerstats/felix/Android.bp
+++ b/powerstats/felix/Android.bp
@@ -16,6 +16,7 @@
     imports: [
         "hardware/google/pixel",
         "device/google/gs201/powerstats",
+        "device/google/gs-common/powerstats",
     ]
 }
 
@@ -40,5 +41,6 @@
 
     shared_libs: [
         "android.hardware.power.stats-impl.gs201",
+        "android.hardware.power.stats-impl.gs-common",
     ],
 }
diff --git a/powerstats/felix/service.cpp b/powerstats/felix/service.cpp
index a7b0824..2de3797 100644
--- a/powerstats/felix/service.cpp
+++ b/powerstats/felix/service.cpp
@@ -19,6 +19,7 @@
 #include <dataproviders/DisplayStateResidencyDataProvider.h>
 #include <dataproviders/GenericStateResidencyDataProvider.h>
 #include <dataproviders/PowerStatsEnergyConsumer.h>
+#include <DevfreqStateResidencyDataProvider.h>
 #include <Gs201CommonDataProviders.h>
 #include <PowerStatsAidl.h>
 
@@ -27,43 +28,53 @@
 #include <android/binder_manager.h>
 #include <android/binder_process.h>
 #include <log/log.h>
+#include <sys/stat.h>
 
+using aidl::android::hardware::power::stats::DevfreqStateResidencyDataProvider;
 using aidl::android::hardware::power::stats::DisplayStateResidencyDataProvider;
 using aidl::android::hardware::power::stats::EnergyConsumerType;
 using aidl::android::hardware::power::stats::GenericStateResidencyDataProvider;
 using aidl::android::hardware::power::stats::PowerStatsEnergyConsumer;
 
 void addDisplay(std::shared_ptr<PowerStats> p) {
-    // Add display residency stats
-    std::vector<std::string> states = {
+    // Add display residency stats for inner display
+    std::vector<std::string> inner_states = {
         "Off",
-        "LP: 1440x3120@1",
-        "LP: 1440x3120@10",
-        "LP: 1440x3120@30",
-        "On: 1440x3120@60",
-        "On: 1440x3120@90",
-        "On: 1440x3120@120",
-        "HBM: 1440x3120@60",
-        "HBM: 1440x3120@90",
-        "HBM: 1440x3120@120"};
+        "LP: 1840x2208@1",
+        "LP: 1840x2208@30",
+        "On: 1840x2208@1",
+        "On: 1840x2208@10",
+        "On: 1840x2208@60",
+        "On: 1840x2208@120",
+        "HBM: 1840x2208@60",
+        "HBM: 1840x2208@120"};
 
     p->addStateResidencyDataProvider(std::make_unique<DisplayStateResidencyDataProvider>(
-            "Display",
+            "Inner Display",
             "/sys/class/backlight/panel0-backlight/state",
-            states));
+            inner_states));
+
+    // Add display residency stats for outer display
+    std::vector<std::string> outer_states = {
+        "Off",
+        "LP: 1080x2092@30",
+        "On: 1080x2092@10",
+        "On: 1080x2092@60",
+        "On: 1080x2092@120",
+        "HBM: 1080x2092@60",
+        "HBM: 1080x2092@120"};
+
+    p->addStateResidencyDataProvider(std::make_unique<DisplayStateResidencyDataProvider>(
+            "Outer Display",
+            "/sys/class/backlight/panel1-backlight/state",
+            outer_states));
 
     // Add display energy consumer
-    p->addEnergyConsumer(PowerStatsEnergyConsumer::createMeterAndEntityConsumer(
-            p, EnergyConsumerType::DISPLAY, "display", {"PPVAR_VSYS_PWR_DISP"}, "Display",
-            {{"LP: 1440x3120@1", 1},
-             {"LP: 1440x3120@10", 2},
-             {"LP: 1440x3120@30", 3},
-             {"On: 1440x3120@60", 4},
-             {"On: 1440x3120@90", 5},
-             {"On: 1440x3120@120", 6},
-             {"HBM: 1440x3120@60", 7},
-             {"HBM: 1440x3120@90", 8},
-             {"HBM: 1440x3120@120", 9}}));
+    p->addEnergyConsumer(PowerStatsEnergyConsumer::createMeterConsumer(
+            p,
+            EnergyConsumerType::DISPLAY,
+            "Display",
+            {"VSYS_PWR_DISPLAY"}));// VSYS_PWR_DISPLAY = inner + outer
 }
 
 void addUwb(std::shared_ptr<PowerStats> p) {
@@ -99,6 +110,49 @@
             "/sys/devices/platform/10db0000.spi/spi_master/spi16/spi16.0/uwb/power_stats", cfgs));
 }
 
+void addGPU(std::shared_ptr<PowerStats> p) {
+    std::map<std::string, int32_t> stateCoeffs;
+
+    // Add GPU state residency
+    p->addStateResidencyDataProvider(std::make_unique<DevfreqStateResidencyDataProvider>(
+            "GPU",
+            "/sys/devices/platform/28000000.mali"));
+
+    // Add GPU energy consumer
+    stateCoeffs = {
+        {"202000",  890},
+        {"251000", 1102},
+        {"302000", 1308},
+        {"351000", 1522},
+        {"400000", 1772},
+        {"471000", 2105},
+        {"510000", 2292},
+        {"572000", 2528},
+        {"701000", 3127},
+        {"762000", 3452},
+        {"848000", 4044}};
+
+    p->addEnergyConsumer(PowerStatsEnergyConsumer::createMeterAndAttrConsumer(
+            p,
+            EnergyConsumerType::OTHER,
+            "GPU",
+            {"S2S_VDD_G3D", "S8S_VDD_G3D_L2"},
+            {{UID_TIME_IN_STATE, "/sys/devices/platform/28000000.mali/uid_time_in_state"}},
+            stateCoeffs));
+}
+
+std::string getNfcPath() {
+    struct stat buffer;
+    int size = 128;
+    char path[size];
+    for (int i = 0; i < 10; i++) {
+        std::snprintf(path, size,
+                "/sys/devices/platform/10970000.hsi2c/i2c-%d/i2c-st21nfc/power_stats", i);
+        if (!stat(path, &buffer)) break;
+    }
+    return std::string(path);
+}
+
 int main() {
     LOG(INFO) << "Pixel PowerStats HAL AIDL Service is starting.";
 
@@ -107,10 +161,24 @@
 
     std::shared_ptr<PowerStats> p = ndk::SharedRefBase::make<PowerStats>();
 
-    addGs201CommonDataProviders(p);
+    setEnergyMeter(p);
+    addAoC(p);
+    addPixelStateResidencyDataProvider(p);
+    addCPUclusters(p);
     addDisplay(p);
+    addSoC(p);
+    addGNSS(p);
+    addMobileRadio(p);
+    addPCIe(p);
+    addWifi(p);
+    addTPU(p);
+    addUfs(p);
+    addNFC(p, getNfcPath());
     addUwb(p);
-    addNFC(p, "/sys/devices/platform/10970000.hsi2c/i2c-4/i2c-st21nfc/power_stats");
+    addPowerDomains(p);
+    addDevfreq(p);
+    addGPU(p);
+    addDvfsStats(p);
 
     const std::string instance = std::string() + PowerStats::descriptor + "/default";
     binder_status_t status = AServiceManager_addService(p->asBinder().get(), instance.c_str());
diff --git a/rro_overlays/UwbOverlay/Android.bp b/rro_overlays/UwbOverlay/Android.bp
new file mode 100644
index 0000000..bdaa13d
--- /dev/null
+++ b/rro_overlays/UwbOverlay/Android.bp
@@ -0,0 +1,18 @@
+package {
+    // See: http://go/android-license-faq
+    // A large-scale-change added 'default_applicable_licenses' to import
+    // all of the 'license_kinds' from "//device/google/felix:device_google_felix_license"
+    // to get the below license kinds:
+    //   SPDX-license-identifier-Apache-2.0
+    default_applicable_licenses: [
+        "//device/google/felix:device_google_felix_license",
+    ],
+}
+
+runtime_resource_overlay {
+    name: "UwbOverlayF10",
+    theme: "UwbOverlayF10",
+    certificate: "platform",
+    sdk_version: "current",
+    product_specific: true
+}
diff --git a/rro_overlays/UwbOverlay/AndroidManifest.xml b/rro_overlays/UwbOverlay/AndroidManifest.xml
new file mode 100644
index 0000000..57dfd5b
--- /dev/null
+++ b/rro_overlays/UwbOverlay/AndroidManifest.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Copyright (C) 2022 The Android Open Source Project
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+<!-- Pixel specific uwb overlays -->
+<manifest xmlns:android="http://schemas.android.com/apk/res/android"
+    package="com.android.uwb.resources.pixel"
+    android:versionCode="1"
+    android:versionName="1.0">
+    <application android:hasCode="false" />
+    <overlay
+      android:targetPackage="com.android.uwb.resources"
+      android:targetName="UwbCustomization"
+      android:isStatic="true"
+      android:priority="0"/>
+</manifest>
diff --git a/rro_overlays/UwbOverlay/OWNERS b/rro_overlays/UwbOverlay/OWNERS
new file mode 100644
index 0000000..2395d7f
--- /dev/null
+++ b/rro_overlays/UwbOverlay/OWNERS
@@ -0,0 +1,3 @@
+# People who can approve changes for submission
+include platform/packages/modules/Uwb:/OWNERS
+victorliu@google.com
diff --git a/rro_overlays/UwbOverlay/res/values/config.xml b/rro_overlays/UwbOverlay/res/values/config.xml
new file mode 100644
index 0000000..3c45c6a
--- /dev/null
+++ b/rro_overlays/UwbOverlay/res/values/config.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+-->
+<resources>
+    <!-- When true, the filter engine will alter UWB values to improve accuracy. -->
+    <bool name="enable_filters">true</bool>
+
+    <!-- Enables the AoA conversion primer. This is needed on hardware that does not convert AoA
+    to spherical coordinates, including hardware that does not support elevation.-->
+    <bool name="enable_primer_aoa">true</bool>
+</resources>
diff --git a/rro_overlays/WifiOverlay/Android.bp b/rro_overlays/WifiOverlay/Android.bp
new file mode 100644
index 0000000..ae60aa3
--- /dev/null
+++ b/rro_overlays/WifiOverlay/Android.bp
@@ -0,0 +1,18 @@
+package {
+    // See: http://go/android-license-faq
+    // A large-scale-change added 'default_applicable_licenses' to import
+    // all of the 'license_kinds' from "//device/google/felix:device_google_felix_license"
+    // to get the below license kinds:
+    //   SPDX-license-identifier-Apache-2.0
+    default_applicable_licenses: [
+        "//device/google/felix:device_google_felix_license",
+    ],
+}
+
+runtime_resource_overlay {
+    name: "WifiOverlay2023Mid_F10",
+    theme: "WifiOverlay2023Mid_F10",
+    certificate: "platform",
+    sdk_version: "current",
+    product_specific: true
+}
diff --git a/rro_overlays/WifiOverlay/AndroidManifest.xml b/rro_overlays/WifiOverlay/AndroidManifest.xml
new file mode 100644
index 0000000..0a1b153
--- /dev/null
+++ b/rro_overlays/WifiOverlay/AndroidManifest.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Copyright (C) 2022 The Android Open Source Project
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+-->
+<!-- Pixel specific wifi overlays -->
+<manifest xmlns:android="http://schemas.android.com/apk/res/android"
+    package="com.android.wifi.resources.pixel"
+    android:versionCode="1"
+    android:versionName="1.0">
+    <application android:hasCode="false" />
+    <overlay
+      android:targetPackage="com.android.wifi.resources"
+      android:targetName="WifiCustomization"
+      android:isStatic="true"
+      android:priority="0"/>
+</manifest>
diff --git a/rro_overlays/WifiOverlay/OWNERS b/rro_overlays/WifiOverlay/OWNERS
new file mode 100644
index 0000000..8b6c5a7
--- /dev/null
+++ b/rro_overlays/WifiOverlay/OWNERS
@@ -0,0 +1,4 @@
+# People who can approve changes for submission
+kumachang@google.com
+wangroger@google.com
+hsuvictor@google.com
diff --git a/rro_overlays/WifiOverlay/res/values/config.xml b/rro_overlays/WifiOverlay/res/values/config.xml
new file mode 100644
index 0000000..94f377b
--- /dev/null
+++ b/rro_overlays/WifiOverlay/res/values/config.xml
@@ -0,0 +1,170 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+-->
+<resources>
+    <!-- Boolean indicating whether the wifi chipset has 5GHz frequency band support -->
+    <bool translatable="false" name="config_wifi5ghzSupport">true</bool>
+
+    <!-- boolean indicating whether the WiFi chipset has 6GHz band support -->
+    <bool translatable="false" name ="config_wifi6ghzSupport">true</bool>
+
+    <!-- Boolean indicating whether 802.11r Fast BSS Transition is enabled on this platform -->
+    <bool translatable="false" name="config_wifi_fast_bss_transition_enabled">true</bool>
+
+    <!-- Boolean indicating whether the wifi chipset has background scan support -->
+    <bool translatable="false" name="config_wifi_background_scan_support">true</bool>
+
+    <!-- Integer thresholds, do not connect to APs with RSSI lower than these values  -->
+    <integer translatable="false" name="config_wifi_framework_wifi_score_entry_rssi_threshold_5GHz">-77</integer>
+    <integer translatable="false" name="config_wifi_framework_wifi_score_entry_rssi_threshold_24GHz">-80</integer>
+    <!-- Integer thresholds for low network score, should be somewhat less than the entry thresholds -->
+    <integer translatable="false" name="config_wifi_framework_wifi_score_bad_rssi_threshold_5GHz">-80</integer>
+    <integer translatable="false" name="config_wifi_framework_wifi_score_bad_rssi_threshold_24GHz">-83</integer>
+
+    <!-- Boolean indicating whether or not to revert to default country code when cellular
+    radio is unable to find any MCC information to infer wifi country code from -->
+    <bool translatable="false" name="config_wifi_revert_country_code_on_cellular_loss">false</bool>
+
+    <!-- Boolean indicating whether or not wifi should turn off when emergency call is made -->
+    <bool translatable="false" name="config_wifi_turn_off_during_emergency_call">true</bool>
+
+    <!-- Configure wifi tcp buffersizes in the form:
+         rmem_min,rmem_def,rmem_max,wmem_min,wmem_def,wmem_max -->
+    <string name="config_wifi_tcp_buffers" translatable="false">524288,2097152,8388608,262144,524288,4194304</string>
+
+    <!-- Enable ACS (auto channel selection) for Wifi hotspot (SAP) -->
+    <bool translatable="false" name="config_wifi_softap_acs_supported">true</bool>
+
+    <!-- Enable 802.11ac for Wifi hotspot (SAP) -->
+    <bool translatable="false" name="config_wifi_softap_ieee80211ac_supported">true</bool>
+
+    <!-- True if the firmware supports connected MAC randomization -->
+    <bool name="config_wifi_connected_mac_randomization_supported">true</bool>
+    <bool name="config_wifiAllowNonPersistentMacRandomizationOnOpenSsids">true</bool>
+
+    <!-- True if the firmware supports p2p MAC randomization -->
+    <bool name="config_wifi_p2p_mac_randomization_supported">true</bool>
+
+    <!-- True if the firmware supports ap MAC randomization -->
+    <bool name="config_wifi_ap_mac_randomization_supported">true</bool>
+
+    <!-- True if the firmware supports Wi-Fi link probing -->
+    <bool name="config_wifi_link_probing_supported">true</bool>
+
+    <!-- Indicates that a full bugreport should be triggered when wifi diagnostics detects an error on non-user (i.e debug) builds -->
+    <bool translatable="false" name="config_wifi_diagnostics_bugreport_enabled">true</bool>
+
+    <!-- Default access point SSID used for tethering -->
+    <string name="wifi_tether_configure_ssid_default" translatable="false">Pixel</string>
+
+    <!-- Integer indicating maximum hardware supported client number of soft ap -->
+    <integer translatable="false" name="config_wifiHardwareSoftapMaxClientCount">32</integer>
+
+    <!-- Array indicating wifi fatal firmware alert error code list from driver -->
+    <array translatable="false" name="config_wifi_fatal_firmware_alert_error_code_list">
+        <item>1</item>      <!-- ALERT_TX_STALL -->
+        <item>2</item>      <!-- ALERT_RX_STALL -->
+        <item>3</item>      <!-- ALERT_IOCTL_TIMEOUT -->
+        <item>8</item>      <!-- ALERT_FW_QUEUE_STALL -->
+    </array>
+
+    <!-- Integer delay in milliseconds before set wlan interface up during watchdog recovery -->
+    <integer name="config_wifi_framework_recovery_timeout_delay">3000</integer>
+
+    <!-- Number of self recoveries to be attempted per hour. Any fatal errors beyond this will
+         cause the wifi stack to turn wifi off and wait for user input.
+         Set to 0 to turn off recovery attempts and always turn off wifi on failures -->
+    <integer translatable="false" name="config_wifiMaxNativeFailureSelfRecoveryPerHour">10</integer>
+
+    <!-- Wifi driver supports IEEE80211AX for softap -->
+    <bool translatable="false" name="config_wifiSoftapIeee80211axSupported">true</bool>
+
+      <!-- Indicates that 11ax mode is supported on this device
+           Note that if this flag is set to true, then 11ax is assumed to be supported.
+           However, if it is left to the default value of false, the 11ax support will
+           be checked via NL80211 interface -->
+    <bool translatable="false" name="config_wifi11axSupportOverride">true</bool>
+
+    <!-- Wifi driver supports WPA3 Simultaneous Authentication of Equals (WPA3-SAE) for softap -->
+    <bool translatable="false" name="config_wifi_softap_sae_supported">true</bool>
+
+    <!-- Override channel utilization estimation with fixed value, disabled in brcm-based pixels -->
+    <bool translatable="false" name="config_wifiChannelUtilizationOverrideEnabled">false</bool>
+
+    <!-- Enable adding minimum confirmation duration when sending network score to connectivity service. -->
+    <bool translatable="false" name="config_wifiMinConfirmationDurationSendNetworkScoreEnabled">true</bool>
+
+    <!-- Enable concurrent STA + STA peer to peer + internet connectivity -->
+    <bool translatable="false" name="config_wifiMultiStaLocalOnlyConcurrencyEnabled">true</bool>
+
+    <!-- Enable concurrent STA + STA MBB support -->
+    <bool translatable="false" name="config_wifiMultiStaNetworkSwitchingMakeBeforeBreakEnabled">true</bool>
+
+    <!-- Enable concurrent Bridged access point (AP) support -->
+    <bool translatable="false" name="config_wifiBridgedSoftApSupported">true</bool>
+
+    <!-- Enable concurrent STA + Bridged access point (AP) support -->
+    <bool translatable="false" name="config_wifiStaWithBridgedSoftApConcurrencySupported">true</bool>
+
+    <!-- Indicates that SAE Hash-to-Element is supported on this device -->
+    <bool translatable="false" name="config_wifiSaeH2eSupported">true</bool>
+
+    <!-- Enable the default coex channel avoidance algorithm and disable the functionality of
+         WifiManager#setCoexUnsafeChannels. -->
+    <bool translatable="false" name="config_wifiDefaultCoexAlgorithmEnabled">true</bool>
+
+    <!-- If the default coex channel avoidance algorithm is enabled, then avoid channels that
+         conflict with GPS L1. -->
+    <bool translatable="false" name="config_wifiCoexForGpsL1">true</bool>
+
+    <!-- The distance in KHz between Wi-Fi-based interference and GPS L1 that is considered unsafe. -->
+    <integer translatable="false" name="config_wifiCoexGpsL1ThresholdKhz">10000</integer>
+
+    <!-- Whether to use the explicit vendor HAL API: IWifiStaIface.setRoamingState for disabling fw roaming. -->
+    <bool translatable="false" name="config_wifiUseHalApiToDisableFwRoaming">true</bool>
+
+    <!-- Indicate the driver doesn't support NL80211 Reg changed event -->
+    <bool translatable="false" name="config_wifiDriverSupportedNl80211RegChangedEvent">false</bool>
+
+    <!-- Indicate whether the verbose logging is always on -->
+    <!-- 0: verbose logging controlled by user
+         1: verbose logging on by default for userdebug
+         2: verbose logging on by default for all builds -->
+    <integer translatable="false" name="config_wifiVerboseLoggingAlwaysOnLevel">1</integer>
+
+    <!-- Enable aggregation of Wifi link layer radio stats from all radios -->
+    <bool translatable="false" name="config_wifiLinkLayerAllRadiosStatsAggregationEnabled">true</bool>
+
+    <!-- Enable WPA2 to WPA3 auto-upgrade offload to capable Driver/Firmware -->
+    <bool translatable="false" name="config_wifiSaeUpgradeOffloadEnabled">true</bool>
+
+    <!-- Boolean indicating whether DTIM multiplier configuration is enabled. DTIM multiplier value
+        is when the system is in the suspended mode -->
+    <bool translatable="false" name="config_wifiDtimMultiplierConfigEnabled">true</bool>
+
+    <!-- Enable the feature of adjusting link layer stats polling interval based on
+    device mobility state and client mode RSSI monitoring. -->
+    <bool translatable="false" name="config_wifiAdjustPollRssiIntervalEnabled">true</bool>
+
+    <!-- Boolean indicating whether the framework updates country from scan results when there is
+         no telephony country code. This is applied to all generic cases and might require the
+         regulatory approval (for example, FCC pre-approval is required according to "594280 D01
+         Software Configuration Control v02r01").-->
+    <bool translatable="false" name ="config_wifiUpdateCountryCodeFromScanResultGeneric">true</bool>
+</resources>
diff --git a/self-extractors/Android.mk b/self-extractors/Android.mk
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/self-extractors/Android.mk
diff --git a/self-extractors/METADATA b/self-extractors/METADATA
new file mode 100644
index 0000000..d97975c
--- /dev/null
+++ b/self-extractors/METADATA
@@ -0,0 +1,3 @@
+third_party {
+  license_type: NOTICE
+}
diff --git a/self-extractors/PART1 b/self-extractors/PART1
new file mode 100644
index 0000000..935267e
--- /dev/null
+++ b/self-extractors/PART1
@@ -0,0 +1,12 @@
+#
+# Usage is subject to the enclosed license agreement
+
+echo
+echo The license for this software will now be displayed.
+echo You must agree to this license before using this software.
+echo
+echo -n Press Enter to view the license
+read dummy
+echo
+
+more << __EOF__
diff --git a/self-extractors/PART2 b/self-extractors/PART2
new file mode 100644
index 0000000..30e8d43
--- /dev/null
+++ b/self-extractors/PART2
@@ -0,0 +1,22 @@
+__EOF__
+
+if test $? != 0
+then
+  echo ERROR: Couldn\'t display license file 1>&2
+  exit 1
+fi
+
+echo
+
+echo -n Type \"I ACCEPT\" if you agree to the terms of the license:\ 
+read typed
+
+if test "$typed" != I\ ACCEPT
+then
+  echo
+  echo You didn\'t accept the license. Extraction aborted.
+  exit 2
+fi
+
+echo
+
diff --git a/self-extractors/PART3 b/self-extractors/PART3
new file mode 100644
index 0000000..6847be5
--- /dev/null
+++ b/self-extractors/PART3
@@ -0,0 +1,12 @@
+
+if test $? != 0
+then
+  echo
+  echo ERROR: Couldn\'t extract files. 1>&2
+  exit 3
+else
+  echo
+  echo Files extracted successfully.
+fi
+exit 0
+
diff --git a/self-extractors/PROLOGUE b/self-extractors/PROLOGUE
new file mode 100644
index 0000000..c856ef1
--- /dev/null
+++ b/self-extractors/PROLOGUE
@@ -0,0 +1,2 @@
+#!/bin/bash
+#
diff --git a/self-extractors/extract-lists.txt b/self-extractors/extract-lists.txt
new file mode 100644
index 0000000..9fc0800
--- /dev/null
+++ b/self-extractors/extract-lists.txt
@@ -0,0 +1,18 @@
+  google_devices)
+    TO_EXTRACT="\
+            IMAGES/vbmeta_vendor.img \
+            IMAGES/vendor.img \
+            IMAGES/vendor_dlkm.img \
+            RADIO/bootloader.img \
+            RADIO/radio.img \
+            system_ext/etc/permissions/com.shannon.imsservice.xml \
+            system_ext/etc/permissions/com.shannon.rcsservice.xml \
+            system_ext/etc/permissions/privapp-permissions-qorvo.xml \
+            system_ext/lib64/libmediaadaptor.so \
+            system_ext/priv-app/ShannonRcs/ShannonRcs.apk \
+            system_ext/priv-app/ShannonIms/ShannonIms.apk \
+            system_ext/priv-app/PixelQualifiedNetworksService/PixelQualifiedNetworksService.apk \
+            system_ext/priv-app/UwbVendorService/UwbVendorService.apk \
+            "
+    ;;
+
diff --git a/self-extractors/google_devices/COPYRIGHT b/self-extractors/google_devices/COPYRIGHT
new file mode 100644
index 0000000..db593ae
--- /dev/null
+++ b/self-extractors/google_devices/COPYRIGHT
@@ -0,0 +1 @@
+# (C) Google Inc.
diff --git a/self-extractors/google_devices/LICENSE b/self-extractors/google_devices/LICENSE
new file mode 100644
index 0000000..6b4042b
--- /dev/null
+++ b/self-extractors/google_devices/LICENSE
@@ -0,0 +1,264 @@
+THIS DEVELOPER SOFTWARE LICENSE AGREEMENT (THE "AGREEMENT") IS A LEGALLY
+BINDING AGREEMENT BETWEEN Google Inc. ("LICENSOR") AND
+YOU OR THE LEGAL ENTITY YOU REPRESENT ("You" or its possessive, "Your"). BY
+TYPING "I ACCEPT" WHERE INDICATED YOU ACKNOWLEDGE THAT YOU HAVE READ THIS
+AGREEMENT, UNDERSTAND IT AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS.
+IF YOU DO NOT AGREE TO THESE TERMS YOU MUST DISCONTINUE THE INSTALLATION
+PROCESS AND YOU SHALL NOT USE THE SOFTWARE OR RETAIN ANY COPIES OF THE
+SOFTWARE OR DOCUMENTATION. ANY USE OR POSSESSION OF THE SOFTWARE BY YOU IS
+SUBJECT TO THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT. IF THE
+SOFTWARE IS INSTALLED ON A COMPUTER OWNED BY A CORPORATION OR OTHER LEGAL
+ENTITY, THEN YOU REPRESENT AND WARRANT THAT YOU HAVE THE AUTHORITY TO BIND
+SUCH ENTITY TO THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+
+   1.  Special Definitions
+
+      a.  The term "Android" means the open source mobile platform, software
+          stack, operating system, middleware, application programming
+          interfaces and mobile applications under the trade-name "Android"
+          distributed at Android.com.
+
+      b.  The term "Android Applications" means a software application or
+          open-source contribution developed by You, designed to operate with
+          Android that does not contain or incorporate any of the Software.
+
+      c.  The term "Authorized Android Enabled Device" means only the device
+          identified on the site from which You downloaded the Software.
+          The term "Software" means the Licensor's proprietary software and
+          libraries in object code form, designed for use on the Authorized
+          Android Enabled Device.
+
+      d.  The term "Authorized Android Enabled Device Software" means a
+          packaged build for Authorized Android Enabled Devices, consisting
+          of files suitable for installation on an Authorized Android Enabled
+          Device using a mechanism such as fastboot mode or recovery mode.
+
+   2.  License Grant
+
+      a.  Subject to the terms of this Agreement, Licensor hereby grants to
+          You, free of charge, a non-exclusive, non-sublicensable,
+          non-transferable, limited copyright license, during the term of
+          this Agreement, to download, install and use the Software
+          internally in machine-readable (i.e., object code) form and the
+          Documentation for non-commercial use on an Authorized Android
+          Enabled Device and non-commercial redistribution for academic
+          purposes only of a reasonable number of copies of the Authorized
+          Android Enabled Device Software (the "Limited Purpose"). You may
+          grant your end users the right to use the Software for
+          non-commercial purposes on an Authorized Android Enabled Device.
+          The license to the Software granted to You hereunder is solely for
+          the Limited Purpose set forth in this section, and the Software
+          shall not be used for any other purpose.
+
+   3.  Restrictions
+
+      a.  Retention of Rights. The entire right, title and interest in the
+          Software shall remain with Licensor and, unless specified in
+          writing hereunder, no rights are granted to any of the Software.
+          Except for the right to use the Software for the Limited Purpose,
+          the delivery of the Software to You does not convey to You any
+          intellectual property rights in the Software, including, but not
+          limited to any rights under any patent, trademark, copyright, or
+          trade secret. Neither the delivery of the Software to You nor any
+          terms set forth herein shall be construed to grant to You, either
+          expressly, by implication or by way of estoppel, any license under
+          any patents or other intellectual property rights covering or
+          relating to any other product or invention or any combination of
+          the Software with any other product. Any rights not expressly
+          granted to You herein are reserved by Licensor.
+
+      b.  No Commercialization or Distribution of the Software and
+          Documentation. Except as expressly provided in Section 2 of this
+          Agreement, You shall have no right to (i) copy, disclose,
+          distribute, publically perform, publically display, transfer,
+          alter, modify, translate, disassemble, decompile, reverse engineer,
+          or adapt the Software and Documentation, or any portion thereof, or
+          create any derivative works based thereon; (ii) rent, lease,
+          assign, sublicense, resell, disclose or otherwise transfer the
+          Software and Documentation in whole or in part to any third party
+          (iii) use the Software and Documentation except for the Limited
+          Purpose, (iv) remove or alter any of the copyright or proprietary
+          notices contained in any of the Software and Documentation. For the
+          purposes of clarity, nothing in this Agreement prohibits You from
+          making and distributing Android Applications under commercial or
+          non-commercial terms, provided that You shall not contain,
+          incorporate, and/or compile the Software or any of its derivative
+          works, in whole or in part, into Your Android Applications and/or
+          any software/devices created by You or by third parties acting on
+          Your behalf. You and any such third party shall comply with all of
+          the terms and conditions of this Agreement.
+
+      c.  No Reverse Engineering. Except for any portions of the Software
+          provided to You in source code format and except for any third
+          party code distributed with the Software that is licensed under
+          contrary terms, You will not reverse engineer, disassemble,
+          decompile, or translate the Software, or otherwise attempt to
+          derive the source code version of the Software, except if and to
+          the extent expressly permitted under any applicable law.
+
+      d.  Third Party Software. You agree that Android may contain third
+          party software. You agree that you may not distribute such third
+          party software for any purpose without appropriate licenses from
+          the applicable third party or parties.
+
+      e.  No Transfer or Assignment. You shall not assign any of its rights
+          or obligations under this Agreement. Any attempted assignment in
+          contravention of this Section shall be void.
+
+      f.  Licensor shall retain all title, ownership and Intellectual
+          Property Rights in and to the Software and any derivative thereof.
+          "Intellectual Property Rights" shall mean all patent, copyright,
+          trade secret, trademark and other proprietary and intellectual
+          property rights, including moral rights.
+
+      g.  Neither this Agreement, nor any act by Licensor or its Affiliates
+          persuant to this Agreement or relating to the Software (including,
+          without limitation, the provision by Licensor or its Affiliates of
+          the Software) shall provide to You any license or any other rights
+          whatsoever under any patents, trademarks, trade secrets, copyrights
+          or any other intellectual property rights of Licensor or its
+          Affiliates, except for the copyrights expressly set forth in this
+          Agreement. You understand and agree that:
+
+      h.  Neither this Agreement, nor delivery of the Software alone or in
+          combination with any Licensor ASIC grants you any right to
+          practice, or any other right at all with respect to, any patent of
+          Licensor or its Affiliates, and
+
+      i.  A separating license agreement from Motorola Incorporated is needed
+          to use or practice any patent of Licensor or its Affiliates.
+
+      j.  You agree not to contend in any context that, as a result of the
+          provision or use of this software, either Licensor or Affiliate has
+          any obligation to extend, or Licensor or any other party has
+          obtained any right to, any license, whether express or implied,
+          with respect to any patent of Licensor or its Affiliates for any
+          purpose. For the purposes of this agreement, "Affiliate" means
+          (i) any corporation or any other legal entity that owns, directly
+          or indirectly, more than fifty percent (50%) of the shares, equity
+          interest or other securities of any entity entitled to vote for
+          election of directors (or other managing authority), or (ii) any
+          corporation or any other legal entity fifty percent (50%) or more
+          of whose shares, equity interest, or other securities entitled to
+          vote for election of directors (or other managing authority) is
+          owned or controlled by an entity, either directly or indirectly.
+
+   4.  Indemnity
+
+      a.  You agree to indemnify and hold harmless Licensor, Google, and
+          their officers, directors, customers, employees and successors and
+          assigns (each an "Indemnified Party") against any and all claims,
+          demands, causes of action, losses, liabilities, damages, costs and
+          expenses, incurred by the Indemnified Party (including but not
+          limited to costs of defense, investigation and reasonable
+          attorney's fees) arising out of, resulting from or related to
+          (i) any software, products, documentation, content, materials or
+          derivative works created or developed by You using the Software
+          which causes an infringement of any patent, copyright, trademark,
+          trade secret, or other property, publicity or privacy rights of any
+          third parties arising in any jurisdiction anywhere in the world,
+          (ii) the download, distribution, installation, storage, execution,
+          use or transfer of such software, products, documentation, content,
+          materials or derivative works by any person or entity, and/or
+          (iii) any breach of this Agreement by You. If requested by an
+          Indemnified Party, You agree to defend such Indemnified Party in
+          connection with any third party claims, demands, or causes of
+          action resulting from, arising out of or in connection with any of
+          the foregoing.
+
+   5.  Limitation of Liability
+
+      a.  TO THE MAXIMUM EXTENT PERMITTED UNDER APPLICABLE LAWS, UNDER NO
+          CIRCUMSTANCES, INCLUDING WITHOUT LIMITATION NEGLIGENCE, SHALL
+          LICENSOR, GOOGLE, THEIR AFFILIATES AND/OR ITS DIRECTORS, OFFICERS,
+          EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, INCIDENTAL,
+          SPECIAL, PUNITIVE OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT
+          LIMITED TO DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+          INTERRUPTION, LOSS OF BUSINESS INFORMATION AND THE LIKE) ARISING
+          OUT OF OR IN CONNECTION WITH THE SOFTWARE OR ANY DOWNLOAD,
+          INSTALLATION OR USE OF, OR INABILITY TO USE, THE SOFTWARE, EVEN IF
+          LICENSOR OR GOOGLE HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH
+          DAMAGES. SOME JURISDICTIONS DO NOT ALLOW THE LIMITATION OR
+          EXCLUSION OF LIABILITY FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES SO
+          THE ABOVE LIMITATION OR EXCLUSION MAY NOT APPLY OR MAY BE LIMITED.
+          IN NO EVENT SHALL LICENSOR'S OR GOOGLE'S TOTAL AGGREGATE LIABILITY
+          TO YOU FOR ANY AND ALL DAMAGES, LOSSES, CLAIMS AND CAUSES OF
+          ACTIONS (WHETHER IN CONTRACT, TORT, INCLUDING NEGLIGENCE,
+          INDEMNIFICATION OR OTHERWISE) EXCEED ONE HUNDRED U.S. DOLLARS
+          (US$100). THE LIMITATIONS SET FORTH IN THIS PARAGRAPH SHALL BE
+          DEEMED TO APPLY TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW.
+          THE PARTIES HAVE FULLY CONSIDERED THE FOREGOING ALLOCATION OF RISK
+          AND FIND IT REASONABLE, AND THAT THE FOREGOING LIMITATIONS IN THIS
+          PARAGRAPH ARE AN ESSENTIAL BASIS OF THE BARGAIN BETWEEN THE
+          PARTIES.
+
+   6.  No Warranty
+
+      a.  LICENSOR AND GOOGLE MAKE NO WARRANTIES, EXPRESS OR IMPLIED, WITH
+          RESPECT TO THE SOFTWARE AND DOCUMENTATION PROVIDED UNDER THIS
+          AGREEMENT, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF
+          MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR AGAINST
+          INFRINGEMENT, OR ANY EXPRESS OR IMPLIED WARRANTY ARISING OUT OF
+          TRADE USAGE OR OUT OF A COURSE OF DEALING OR COURSE OF PERFORMANCE.
+          NOTHING CONTAINED IN THIS AGREEMENT SHALL BE CONSTRUED AS A
+          WARRANTY OR REPRESENTATION BY LICENSOR (I) AS TO THE VALIDITY OR
+          SCOPE OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT
+          AND (II) THAT ANY MANUFACTURE OR USE WILL BE FREE FROM INFRINGEMENT
+          OF PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS OF
+          OTHERS, AND IT SHALL BE THE SOLE RESPONSIBILITY OF YOU TO MAKE SUCH
+          DETERMINATION AS IS NECESSARY WITH RESPECT TO THE ACQUISITION OF
+          LICENSES UNDER PATENTS AND OTHER INTELLECTUAL PROPERTY OF THIRD
+          PARTIES. LICENSOR AND GOOGLE SHALL NOT HAVE ANY OBLIGATION TO
+          PROVIDE ANY TECHNICAL SUPPORT OF THE SOFTWARE UNDER THIS AGREEMENT.
+
+   7.  Term and Termination
+
+      a.  This Agreement shall be effective on the date You accept this
+          Agreement and shall remain in effect until terminated as provided
+          herein. You may terminate the Agreement at any time by deleting and
+          destroying all copies of the Software and all related information
+          in Your possession or control. This Agreement terminates
+          immediately and automatically, with or without notice, if You fail
+          to comply with any provision hereof. Additionally, Licensor may at
+          any time terminate this Agreement, without cause, upon notice to
+          You. Upon termination You must delete or destroy all copies of the
+          Software in Your possession, and the license granted to You in this
+          Agreement shall terminate. Sections 3, 4, 5, 6 and 8 shall survive
+          the termination of this Agreement.
+
+   8.  Miscellaneous
+
+      a.  Governing Law. This Agreement is governed and interpreted in
+          accordance with the laws of the State of California without giving
+          effect to its conflict of laws provisions. The United Nations
+          Convention on Contracts for the International Sale of Goods is
+          expressly disclaimed and shall not apply. Any claim arising out of
+          or related to this Agreement must be brought exclusively in a
+          federal or state court located in Santa Clara County, California
+          and You consent to the jurisdiction and venue of such courts.
+
+      b.  Waiver and Severability. The failure of either party to require
+          performance by the other party of any provision of this Agreement
+          shall not affect the full right to require such performance at any
+          time thereafter; nor shall the waiver by either party of a breach
+          of any provision of this Agreement be taken or held to be a waiver
+          of the provision itself. Severability. If any provision of this
+          Agreement is unenforceable or invalid under any applicable law or
+          is so held by applicable court decision, such unenforceability or
+          invalidity shall not render this Agreement unenforceable or invalid
+          as a whole, and such provision shall be changed and interpreted so
+          as to best accomplish the objectives of such unenforceable or
+          invalid provision within the limits of applicable law or
+          applicable court decisions.
+
+      c.  Amendment and Modification. This Agreement and any of its terms and
+          provisions may only be amended, modified, supplemented or waived in
+          a writing signed by both parties hereto.
+
+      d.  Compliance with Laws. You shall comply with all applicable laws,
+          rules, and regulations in connection with its activities under this
+          Agreement.
+
+      e.  Entire Agreement. This Agreement completely and exclusively states
+          the agreement between You and Licensor regarding this subject
+          matter.
diff --git a/self-extractors/google_devices/staging/Android.bp.txt b/self-extractors/google_devices/staging/Android.bp.txt
new file mode 100644
index 0000000..fd5b931
--- /dev/null
+++ b/self-extractors/google_devices/staging/Android.bp.txt
@@ -0,0 +1,41 @@
+// Copyright (C) 2023 The Android Open Source Project
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+soong_namespace {
+}
+
+cc_prebuilt_library_shared {
+    name: "libmediaadaptor",
+    arch: {
+        arm64: {
+            srcs: ["lib64/libmediaadaptor.so"],
+            shared_libs: [
+                "libandroid_runtime",
+                "libbinder",
+                "libc++",
+                "liblog",
+                "libmedia",
+                "libnativehelper",
+                "libstagefright",
+                "libutils",
+            ],
+        },
+    },
+    compile_multilib: "both",
+    system_ext_specific: true,
+    strip: {
+        none: true,
+    },
+}
+
diff --git a/self-extractors/google_devices/staging/Android.mk b/self-extractors/google_devices/staging/Android.mk
new file mode 100644
index 0000000..60234be
--- /dev/null
+++ b/self-extractors/google_devices/staging/Android.mk
@@ -0,0 +1,89 @@
+#
+# Copyright (C) 2023 The Android Open-Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+ifneq ($(filter felix,$(TARGET_DEVICE)),)
+  $(call add-radio-file,bootloader.img)
+  $(call add-radio-file,radio.img)
+endif
+
+ifneq ($(filter felix,$(TARGET_DEVICE)),)
+include $(CLEAR_VARS)
+LOCAL_MODULE_SUFFIX := $(COMMON_ANDROID_PACKAGE_SUFFIX)
+LOCAL_MODULE := PixelQualifiedNetworksService
+LOCAL_MODULE_TAGS := optional
+LOCAL_BUILT_MODULE_STEM := package.apk
+LOCAL_SYSTEM_EXT_MODULE := true
+LOCAL_PRIVILEGED_MODULE := true
+LOCAL_MODULE_OWNER := samsung
+LOCAL_MODULE_CLASS := APPS
+LOCAL_SRC_FILES := $(LOCAL_MODULE).apk
+LOCAL_CERTIFICATE := platform
+LOCAL_LICENSE_KINDS := SPDX-license-identifier-Apache-2.0
+LOCAL_LICENSE_CONDITIONS := notice
+LOCAL_NOTICE_FILE := $(LOCAL_PATH)/../COPYRIGHT $(LOCAL_PATH)/../LICENSE
+include $(BUILD_PREBUILT)
+
+include $(CLEAR_VARS)
+LOCAL_MODULE_SUFFIX := $(COMMON_ANDROID_PACKAGE_SUFFIX)
+LOCAL_MODULE := ShannonIms
+LOCAL_MODULE_TAGS := optional
+LOCAL_BUILT_MODULE_STEM := package.apk
+LOCAL_SYSTEM_EXT_MODULE := true
+LOCAL_PRIVILEGED_MODULE := true
+LOCAL_MODULE_OWNER := samsung
+LOCAL_MODULE_CLASS := APPS
+LOCAL_SRC_FILES := $(LOCAL_MODULE).apk
+LOCAL_CERTIFICATE := platform
+LOCAL_LICENSE_KINDS := SPDX-license-identifier-Apache-2.0
+LOCAL_LICENSE_CONDITIONS := notice
+LOCAL_NOTICE_FILE := $(LOCAL_PATH)/../COPYRIGHT $(LOCAL_PATH)/../LICENSE
+include $(BUILD_PREBUILT)
+
+include $(CLEAR_VARS)
+LOCAL_MODULE_SUFFIX := $(COMMON_ANDROID_PACKAGE_SUFFIX)
+LOCAL_MODULE := ShannonRcs
+LOCAL_MODULE_TAGS := optional
+LOCAL_BUILT_MODULE_STEM := package.apk
+LOCAL_SYSTEM_EXT_MODULE := true
+LOCAL_PRIVILEGED_MODULE := true
+LOCAL_MODULE_OWNER := samsung
+LOCAL_MODULE_CLASS := APPS
+LOCAL_SRC_FILES := $(LOCAL_MODULE).apk
+LOCAL_CERTIFICATE := platform
+LOCAL_LICENSE_KINDS := SPDX-license-identifier-Apache-2.0
+LOCAL_LICENSE_CONDITIONS := notice
+LOCAL_NOTICE_FILE := $(LOCAL_PATH)/../COPYRIGHT $(LOCAL_PATH)/../LICENSE
+include $(BUILD_PREBUILT)
+
+include $(CLEAR_VARS)
+LOCAL_MODULE_SUFFIX := $(COMMON_ANDROID_PACKAGE_SUFFIX)
+LOCAL_MODULE := UwbVendorService
+LOCAL_MODULE_TAGS := optional
+LOCAL_BUILT_MODULE_STEM := package.apk
+LOCAL_SYSTEM_EXT_MODULE := true
+LOCAL_PRIVILEGED_MODULE := true
+LOCAL_MODULE_OWNER := qorvo
+LOCAL_MODULE_CLASS := APPS
+LOCAL_SRC_FILES := $(LOCAL_MODULE).apk
+LOCAL_CERTIFICATE := platform
+LOCAL_LICENSE_KINDS := SPDX-license-identifier-Apache-2.0
+LOCAL_LICENSE_CONDITIONS := notice
+LOCAL_NOTICE_FILE := $(LOCAL_PATH)/../COPYRIGHT $(LOCAL_PATH)/../LICENSE
+include $(BUILD_PREBUILT)
+
+endif
diff --git a/self-extractors/google_devices/staging/BoardConfigPartial.mk b/self-extractors/google_devices/staging/BoardConfigPartial.mk
new file mode 100644
index 0000000..4b94e4e
--- /dev/null
+++ b/self-extractors/google_devices/staging/BoardConfigPartial.mk
@@ -0,0 +1,37 @@
+# Copyright 2023 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+BOARD_PREBUILT_VENDORIMAGE := vendor/google_devices/felix/proprietary/vendor.img
+
+BOARD_PREBUILT_VENDOR_DLKMIMAGE := vendor/google_devices/felix/proprietary/vendor_dlkm.img
+
+TARGET_COPY_OUT_VENDOR_DLKM := vendor_dlkm
+
+BOARD_AVB_VBMETA_VENDOR := vendor
+BOARD_AVB_VBMETA_VENDOR_KEY_PATH := external/avb/test/data/testkey_rsa2048.pem
+BOARD_AVB_VBMETA_VENDOR_ALGORITHM := SHA256_RSA2048
+BOARD_AVB_VBMETA_VENDOR_ROLLBACK_INDEX := $(PLATFORM_SECURITY_PATCH_TIMESTAMP)
+BOARD_AVB_VBMETA_VENDOR_ROLLBACK_INDEX_LOCATION := 3
+
+AB_OTA_PARTITIONS += \
+    vbmeta_vendor \
+    vendor \
+    vendor_dlkm \
+
+-include vendor/google/tools/android-info.mk
+ifdef USE_ANDROID_INFO
+  TARGET_BOARD_INFO_FILE := vendor/google_devices/felix/android-info.txt
+endif
+
+VENDOR_BLOBS_LICENSE := vendor/google_devices/felix/LICENSE
diff --git a/self-extractors/google_devices/staging/device-partial.mk b/self-extractors/google_devices/staging/device-partial.mk
new file mode 100644
index 0000000..9c4717f
--- /dev/null
+++ b/self-extractors/google_devices/staging/device-partial.mk
@@ -0,0 +1,33 @@
+# Copyright 2023 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+PRODUCT_SOONG_NAMESPACES += \
+    vendor/google_devices/felix/proprietary \
+
+# AOSP packages required by the blobs
+PRODUCT_PACKAGES := \
+    PixelQualifiedNetworksService \
+    ShannonIms \
+    ShannonRcs \
+    UwbVendorService \
+
+PRODUCT_PACKAGES += \
+    libmediaadaptor \
+
+#  blob(s) necessary for felix hardware
+PRODUCT_COPY_FILES := \
+    vendor/google_devices/felix/proprietary/com.shannon.imsservice.xml:system_ext/etc/permissions/com.shannon.imsservice.xml:samsung \
+    vendor/google_devices/felix/proprietary/com.shannon.rcsservice.xml:system_ext/etc/permissions/com.shannon.rcsservice.xml:samsung \
+    vendor/google_devices/felix/proprietary/privapp-permissions-qorvo.xml:system_ext/etc/permissions/privapp-permissions-qorvo.xml:qorvo \
+
diff --git a/self-extractors/root/android-info.txt b/self-extractors/root/android-info.txt
new file mode 100644
index 0000000..662e6cb
--- /dev/null
+++ b/self-extractors/root/android-info.txt
@@ -0,0 +1,8 @@
+require board=felix
+require partition-exists=vendor_kernel_boot
+
+require version-bootloader=felix-1.0-9477737
+
+
+
+require version-baseband=g5300n-230112-230118-B-9502391
diff --git a/self-extractors/root/proprietary/BoardConfigVendor.mk b/self-extractors/root/proprietary/BoardConfigVendor.mk
new file mode 100644
index 0000000..669c0fc
--- /dev/null
+++ b/self-extractors/root/proprietary/BoardConfigVendor.mk
@@ -0,0 +1,15 @@
+# Copyright 2023 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+-include vendor/google_devices/felix/BoardConfigPartial.mk
diff --git a/self-extractors/root/proprietary/device-vendor.mk b/self-extractors/root/proprietary/device-vendor.mk
new file mode 100644
index 0000000..3b79afb
--- /dev/null
+++ b/self-extractors/root/proprietary/device-vendor.mk
@@ -0,0 +1,15 @@
+# Copyright 2023 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+$(call inherit-product-if-exists, vendor/google_devices/felix/device-partial.mk)
diff --git a/sensors/Android.mk b/sensors/Android.mk
deleted file mode 100644
index 4417bc4..0000000
--- a/sensors/Android.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# Copyright (C) 2009 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-LOCAL_PATH := $(call my-dir)
-
-# HAL module implemenation stored in
-# hw/<SENSORS_HARDWARE_MODULE_ID>.<ro.hardware>.so
-include $(CLEAR_VARS)
-
-LOCAL_MODULE_RELATIVE_PATH := hw
-LOCAL_SHARED_LIBRARIES := liblog libcutils libhardware
-LOCAL_SRC_FILES := sensors_dummy.c
-LOCAL_MODULE := sensors.felix
-LOCAL_LICENSE_KINDS := SPDX-license-identifier-Apache-2.0
-LOCAL_LICENSE_CONDITIONS := notice
-LOCAL_NOTICE_FILE := $(LOCAL_PATH)/../NOTICE
-LOCAL_PROPRIETARY_MODULE := true
-
-include $(BUILD_SHARED_LIBRARY)
diff --git a/sensors/sensors_dummy.c b/sensors/sensors_dummy.c
deleted file mode 100644
index b1edd56..0000000
--- a/sensors/sensors_dummy.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * Copyright (C) 2009 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* this implements a sensors hardware library for the Android emulator.
- * the following code should be built as a shared library that will be
- * placed into /system/lib/hw/sensors.goldfish.so
- *
- * it will be loaded by the code in hardware/libhardware/hardware.c
- * which is itself called from com_android_server_SensorService.cpp
- */
-
-#define  SENSORS_SERVICE_NAME "sensors"
-
-#define LOG_TAG "Dummy_Sensors"
-
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <string.h>
-#include <log/log.h>
-#include <cutils/sockets.h>
-#include <hardware/sensors.h>
-#include <pthread.h>
-
-#if 0
-#define  D(...)  ALOGD(__VA_ARGS__)
-#else
-#define  D(...)  ((void)0)
-#endif
-
-#define  E(...)  ALOGE(__VA_ARGS__)
-
-/** SENSOR IDS AND NAMES
- **/
-
-#define MAX_NUM_SENSORS 8
-
-#define SUPPORTED_SENSORS  ((1<<MAX_NUM_SENSORS)-1)
-
-#define  ID_BASE           SENSORS_HANDLE_BASE
-#define  ID_ACCELERATION   (ID_BASE+0)
-#define  ID_MAGNETIC_FIELD (ID_BASE+1)
-#define  ID_ORIENTATION    (ID_BASE+2)
-#define  ID_TEMPERATURE    (ID_BASE+3)
-#define  ID_PROXIMITY      (ID_BASE+4)
-#define  ID_LIGHT          (ID_BASE+5)
-#define  ID_PRESSURE       (ID_BASE+6)
-#define  ID_HUMIDITY       (ID_BASE+7)
-
-#define  SENSORS_ACCELERATION    (1 << ID_ACCELERATION)
-#define  SENSORS_MAGNETIC_FIELD  (1 << ID_MAGNETIC_FIELD)
-#define  SENSORS_ORIENTATION     (1 << ID_ORIENTATION)
-#define  SENSORS_TEMPERATURE     (1 << ID_TEMPERATURE)
-#define  SENSORS_PROXIMITY       (1 << ID_PROXIMITY)
-#define  SENSORS_LIGHT           (1 << ID_LIGHT)
-#define  SENSORS_PRESSURE        (1 << ID_PRESSURE)
-#define  SENSORS_HUMIDITY        (1 << ID_HUMIDITY)
-
-#define  ID_CHECK(x)  ((unsigned)((x) - ID_BASE) < MAX_NUM_SENSORS)
-
-#define  SENSORS_LIST  \
-    SENSOR_(ACCELERATION,"acceleration") \
-    SENSOR_(MAGNETIC_FIELD,"magnetic-field") \
-    SENSOR_(ORIENTATION,"orientation") \
-    SENSOR_(TEMPERATURE,"temperature") \
-    SENSOR_(PROXIMITY,"proximity") \
-    SENSOR_(LIGHT, "light") \
-    SENSOR_(PRESSURE, "pressure") \
-    SENSOR_(HUMIDITY, "humidity")
-
-static const struct {
-    const char*  name;
-    int          id; } _sensorIds[MAX_NUM_SENSORS] =
-{
-#define SENSOR_(x,y)  { y, ID_##x },
-    SENSORS_LIST
-#undef  SENSOR_
-};
-
-static const char*
-_sensorIdToName( int  id )
-{
-    int  nn;
-    for (nn = 0; nn < MAX_NUM_SENSORS; nn++)
-        if (id == _sensorIds[nn].id)
-            return _sensorIds[nn].name;
-    return "<UNKNOWN>";
-}
-
-static int
-_sensorIdFromName( const char*  name )
-{
-    int  nn;
-
-    if (name == NULL)
-        return -1;
-
-    for (nn = 0; nn < MAX_NUM_SENSORS; nn++)
-        if (!strcmp(name, _sensorIds[nn].name))
-            return _sensorIds[nn].id;
-
-    return -1;
-}
-
-/* return the current time in nanoseconds */
-static int64_t now_ns(void) {
-    struct timespec  ts;
-    clock_gettime(CLOCK_MONOTONIC, &ts);
-    return (int64_t)ts.tv_sec * 1000000000 + ts.tv_nsec;
-}
-
-/** SENSORS POLL DEVICE
- **
- ** This one is used to read sensor data from the hardware.
- ** We implement this by simply reading the data from the
- ** emulator through the QEMUD channel.
- **/
-
-typedef struct SensorDevice {
-    struct sensors_poll_device_1  device;
-    sensors_event_t               sensors[MAX_NUM_SENSORS];
-    uint32_t                      pendingSensors;
-    int64_t                       timeStart;
-    int64_t                       timeOffset;
-    uint32_t                      active_sensors;
-    int                           fd;
-    pthread_mutex_t               lock;
-} SensorDevice;
-
-/* Grab the file descriptor to the emulator's sensors service pipe.
- * This function returns a file descriptor on success, or -errno on
- * failure, and assumes the SensorDevice instance's lock is held.
- *
- * This is needed because set_delay(), poll() and activate() can be called
- * from different threads, and poll() is blocking.
- *
- * 1) On a first thread, de-activate() all sensors first, then call poll(),
- *    which results in the thread blocking.
- *
- * 2) On a second thread, slightly later, call set_delay() then activate()
- *    to enable the acceleration sensor.
- *
- * The system expects this to unblock the first thread which will receive
- * new sensor events after the activate() call in 2).
- *
- * This cannot work if both threads don't use the same connection.
- *
- * TODO(digit): This protocol is brittle, implement another control channel
- *              for set_delay()/activate()/batch() when supporting HAL 1.3
- */
-static int sensor_device_get_fd_locked(SensorDevice* dev) {
-    /* Create connection to service on first call */
-    if (dev->fd < 0) {
-	    int ret = -errno;
-	    E("%s: Could not open connection to service: %s", __FUNCTION__,
-	    		    strerror(-ret));
-	    return ret;
-    }
-    return dev->fd;
-}
-
-/* Pick up one pending sensor event. On success, this returns the sensor
- * id, and sets |*event| accordingly. On failure, i.e. if there are no
- * pending events, return -EINVAL.
- *
- * Note: The device's lock must be acquired.
- */
-static int sensor_device_pick_pending_event_locked(SensorDevice* d,
-                                                   sensors_event_t*  event)
-{
-    uint32_t mask = SUPPORTED_SENSORS & d->pendingSensors;
-
-    if (mask) {
-        uint32_t i = 31 - __builtin_clz(mask);
-
-	pthread_mutex_lock(&d->lock);
-        d->pendingSensors &= ~(1U << i);
-        *event = d->sensors[i];
-        event->sensor = i;
-        event->version = sizeof(*event);
-	pthread_mutex_unlock(&d->lock);
-        D("%s: %d [%f, %f, %f]", __FUNCTION__,
-                i,
-                event->data[0],
-                event->data[1],
-                event->data[2]);
-        return i;
-    }
-    E("No sensor to return!!! pendingSensors=0x%08x", d->pendingSensors);
-    // we may end-up in a busy loop, slow things down, just in case.
-    usleep(1000);
-    return -EINVAL;
-}
-
-static int sensor_device_close(struct hw_device_t* dev0)
-{
-    SensorDevice* dev = (void*)dev0;
-    // Assume that there are no other threads blocked on poll()
-    if (dev->fd >= 0) {
-        close(dev->fd);
-        dev->fd = -1;
-    }
-    pthread_mutex_destroy(&dev->lock);
-    free(dev);
-    return 0;
-}
-
-/* Return an array of sensor data. This function blocks until there is sensor
- * related events to report. On success, it will write the events into the
- * |data| array, which contains |count| items. The function returns the number
- * of events written into the array, which shall never be greater than |count|.
- * On error, return -errno code.
- *
- * Note that according to the sensor HAL [1], it shall never return 0!
- *
- * [1] http://source.android.com/devices/sensors/hal-interface.html
- */
-static int sensor_device_poll(struct sensors_poll_device_t *dev0,
-                              sensors_event_t* data, int count)
-{
-    return -EIO;
-}
-
-static int sensor_device_activate(struct sensors_poll_device_t *dev0,
-                                  int handle,
-                                  int enabled)
-{
-    SensorDevice* dev = (void*)dev0;
-
-    D("%s: handle=%s (%d) enabled=%d", __FUNCTION__,
-        _sensorIdToName(handle), handle, enabled);
-
-    /* Sanity check */
-    if (!ID_CHECK(handle)) {
-        E("%s: bad handle ID", __FUNCTION__);
-        return -EINVAL;
-    }
-
-    /* Exit early if sensor is already enabled/disabled. */
-    uint32_t mask = (1U << handle);
-    uint32_t sensors = enabled ? mask : 0;
-
-    pthread_mutex_lock(&dev->lock);
-
-    uint32_t active = dev->active_sensors;
-    uint32_t new_sensors = (active & ~mask) | (sensors & mask);
-    uint32_t changed = active ^ new_sensors;
-
-    if (changed)
-	    dev->active_sensors = new_sensors;
-
-    pthread_mutex_unlock(&dev->lock);
-    return 0;
-}
-
-static int sensor_device_default_flush(
-        struct sensors_poll_device_1* dev0,
-        int handle) {
-
-    SensorDevice* dev = (void*)dev0;
-
-    D("%s: handle=%s (%d)", __FUNCTION__,
-        _sensorIdToName(handle), handle);
-
-    /* Sanity check */
-    if (!ID_CHECK(handle)) {
-        E("%s: bad handle ID", __FUNCTION__);
-        return -EINVAL;
-    }
-
-    pthread_mutex_lock(&dev->lock);
-    dev->sensors[handle].version = META_DATA_VERSION;
-    dev->sensors[handle].type = SENSOR_TYPE_META_DATA;
-    dev->sensors[handle].sensor = 0;
-    dev->sensors[handle].timestamp = 0;
-    dev->sensors[handle].meta_data.what = META_DATA_FLUSH_COMPLETE;
-    dev->pendingSensors |= (1U << handle);
-    pthread_mutex_unlock(&dev->lock);
-
-    return 0;
-}
-
-static int sensor_device_set_delay(struct sensors_poll_device_t *dev0,
-                                   int handle __unused,
-                                   int64_t ns)
-{
-    return 0;
-}
-
-static int sensor_device_default_batch(
-     struct sensors_poll_device_1* dev,
-     int sensor_handle,
-     int flags,
-     int64_t sampling_period_ns,
-     int64_t max_report_latency_ns) {
-    return sensor_device_set_delay(dev, sensor_handle, sampling_period_ns);
-}
-
-/** MODULE REGISTRATION SUPPORT
- **
- ** This is required so that hardware/libhardware/hardware.c
- ** will dlopen() this library appropriately.
- **/
-
-/*
- * the following is the list of all supported sensors.
- * this table is used to build sSensorList declared below
- * according to which hardware sensors are reported as
- * available from the emulator (see get_sensors_list below)
- *
- * note: numerical values for maxRange/resolution/power for
- *       all sensors but light, pressure and humidity were
- *       taken from the reference AK8976A implementation
- */
-static const struct sensor_t sSensorListInit[] = {
-        { .name       = "Accelerometer",
-          .vendor     = "The Android Open Source Project",
-          .version    = 1,
-          .handle     = ID_ACCELERATION,
-          .type       = SENSOR_TYPE_ACCELEROMETER,
-          .maxRange   = 2.8f,
-          .resolution = 1.0f/4032.0f,
-          .power      = 3.0f,
-          .minDelay   = 10000,
-          .maxDelay   = 60 * 1000 * 1000,
-          .fifoReservedEventCount = 0,
-          .fifoMaxEventCount =   0,
-          .stringType =         0,
-          .requiredPermission = 0,
-          .flags = SENSOR_FLAG_CONTINUOUS_MODE,
-          .reserved   = {}
-        },
-};
-
-static struct sensor_t  sSensorList[1];
-
-static int sensors__get_sensors_list(struct sensors_module_t* module __unused,
-        struct sensor_t const** list)
-{
-    *list = sSensorList;
-
-    return 0;
-}
-
-static int
-open_sensors(const struct hw_module_t* module,
-             const char*               name,
-             struct hw_device_t*      *device)
-{
-    int  status = -EINVAL;
-
-    D("%s: name=%s", __FUNCTION__, name);
-
-    if (!strcmp(name, SENSORS_HARDWARE_POLL)) {
-        SensorDevice *dev = malloc(sizeof(*dev));
-
-        memset(dev, 0, sizeof(*dev));
-
-        dev->device.common.tag     = HARDWARE_DEVICE_TAG;
-        dev->device.common.version = SENSORS_DEVICE_API_VERSION_1_3;
-        dev->device.common.module  = (struct hw_module_t*) module;
-        dev->device.common.close   = sensor_device_close;
-        dev->device.poll           = sensor_device_poll;
-        dev->device.activate       = sensor_device_activate;
-        dev->device.setDelay       = sensor_device_set_delay;
-
-        // Version 1.3-specific functions
-        dev->device.batch       = sensor_device_default_batch;
-        dev->device.flush       = sensor_device_default_flush;
-
-        dev->fd = -1;
-        pthread_mutex_init(&dev->lock, NULL);
-
-        *device = &dev->device.common;
-        status  = 0;
-    }
-    return status;
-}
-
-
-static struct hw_module_methods_t sensors_module_methods = {
-    .open = open_sensors
-};
-
-struct sensors_module_t HAL_MODULE_INFO_SYM = {
-    .common = {
-        .tag = HARDWARE_MODULE_TAG,
-        .version_major = 1,
-        .version_minor = 0,
-        .id = SENSORS_HARDWARE_MODULE_ID,
-        .name = "Dummy SENSORS Module",
-        .author = "The Android Open Source Project",
-        .methods = &sensors_module_methods,
-    },
-    .get_sensors_list = sensors__get_sensors_list
-};
diff --git a/thermal_info_config_charge_felix.json b/thermal_info_config_charge_felix.json
new file mode 100644
index 0000000..ceb9181
--- /dev/null
+++ b/thermal_info_config_charge_felix.json
@@ -0,0 +1,331 @@
+{
+    "Sensors":[
+        {
+            "Name":"neutral_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/neutral_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"quiet_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"skin_therm",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 32.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/skin_therm/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"usb_pwr_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"usb_pwr_therm2",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 40.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm2/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"inner_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/inner_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"outer_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/outer_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"gnss_tcxo_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/gnss_tcxo_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"inner-disp",
+            "Type":"UNKNOWN",
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[-1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"CLOSE-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.259, 0.652, -0.161, 0.03],
+            "Offset":8450,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.05, 0.05, 1.25, 0.15, -0.6],
+            "Offset":270,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2"],
+            "Coefficient":[0.4, 1.65, -1.2, 0.6, -0.55],
+            "Offset":2350,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "outer_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-1.3, 1.05, 0.65, 0.15, 1, -0.05, -0.5],
+            "Offset":120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB6",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-0.45, -1.2, -0.8, 0.65, 2.5, 0.2],
+            "Offset":1820,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["CLOSE-SUB2", "CLOSE-SUB3", "CLOSE-SUB4", "CLOSE-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["CLOSE-SUB-MAX", "IS_OPEN"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB1",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm"],
+            "Coefficient":[-0.05, 0.3, 0.3, 0.35],
+            "Offset":3740,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.385, 0.075, 0.348, 0.302],
+            "Offset":-4950,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-2, 1.4, 1.4, -0.4, 0.25, 0.25],
+            "Offset":-4120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.3, 1.8, 0.55, 0.4, -1.2, -0.15, -0.8],
+            "Offset":-540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm"],
+            "Coefficient":[0.15, 1.05, -0.65, 1, -0.55],
+            "Offset":3540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["OPEN-SUB1", "OPEN-SUB2", "OPEN-SUB3", "OPEN-SUB4", "OPEN-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["OPEN-SUB-MAX", "IS_CLOSE"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CHARGE",
+            "Type":"UNKNOWN",
+            "Version":"0.3",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN-CLOSE", "VIRTUAL-SKIN-OPEN"],
+            "Coefficient":[1.0, 1.0],
+            "HotThreshold":["NAN", 25.0, 39.0, 41.0, 45.0, 46.5, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.9, 1.4, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":60000,
+            "PassiveDelay":60000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", 1000, "NAN", "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", 30, "NAN", "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", 40, "NAN", "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", 1500, "NAN", "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", 3000, "NAN", "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", 10000, "NAN", "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", 14, "NAN", "NAN", "NAN", "NAN"],
+                "I_Default":1500
+            },
+            "ExcludedPowerInfo": [
+                {
+                    "PowerRail": "PARTIAL_SYSTEM_POWER",
+                    "PowerWeight": [1.6, 1.6, 1.6, 1.6, 1.6, 1.6, 1.6]
+                }
+            ],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "chg_mdis",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "CdevCeiling": [0, 10, 11, 11, 12, 12, 12],
+                    "LimitInfo": [0, 0, 0, 0, 0, 12, 12]
+                }
+            ]
+        },
+        {
+            "Name":"USB2-MINUS-USB",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor": "usb_pwr_therm2",
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["usb_pwr_therm2", "usb_pwr_therm"],
+            "Coefficient":[1.0, -1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-USB-THROTTLING",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "usb_pwr_therm2",
+            "Combination":["usb_pwr_therm2", "USB2-MINUS-USB"],
+            "Coefficient":[40000, 10000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "2.0", "NAN", "NAN"],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "usbc-port",
+                    "LimitInfo": [0, 0, 0, 0, 1, 1, 1]
+                }
+            ],
+            "Multiplier":1,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        }
+    ],
+    "CoolingDevices":[
+        {
+            "Name":"chg_mdis",
+            "Type":"BATTERY",
+            "State2Power":[4122, 3623, 3308, 2824, 2524, 2241, 1864, 1635, 1319, 932, 632, 344, 0]
+        },
+        {
+            "Name":"usbc-port",
+            "Type":"BATTERY"
+        }
+    ],
+    "PowerRails":[
+        {
+            "Name":"PARTIAL_SYSTEM_POWER",
+            "VirtualRails":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["VSYS_PWR_MMWAVE", "VSYS_PWR_MODEM", "VSYS_PWR_RFFE", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S8M_LLDO2",
+                    "S10M_VDD_TPU", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "VSYS_PWR_CAM", "S1S_VDD_CAM","S2S_VDD_G3D", "S4S_VDD2H_MEM", "S8S_VDD_G3D_L2", "L2S_PLL_MIPI_UFS"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0],
+            "PowerSampleDelay":60000,
+            "PowerSampleCount":1
+        }
+    ]
+}
diff --git a/thermal_info_config_felix.json b/thermal_info_config_felix.json
new file mode 100644
index 0000000..6bbb5b0
--- /dev/null
+++ b/thermal_info_config_felix.json
@@ -0,0 +1,990 @@
+{
+    "Sensors":[
+        {
+            "Name":"battery",
+            "Type":"BATTERY",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"neutral_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/neutral_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"quiet_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"skin_therm",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 32.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/skin_therm/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"usb_pwr_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"usb_pwr_therm2",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 40.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm2/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"inner_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/inner_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"outer_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/outer_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"gnss_tcxo_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/gnss_tcxo_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"inner-disp",
+            "Type":"UNKNOWN",
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[-1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"CLOSE-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.259, 0.652, -0.161, 0.03],
+            "Offset":8450,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.05, 0.05, 1.25, 0.15, -0.6],
+            "Offset":270,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2"],
+            "Coefficient":[0.4, 1.65, -1.2, 0.6, -0.55],
+            "Offset":2350,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "outer_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-1.3, 1.05, 0.65, 0.15, 1, -0.05, -0.5],
+            "Offset":120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB6",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-0.45, -1.2, -0.8, 0.65, 2.5, 0.2],
+            "Offset":1820,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["CLOSE-SUB2", "CLOSE-SUB3", "CLOSE-SUB4", "CLOSE-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["CLOSE-SUB-MAX", "IS_OPEN"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB1",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm"],
+            "Coefficient":[-0.05, 0.3, 0.3, 0.35],
+            "Offset":3740,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.385, 0.075, 0.348, 0.302],
+            "Offset":-4950,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-2, 1.4, 1.4, -0.4, 0.25, 0.25],
+            "Offset":-4120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.3, 1.8, 0.55, 0.4, -1.2, -0.15, -0.8],
+            "Offset":-540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm"],
+            "Coefficient":[0.15, 1.05, -0.65, 1, -0.55],
+            "Offset":3540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["OPEN-SUB1", "OPEN-SUB2", "OPEN-SUB3", "OPEN-SUB4", "OPEN-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["OPEN-SUB-MAX", "IS_CLOSE"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN",
+            "Type":"SKIN",
+            "Version":"0.5",
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN-CLOSE", "VIRTUAL-SKIN-OPEN"],
+            "Coefficient":[1.0, 1.0],
+            "HotThreshold":["NAN", 39.0, 43.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 2, 3, 4, 5, 5, 5]
+                },
+                {
+                    "CdevRequest": "gxp-cooling",
+                    "LimitInfo": [0, 0, 0, 0, 0, 99, 99]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-HINT",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 43.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "SendPowerHint":true,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"cellular-emergency",
+            "Type":"POWER_AMPLIFIER",
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 52.5, "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 0.0, 1.9, 0.0],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "SendCallback":true
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CPU",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 39.0, 41.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", "NAN", 400, "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", "NAN", 400, "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", "NAN", 10000, "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", "NAN", 2, "NAN", "NAN", "NAN"]
+            },
+            "ExcludedPowerInfo": [
+                {
+                    "PowerRail": "VSYS_PWR_MODEM",
+                    "PowerWeight": [0.3, 0.3, 0.3, 0.3, 0.3, 0.3, 0.3]
+                }
+            ],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S4M_VDD_CPUCL0",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-1",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S3M_VDD_CPUCL1",
+                    "CdevCeiling": [0, 12, 12, 12, 12, 14, 14],
+                    "LimitInfo": [0, 0, 0, 0, 12, 14, 14]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "BindedPowerRail": "S2M_VDD_CPUCL2",
+                    "CdevCeiling": [0, 15, 15, 15, 15, 17, 17],
+                    "LimitInfo": [0, 0, 0, 0, 15, 17, 17]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CPU-GPU",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 43.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", "NAN", 700, "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", "NAN", 3900, "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", "NAN", 2, "NAN", "NAN", "NAN"]
+            },
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S4M_VDD_CPUCL0",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-1",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S3M_VDD_CPUCL1",
+                    "CdevCeiling": [0, 12, 12, 12, 12, 14, 14],
+                    "LimitInfo": [0, 0, 0, 0, 12, 14, 14]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "BindedPowerRail": "S2M_VDD_CPUCL2",
+                    "CdevCeiling": [0, 15, 15, 15, 15, 17, 17],
+                    "LimitInfo": [0, 0, 0, 0, 15, 17, 17]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S2S_VDD_G3D",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CHARGE",
+            "Type":"UNKNOWN",
+            "Version":"0.3",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 25.0, 39.0, 41.0, 45.0, 46.5, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.9, 1.4, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":60000,
+            "PassiveDelay":60000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", 1000, "NAN", "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", 30, "NAN", "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", 40, "NAN", "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", 1500, "NAN", "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", 3000, "NAN", "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", 10000, "NAN", "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", 14, "NAN", "NAN", "NAN", "NAN"],
+                "I_Default":1500
+            },
+            "ExcludedPowerInfo": [
+                {
+                    "PowerRail": "PARTIAL_SYSTEM_POWER",
+                    "PowerWeight": [1.6, 1.6, 1.6, 1.6, 1.6, 1.6, 1.6]
+                }
+            ],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "chg_mdis",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "CdevCeiling": [0, 10, 11, 11, 12, 12, 12],
+                    "LimitInfo": [0, 0, 0, 0, 0, 12, 12]
+                }
+            ]
+        },
+        {
+            "Name":"USB2-MINUS-USB",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor": "usb_pwr_therm2",
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["usb_pwr_therm2", "usb_pwr_therm"],
+            "Coefficient":[1.0, -1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-USB-THROTTLING",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "usb_pwr_therm2",
+            "Combination":["usb_pwr_therm2", "USB2-MINUS-USB"],
+            "Coefficient":[40000, 10000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "2.0", "NAN", "NAN"],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "usbc-port",
+                    "LimitInfo": [0, 0, 0, 0, 1, 1, 1]
+                }
+            ],
+            "Multiplier":1,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"VIRTUAL-USB-UI",
+            "Type":"USB_PORT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "usb_pwr_therm2",
+            "Combination":["usb_pwr_therm2", "USB2-MINUS-USB"],
+            "Coefficient":[40000, 13000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "2.0", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"LEFT-INNER-DISPLAY",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["outer_disp_therm"],
+            "Coefficient":[1.56],
+            "Offset":-14540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"RIGHT-INNER-DISPLAY",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm"],
+            "Coefficient":[0.35, -0.2, 0.55, -0.95, 0.35, 0.8],
+            "Offset":3110,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"INNER-DISPLAY-DIFF",
+            "Type":"UNKNOWN",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["LEFT-INNER-DISPLAY", "RIGHT-INNER-DISPLAY"],
+            "Coefficient":[1.0, -1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"LITTLE",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"MID",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"BIG",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"G3D",
+            "Type":"GPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"TPU",
+            "Type":"NPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"battery_cycle",
+            "Type":"BCL_VOLTAGE",
+            "Multiplier":1,
+            "SendCallback":false
+        },
+        {
+            "Name":"critical-battery-cell",
+            "Type":"BCL_VOLTAGE",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "vdroop1",
+            "Combination":["battery", "battery_cycle", "vdroop1"],
+            "Coefficient":[-10000, 400, 1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 3.00, "NAN"],
+            "Multiplier":1,
+            "SendCallback":true
+        },
+        {
+            "Name":"FLASH_LED_REDUCE",
+            "Type":"UNKNOWN",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "vdroop1",
+            "Combination":["battery", "battery_cycle", "vdroop1"],
+            "Coefficient":[-10000, 400, 1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.00, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "SendPowerHint":true
+        },
+        {
+            "Name":"soc",
+            "Type":"BCL_PERCENTAGE",
+            "HotThreshold":["NAN", "NAN", 80, "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":1
+        },
+        {
+            "Name":"BCL_TPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "TriggerSensor": "ocp_tpu",
+            "Combination":["ocp_tpu", "battery"],
+            "Coefficient":[1, -10],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 13000, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_GPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "TriggerSensor": "ocp_gpu",
+            "Combination":["ocp_gpu", "battery"],
+            "Coefficient":[1, -10],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 13000, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 9, 9, 9]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_GPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_gpu", "battery"],
+            "Coefficient":[5000, 12000, -1000 ],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN",  3.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 9, 9, 9]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_TPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_tpu", "battery"],
+            "Coefficient":[5000, 12000, -1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_GPU",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_gpu"],
+            "Coefficient":[5000, 12000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 4, 4, 4]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_TPU",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":[
+                "batoilo",
+                "ocp_tpu"
+            ],
+            "Coefficient":[5000, 12000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 6, 6, 6]
+                }
+            ]
+        },
+        {
+            "Name":"batoilo",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 5000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 5, 5, 5]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_AUDIO_BAACL",
+            "Type":"BCL_VOLTAGE",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "soc",
+            "Combination":["battery", "soc"],
+            "Coefficient":[-10000, 80],
+            "HotThreshold":["NAN", "NAN",  "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true
+        },
+        {
+            "Name":"vdroop1",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 2, 2, 2]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"vdroop2",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1200, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 4, 4, 4]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"smpl_gm",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1100, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"ocp_cpu1",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"ocp_cpu2",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"ocp_tpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"ocp_gpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_cpu2",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_cpu1",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_tpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8500, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"soft_ocp_gpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 9000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        }
+    ],
+    "CoolingDevices":[
+        {
+            "Name":"thermal-cpufreq-0",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote",
+            "State2Power":[516, 456, 392, 296, 264, 216, 184, 140, 100, 68, 28]
+        },
+        {
+            "Name":"thermal-cpufreq-1",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote",
+            "State2Power":[2466, 2166, 1840, 1544, 1260, 1024, 816, 642, 538, 410, 342, 276, 224, 162, 104]
+        },
+        {
+            "Name":"thermal-cpufreq-2",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote",
+            "State2Power":[4920, 4614, 4092, 3684, 3198, 2820, 2354, 2184, 1862, 1476, 1338, 1110, 928, 738, 552, 450, 362, 188]
+        },
+        {
+            "Name":"thermal-gpufreq-0",
+            "Type":"GPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote",
+            "State2Power":[1925, 1528, 1258, 928, 795, 703, 573, 481, 396, 314, 236]
+        },
+        {
+            "Name":"chg_mdis",
+            "Type":"BATTERY",
+            "State2Power":[4122, 3623, 3308, 2824, 2524, 2241, 1864, 1635, 1319, 932, 632, 344, 0]
+        },
+        {
+            "Name":"usbc-port",
+            "Type":"BATTERY"
+        },
+        {
+            "Name":"tpu_cooling",
+            "Type":"NPU",
+            "WritePath":"/dev/thermal/cdev-by-name/tpu_cooling/user_vote"
+        },
+        {
+            "Name":"gxp-cooling",
+            "Type":"NPU",
+            "WritePath":"/dev/thermal/cdev-by-name/gxp-cooling/user_vote"
+        }
+    ],
+    "PowerRails":[
+        {
+            "Name":"VSYS_PWR_MODEM",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S2M_VDD_CPUCL2",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+
+        },
+        {
+            "Name":"S3M_VDD_CPUCL1",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S4M_VDD_CPUCL0",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S2S_VDD_G3D",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"PARTIAL_SYSTEM_POWER",
+            "VirtualRails":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["VSYS_PWR_MMWAVE", "VSYS_PWR_MODEM", "VSYS_PWR_RFFE", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S8M_LLDO2",
+                    "S10M_VDD_TPU", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "VSYS_PWR_CAM", "S1S_VDD_CAM","S2S_VDD_G3D", "S4S_VDD2H_MEM", "S8S_VDD_G3D_L2", "L2S_PLL_MIPI_UFS"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0],
+            "PowerSampleDelay":60000,
+            "PowerSampleCount":1
+        }
+    ],
+    "Stats": {
+        "Sensors": {
+            "RecordWithDefaultThreshold": ["VIRTUAL-SKIN"],
+            "RecordWithThreshold": [
+                {
+                    "Name": "VIRTUAL-SKIN",
+                    "Thresholds": [31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51]
+                },
+                {
+                    "Name": "VIRTUAL-USB-THROTTLING",
+                    "Thresholds": [2.0]
+                }
+            ]
+        },
+        "CoolingDevices": {
+            "RecordVotePerSensor": {
+                "DefaultThresholdEnableAll": true
+            }
+        }
+    }
+}
diff --git a/thermal_info_config_proactive_skin_felix.json b/thermal_info_config_proactive_skin_felix.json
new file mode 100644
index 0000000..1b7c446
--- /dev/null
+++ b/thermal_info_config_proactive_skin_felix.json
@@ -0,0 +1,970 @@
+{
+    "Sensors":[
+        {
+            "Name":"battery",
+            "Type":"BATTERY",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"neutral_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/neutral_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"quiet_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"skin_therm",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 32.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/skin_therm/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"usb_pwr_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"usb_pwr_therm2",
+            "Type":"UNKNOWN",
+            "HotThreshold":["NAN", 40.0, "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm2/tz_temp",
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"inner_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/inner_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"outer_disp_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/outer_disp_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"gnss_tcxo_therm",
+            "Type":"UNKNOWN",
+            "TempPath":"/dev/thermal/tz-by-name/gnss_tcxo_therm/tz_temp",
+            "Multiplier":0.001
+        },
+        {
+            "Name":"inner-disp",
+            "Type":"UNKNOWN",
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"IS_CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "Combination":["inner-disp"],
+            "Coefficient":[-1.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"CLOSE-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.259, 0.652, -0.161, 0.03],
+            "Offset":8450,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.05, 0.05, 1.25, 0.15, -0.6],
+            "Offset":270,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2"],
+            "Coefficient":[0.4, 1.65, -1.2, 0.6, -0.55],
+            "Offset":2350,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "outer_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-1.3, 1.05, 0.65, 0.15, 1, -0.05, -0.5],
+            "Offset":120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB6",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-0.45, -1.2, -0.8, 0.65, 2.5, 0.2],
+            "Offset":1820,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"CLOSE-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["CLOSE-SUB2", "CLOSE-SUB3", "CLOSE-SUB4", "CLOSE-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CLOSE",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["CLOSE-SUB-MAX", "IS_OPEN"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB1",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm"],
+            "Coefficient":[-0.05, 0.3, 0.3, 0.35],
+            "Offset":3740,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB2",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.385, 0.075, 0.348, 0.302],
+            "Offset":-4950,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB3",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[-2, 1.4, 1.4, -0.4, 0.25, 0.25],
+            "Offset":-4120,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB4",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm", "gnss_tcxo_therm"],
+            "Coefficient":[0.3, 1.8, 0.55, 0.4, -1.2, -0.15, -0.8],
+            "Offset":-540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB5",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm"],
+            "Coefficient":[0.15, 1.05, -0.65, 1, -0.55],
+            "Offset":3540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"OPEN-SUB-MAX",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"MAXIMUM",
+            "Combination":["OPEN-SUB1", "OPEN-SUB2", "OPEN-SUB3", "OPEN-SUB4", "OPEN-SUB5"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN-OPEN",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["OPEN-SUB-MAX", "IS_CLOSE"],
+            "Coefficient":[1.0, -1000000],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-SKIN",
+            "Type":"SKIN",
+            "Version":"0.5",
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN-CLOSE", "VIRTUAL-SKIN-OPEN"],
+            "Coefficient":[1.0, 1.0],
+            "HotThreshold":["NAN", 37.0, 41.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 2, 3, 4, 5, 5, 5]
+                },
+                {
+                    "CdevRequest": "gxp-cooling",
+                    "LimitInfo": [0, 0, 0, 0, 0, 99, 99]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-HINT",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 41.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "SendPowerHint":true,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"cellular-emergency",
+            "Type":"POWER_AMPLIFIER",
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 52.5, "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 0.0, 1.9, 0.0],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "SendCallback":true
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CPU",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 39.0, 41.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", "NAN", 400, "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", "NAN", 400, "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", "NAN", 10000, "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", "NAN", 2, "NAN", "NAN", "NAN"]
+            },
+            "ExcludedPowerInfo": [
+                {
+                    "PowerRail": "VSYS_PWR_MODEM",
+                    "PowerWeight": [0.3, 0.3, 0.3, 0.3, 0.3, 0.3, 0.3]
+                }
+            ],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S4M_VDD_CPUCL0",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-1",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S3M_VDD_CPUCL1",
+                    "CdevCeiling": [0, 12, 12, 12, 12, 14, 14],
+                    "LimitInfo": [0, 0, 0, 0, 12, 14, 14]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "BindedPowerRail": "S2M_VDD_CPUCL2",
+                    "CdevCeiling": [0, 15, 15, 15, 15, 17, 17],
+                    "LimitInfo": [0, 0, 0, 0, 15, 17, 17]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CPU-GPU",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 37.0, 43.0, 45.0, 46.5, 51.0, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":300000,
+            "PassiveDelay":7000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", "NAN", 700, "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", "NAN", 3900, "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", "NAN", 2, "NAN", "NAN", "NAN"]
+            },
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S4M_VDD_CPUCL0",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-1",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S3M_VDD_CPUCL1",
+                    "CdevCeiling": [0, 12, 12, 12, 12, 14, 14],
+                    "LimitInfo": [0, 0, 0, 0, 12, 14, 14]
+                },
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "BindedPowerRail": "S2M_VDD_CPUCL2",
+                    "CdevCeiling": [0, 15, 15, 15, 15, 17, 17],
+                    "LimitInfo": [0, 0, 0, 0, 15, 17, 17]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 1,
+                    "BindedPowerRail": "S2S_VDD_G3D",
+                    "CdevCeiling": [0, 8, 8, 8, 8, 10, 10],
+                    "LimitInfo": [0, 0, 0, 0, 8, 10, 10]
+                }
+            ]
+        },
+        {
+            "Name":"VIRTUAL-SKIN-CHARGE",
+            "Type":"UNKNOWN",
+            "Version":"0.3",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor":"skin_therm",
+            "Formula":"MAXIMUM",
+            "Combination":["VIRTUAL-SKIN"],
+            "Coefficient":[1.0],
+            "HotThreshold":["NAN", 25.0, 39.0, 41.0, 45.0, 46.5, 54.0],
+            "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.9, 1.4, 1.9],
+            "Multiplier":0.001,
+            "PollingDelay":60000,
+            "PassiveDelay":60000,
+            "PIDInfo": {
+                "K_Po":["NAN", "NAN", 1000, "NAN", "NAN", "NAN", "NAN"],
+                "K_Pu":["NAN", "NAN", 30, "NAN", "NAN", "NAN", "NAN"],
+                "K_I":["NAN", "NAN", 40, "NAN", "NAN", "NAN", "NAN"],
+                "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "I_Max":["NAN", "NAN", 1500, "NAN", "NAN", "NAN", "NAN"],
+                "S_Power":["NAN", "NAN", 3000, "NAN", "NAN", "NAN", "NAN"],
+                "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"],
+                "MaxAllocPower":["NAN", "NAN", 10000, "NAN", "NAN", "NAN", "NAN"],
+                "I_Cutoff":["NAN", "NAN", 14, "NAN", "NAN", "NAN", "NAN"],
+                "I_Default":1500
+            },
+            "ExcludedPowerInfo": [
+                {
+                    "PowerRail": "PARTIAL_SYSTEM_POWER",
+                    "PowerWeight": [1.6, 1.6, 1.6, 1.6, 1.6, 1.6, 1.6]
+                }
+            ],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "chg_mdis",
+                    "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1],
+                    "MaxReleaseStep": 1,
+                    "MaxThrottleStep": 2,
+                    "CdevCeiling": [0, 10, 11, 11, 12, 12, 12],
+                    "LimitInfo": [0, 0, 0, 0, 0, 12, 12]
+                }
+            ]
+        },
+        {
+            "Name":"USB2-MINUS-USB",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "TriggerSensor": "usb_pwr_therm2",
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["usb_pwr_therm2", "usb_pwr_therm"],
+            "Coefficient":[1.0, -1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"VIRTUAL-USB-THROTTLING",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "usb_pwr_therm2",
+            "Combination":["usb_pwr_therm2", "USB2-MINUS-USB"],
+            "Coefficient":[40000, 10000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "2.0", "NAN", "NAN"],
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "usbc-port",
+                    "LimitInfo": [0, 0, 0, 0, 1, 1, 1]
+                }
+            ],
+            "Multiplier":1,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"VIRTUAL-USB-UI",
+            "Type":"USB_PORT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "usb_pwr_therm2",
+            "Combination":["usb_pwr_therm2", "USB2-MINUS-USB"],
+            "Coefficient":[40000, 13000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "2.0", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":300000,
+            "PassiveDelay":7000
+        },
+        {
+            "Name":"LEFT-INNER-DISPLAY",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["outer_disp_therm"],
+            "Coefficient":[1.56],
+            "Offset":-14540,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"RIGHT-INNER-DISPLAY",
+            "Type":"UNKNOWN",
+            "Hidden":true,
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["neutral_therm", "quiet_therm", "skin_therm", "usb_pwr_therm", "usb_pwr_therm2", "inner_disp_therm"],
+            "Coefficient":[0.35, -0.2, 0.55, -0.95, 0.35, 0.8],
+            "Offset":3110,
+            "Multiplier":0.001
+        },
+        {
+            "Name":"INNER-DISPLAY-DIFF",
+            "Type":"UNKNOWN",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["LEFT-INNER-DISPLAY", "RIGHT-INNER-DISPLAY"],
+            "Coefficient":[1.0, -1.0],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"LITTLE",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"MID",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"BIG",
+            "Type":"CPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"G3D",
+            "Type":"GPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"TPU",
+            "Type":"NPU",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":0.001
+        },
+        {
+            "Name":"battery_cycle",
+            "Type":"BCL_VOLTAGE",
+            "Multiplier":1,
+            "SendCallback":false
+        },
+        {
+            "Name":"critical-battery-cell",
+            "Type":"BCL_VOLTAGE",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "vdroop1",
+            "Combination":["battery", "battery_cycle", "vdroop1"],
+            "Coefficient":[-10000, 400, 1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 3.00, "NAN"],
+            "Multiplier":1,
+            "SendCallback":true
+        },
+        {
+            "Name":"FLASH_LED_REDUCE",
+            "Type":"UNKNOWN",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "vdroop1",
+            "Combination":["battery", "battery_cycle", "vdroop1"],
+            "Coefficient":[-10000, 400, 1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.00, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "SendPowerHint":true
+        },
+        {
+            "Name":"soc",
+            "Type":"BCL_PERCENTAGE",
+            "HotThreshold":["NAN", "NAN", 80, "NAN", "NAN", "NAN", "NAN"],
+            "Multiplier":1
+        },
+        {
+            "Name":"BCL_TPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "TriggerSensor": "ocp_tpu",
+            "Combination":["ocp_tpu", "battery"],
+            "Coefficient":[1, -10],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 13000, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_GPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"WEIGHTED_AVG",
+            "TriggerSensor": "ocp_gpu",
+            "Combination":["ocp_gpu", "battery"],
+            "Coefficient":[1, -10],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 13000, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 9, 9, 9]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_GPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_gpu", "battery"],
+            "Coefficient":[5000, 12000, -1000 ],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN",  3.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 9, 9, 9]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_TPU_LOW_TEMP",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_tpu", "battery"],
+            "Coefficient":[5000, 12000, -1000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_GPU",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":["batoilo", "ocp_gpu"],
+            "Coefficient":[5000, 12000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 4, 4, 4]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_BATOILO_TPU",
+            "Type":"BCL_CURRENT",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "batoilo",
+            "Combination":[
+                "batoilo",
+                "ocp_tpu"
+            ],
+            "Coefficient":[5000, 12000],
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 6, 6, 6]
+                }
+            ]
+        },
+        {
+            "Name":"batoilo",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 5000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 5, 5, 5]
+                }
+            ]
+        },
+        {
+            "Name":"BCL_AUDIO_BAACL",
+            "Type":"BCL_VOLTAGE",
+            "VirtualSensor":true,
+            "Formula":"COUNT_THRESHOLD",
+            "TriggerSensor": "soc",
+            "Combination":["battery", "soc"],
+            "Coefficient":[-10000, 80],
+            "HotThreshold":["NAN", "NAN",  "NAN", "NAN", 2.0, "NAN", "NAN"],
+            "Multiplier":1,
+            "SendCallback":true
+        },
+        {
+            "Name":"vdroop1",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 2, 2, 2]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"vdroop2",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1200, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 4, 4, 4]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"smpl_gm",
+            "Type":"BCL_VOLTAGE",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1100, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "SendCallback":true,
+            "PollingDelay":0,
+            "PassiveDelay":60000,
+            "BindedCdevInfo": [
+                {
+                    "CdevRequest": "thermal-cpufreq-2",
+                    "LimitInfo": [0, 0, 0, 0, 7, 7, 7]
+                },
+                {
+                    "CdevRequest": "thermal-gpufreq-0",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                },
+                {
+                    "CdevRequest": "tpu_cooling",
+                    "LimitInfo": [0, 0, 0, 0, 3, 3, 3]
+                }
+            ]
+        },
+        {
+            "Name":"ocp_cpu1",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"ocp_cpu2",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"ocp_tpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"ocp_gpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_cpu2",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 12000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_cpu1",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1
+        },
+        {
+            "Name":"soft_ocp_tpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 8500, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        },
+        {
+            "Name":"soft_ocp_gpu",
+            "Type":"BCL_CURRENT",
+            "HotThreshold":["NAN", "NAN", "NAN", "NAN", 9000, "NAN", "NAN"],
+            "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0],
+            "Multiplier":1,
+            "Hidden":true
+        }
+    ],
+    "CoolingDevices":[
+        {
+            "Name":"thermal-cpufreq-0",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote",
+            "State2Power":[516, 456, 392, 296, 264, 216, 184, 140, 100, 68, 28]
+        },
+        {
+            "Name":"thermal-cpufreq-1",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote",
+            "State2Power":[2466, 2166, 1840, 1544, 1260, 1024, 816, 642, 538, 410, 342, 276, 224, 162, 104]
+        },
+        {
+            "Name":"thermal-cpufreq-2",
+            "Type":"CPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote",
+            "State2Power":[4920, 4614, 4092, 3684, 3198, 2820, 2354, 2184, 1862, 1476, 1338, 1110, 928, 738, 552, 450, 362, 188]
+        },
+        {
+            "Name":"thermal-gpufreq-0",
+            "Type":"GPU",
+            "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote",
+            "State2Power":[1925, 1528, 1258, 928, 795, 703, 573, 481, 396, 314, 236]
+        },
+        {
+            "Name":"chg_mdis",
+            "Type":"BATTERY",
+            "State2Power":[4122, 3623, 3308, 2824, 2524, 2241, 1864, 1635, 1319, 932, 632, 344, 0]
+        },
+        {
+            "Name":"usbc-port",
+            "Type":"BATTERY"
+        },
+        {
+            "Name":"tpu_cooling",
+            "Type":"NPU",
+            "WritePath":"/dev/thermal/cdev-by-name/tpu_cooling/user_vote"
+        },
+        {
+            "Name":"gxp-cooling",
+            "Type":"NPU",
+            "WritePath":"/dev/thermal/cdev-by-name/gxp-cooling/user_vote"
+        }
+    ],
+    "PowerRails":[
+        {
+            "Name":"VSYS_PWR_MODEM",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S2M_VDD_CPUCL2",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+
+        },
+        {
+            "Name":"S3M_VDD_CPUCL1",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S4M_VDD_CPUCL0",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"S2S_VDD_G3D",
+            "PowerSampleDelay":7000,
+            "PowerSampleCount":1
+        },
+        {
+            "Name":"PARTIAL_SYSTEM_POWER",
+            "VirtualRails":true,
+            "Formula":"WEIGHTED_AVG",
+            "Combination":["VSYS_PWR_MMWAVE", "VSYS_PWR_MODEM", "VSYS_PWR_RFFE", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S8M_LLDO2",
+                    "S10M_VDD_TPU", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "VSYS_PWR_CAM", "S1S_VDD_CAM","S2S_VDD_G3D", "S4S_VDD2H_MEM", "S8S_VDD_G3D_L2", "L2S_PLL_MIPI_UFS"],
+            "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0],
+            "PowerSampleDelay":60000,
+            "PowerSampleCount":1
+        }
+    ]
+}
diff --git a/uwb/Android.mk b/uwb/Android.mk
new file mode 100644
index 0000000..a7bdf11
--- /dev/null
+++ b/uwb/Android.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (C) 2022 The Android Open-Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# WARNING: Everything listed here will be built on ALL platforms,
+# including x86, the universal, and the SDK.  Modules must be uniquely
+# named (liblights.panda), and must build everywhere, or limit themselves
+# to only building on ARM if they include assembly. Individual makefiles
+# are responsible for having their own logic, for fine-grained control.
+LOCAL_PATH:= $(call my-dir)
+LOCAL_UWB_CAL_DIR=$(LOCAL_PATH)
+DEVICE_UWB_CAL_DIR=$(TARGET_OUT_VENDOR)/etc/uwb
+$(shell ($(LOCAL_UWB_CAL_DIR)/country_conf_gen.sh $(LOCAL_UWB_CAL_DIR) $(DEVICE_UWB_CAL_DIR)))
diff --git a/uwb/UWB-calibration-ce.conf b/uwb/UWB-calibration-ce.conf
new file mode 100644
index 0000000..ddc9fca
--- /dev/null
+++ b/uwb/UWB-calibration-ce.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x34
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x34
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x34
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x34
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x7E7E687E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x34
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x7E7E687E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x34
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x9E9E7C9E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x34
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x9E9E7C9E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x34
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x00
+restricted_channels=0
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration-default.conf b/uwb/UWB-calibration-default.conf
new file mode 100644
index 0000000..f3b70dd
--- /dev/null
+++ b/uwb/UWB-calibration-default.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x28
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x28
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x3E3E303E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x16
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x3E3E303E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x16
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x8E8E748E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x28
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x8E8E748E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x28
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x00
+restricted_channels=0
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration-fcc.conf b/uwb/UWB-calibration-fcc.conf
new file mode 100644
index 0000000..f3b70dd
--- /dev/null
+++ b/uwb/UWB-calibration-fcc.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x28
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x28
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x3E3E303E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x16
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x3E3E303E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x16
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x8E8E748E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x28
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x8E8E748E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x28
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x00
+restricted_channels=0
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration-jp.conf b/uwb/UWB-calibration-jp.conf
new file mode 100644
index 0000000..1612133
--- /dev/null
+++ b/uwb/UWB-calibration-jp.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x01
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x31
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x31
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x5E5E4C5E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x27
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x5E5E4C5E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x27
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x5E5E4C5E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x27
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x5E5E4C5E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x27
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x01
+restricted_channels=0x20
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration-restricted.conf b/uwb/UWB-calibration-restricted.conf
new file mode 100644
index 0000000..1c98823
--- /dev/null
+++ b/uwb/UWB-calibration-restricted.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x28
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x28
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x3E3E303E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x16
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x3E3E303E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x16
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x8E8E748E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x28
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x8E8E748E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x28
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x00
+restricted_channels=0xFFFF
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration-tw.conf b/uwb/UWB-calibration-tw.conf
new file mode 100644
index 0000000..5a348b2
--- /dev/null
+++ b/uwb/UWB-calibration-tw.conf
@@ -0,0 +1,148 @@
+[CCC]version=3
+[CCC]wifi_coex_time_gap=10
+[CCC]ap_coop_mode=1
+[CCC]wifi_coex_min_spacing=0x08
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
+ant0.ch5.prf16.pg_count=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
+ant0.ch5.prf64.pg_count=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
+ant0.ch9.prf16.pg_count=0
+ant0.ch9.prf16.pg_delay=0x28
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
+ant0.ch9.prf64.pg_count=0
+ant0.ch9.prf64.pg_delay=0x28
+ant0.port=0
+ant0.selector_gpio=7
+ant0.selector_gpio_value=0
+ant1.ch5.prf16.ant_delay=16450
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
+ant1.ch5.prf16.pg_count=0
+ant1.ch5.prf16.pg_delay=0x26
+ant1.ch5.prf64.ant_delay=16450
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
+ant1.ch5.prf64.pg_count=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x3E3E303E
+ant1.ch9.prf16.pg_count=0
+ant1.ch9.prf16.pg_delay=0x16
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x3E3E303E
+ant1.ch9.prf64.pg_count=0
+ant1.ch9.prf64.pg_delay=0x16
+ant1.port=0
+ant1.selector_gpio=7
+ant1.selector_gpio_value=1
+ant2.ch5.prf16.ant_delay=16450
+ant2.ch5.prf16.tx_power=0
+ant2.ch5.prf16.pg_count=0
+ant2.ch5.prf16.pg_delay=0
+ant2.ch5.prf64.ant_delay=16450
+ant2.ch5.prf64.tx_power=0
+ant2.ch5.prf64.pg_count=0
+ant2.ch5.prf64.pg_delay=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x8E8E748E
+ant2.ch9.prf16.pg_count=0
+ant2.ch9.prf16.pg_delay=0x28
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x8E8E748E
+ant2.ch9.prf64.pg_count=0
+ant2.ch9.prf64.pg_delay=0x28
+ant2.port=1
+ant2.selector_gpio=6
+ant2.selector_gpio_value=0
+ant3.ch5.prf16.ant_delay=16450
+ant3.ch5.prf16.tx_power=0
+ant3.ch5.prf16.pg_count=0
+ant3.ch5.prf16.pg_delay=0
+ant3.ch5.prf64.ant_delay=16450
+ant3.ch5.prf64.tx_power=0
+ant3.ch5.prf64.pg_count=0
+ant3.ch5.prf64.pg_delay=0
+ant3.ch9.prf16.ant_delay=16450
+ant3.ch9.prf16.tx_power=0
+ant3.ch9.prf16.pg_count=0
+ant3.ch9.prf16.pg_delay=0
+ant3.ch9.prf64.ant_delay=16450
+ant3.ch9.prf64.tx_power=0
+ant3.ch9.prf64.pg_count=0
+ant3.ch9.prf64.pg_delay=0
+ant3.port=1
+ant3.selector_gpio=6
+ant3.selector_gpio_value=1
+ant0.ant1.ch5.pdoa_offset=0
+ant0.ant1.ch9.pdoa_offset=0
+ant0.ant2.ch5.pdoa_offset=0
+ant0.ant2.ch9.pdoa_offset=0
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
+ant0.ant3.ch5.pdoa_offset=0
+ant0.ant3.ch9.pdoa_offset=0
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
+ant2.ant3.ch5.pdoa_offset=0
+ant2.ant3.ch9.pdoa_offset=0
+ch5.pll_locking_code=0
+ch9.pll_locking_code=0
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
+xtal_trim=23
+temperature_reference=85
+smart_tx_power=1
+auto_sleep_margin=20000
+alternate_pulse_shape=0x00
+restricted_channels=0x20
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
+coex_gpio=4
+coex_delay_us=1000
+coex_margin_us=500
+coex_interval_us=2000
diff --git a/uwb/UWB-calibration.conf b/uwb/UWB-calibration.conf
index 155fac7..f3b70dd 100644
--- a/uwb/UWB-calibration.conf
+++ b/uwb/UWB-calibration.conf
@@ -1,52 +1,45 @@
-[CCC]version=2
-[CCC]ant0.ch5.prf64.pdoa_iso_rf2_rf1=0
-[CCC]ant0.ch5.prf64.pdoa_iso_rf1_rf2=0
-[CCC]ant0.ch9.prf64.pdoa_iso_rf2_rf1=0
-[CCC]ant0.ch9.prf64.pdoa_iso_rf1_rf2=0
-[CCC]ant0.ch5.prf64.pdoa_offset=0
-[CCC]ant0.ch9.prf64.pdoa_offset=0
-[CCC]ant0.ch5.prf64.pll_locking_code=0
-[CCC]ant0.ch9.prf64.pll_locking_code=0
-[CCC]id=0
+[CCC]version=3
 [CCC]wifi_coex_time_gap=10
 [CCC]ap_coop_mode=1
-[CCC]antenna_selection=4
 [CCC]wifi_coex_min_spacing=0x08
-ant0.ch5.prf16.ant_delay=16450
-ant0.ch5.prf16.tx_power=0
+[CCC]ch5.antenna_selection=ant0
+[CCC]ch9.antenna_selection=ant2
+[CCC]alternate_pulse_shape=0x00
+ant0.ch5.prf16.ant_delay=16449
+ant0.ch5.prf16.tx_power=0xFFFFD4FF
 ant0.ch5.prf16.pg_count=0
-ant0.ch5.prf16.pg_delay=0
-ant0.ch5.prf64.ant_delay=16450
-ant0.ch5.prf64.tx_power=0
+ant0.ch5.prf16.pg_delay=0x28
+ant0.ch5.prf64.ant_delay=16449
+ant0.ch5.prf64.tx_power=0xFFFFD4FF
 ant0.ch5.prf64.pg_count=0
-ant0.ch5.prf64.pg_delay=0
-ant0.ch9.prf16.ant_delay=16450
-ant0.ch9.prf16.tx_power=0
+ant0.ch5.prf64.pg_delay=0x28
+ant0.ch9.prf16.ant_delay=16451
+ant0.ch9.prf16.tx_power=0xFEFEC0FE
 ant0.ch9.prf16.pg_count=0
-ant0.ch9.prf16.pg_delay=0
-ant0.ch9.prf64.ant_delay=16450
-ant0.ch9.prf64.tx_power=0
+ant0.ch9.prf16.pg_delay=0x28
+ant0.ch9.prf64.ant_delay=16451
+ant0.ch9.prf64.tx_power=0xFEFEC0FE
 ant0.ch9.prf64.pg_count=0
-ant0.ch9.prf64.pg_delay=0
+ant0.ch9.prf64.pg_delay=0x28
 ant0.port=0
 ant0.selector_gpio=7
 ant0.selector_gpio_value=0
 ant1.ch5.prf16.ant_delay=16450
-ant1.ch5.prf16.tx_power=0
+ant1.ch5.prf16.tx_power=0xFFFFFFFF
 ant1.ch5.prf16.pg_count=0
-ant1.ch5.prf16.pg_delay=0
+ant1.ch5.prf16.pg_delay=0x26
 ant1.ch5.prf64.ant_delay=16450
-ant1.ch5.prf64.tx_power=0
+ant1.ch5.prf64.tx_power=0xFFFFFFFF
 ant1.ch5.prf64.pg_count=0
-ant1.ch5.prf64.pg_delay=0
-ant1.ch9.prf16.ant_delay=16450
-ant1.ch9.prf16.tx_power=0
+ant1.ch5.prf64.pg_delay=0x26
+ant1.ch9.prf16.ant_delay=16451
+ant1.ch9.prf16.tx_power=0x3E3E303E
 ant1.ch9.prf16.pg_count=0
-ant1.ch9.prf16.pg_delay=0
-ant1.ch9.prf64.ant_delay=16450
-ant1.ch9.prf64.tx_power=0
+ant1.ch9.prf16.pg_delay=0x16
+ant1.ch9.prf64.ant_delay=16451
+ant1.ch9.prf64.tx_power=0x3E3E303E
 ant1.ch9.prf64.pg_count=0
-ant1.ch9.prf64.pg_delay=0
+ant1.ch9.prf64.pg_delay=0x16
 ant1.port=0
 ant1.selector_gpio=7
 ant1.selector_gpio_value=1
@@ -58,14 +51,14 @@
 ant2.ch5.prf64.tx_power=0
 ant2.ch5.prf64.pg_count=0
 ant2.ch5.prf64.pg_delay=0
-ant2.ch9.prf16.ant_delay=16450
-ant2.ch9.prf16.tx_power=0
+ant2.ch9.prf16.ant_delay=16451
+ant2.ch9.prf16.tx_power=0x8E8E748E
 ant2.ch9.prf16.pg_count=0
-ant2.ch9.prf16.pg_delay=0
-ant2.ch9.prf64.ant_delay=16450
-ant2.ch9.prf64.tx_power=0
+ant2.ch9.prf16.pg_delay=0x28
+ant2.ch9.prf64.ant_delay=16451
+ant2.ch9.prf64.tx_power=0x8E8E748E
 ant2.ch9.prf64.pg_count=0
-ant2.ch9.prf64.pg_delay=0
+ant2.ch9.prf64.pg_delay=0x28
 ant2.port=1
 ant2.selector_gpio=6
 ant2.selector_gpio_value=0
@@ -92,43 +85,63 @@
 ant0.ant1.ch9.pdoa_offset=0
 ant0.ant2.ch5.pdoa_offset=0
 ant0.ant2.ch9.pdoa_offset=0
-ant1.ant2.ch5.pdoa_offset=2173
-ant1.ant2.ch9.pdoa_offset=3555
+ant1.ant2.ch5.pdoa_offset=0
+ant1.ant2.ch9.pdoa_offset=2421
 ant0.ant3.ch5.pdoa_offset=0
 ant0.ant3.ch9.pdoa_offset=0
-ant1.ant3.ch5.pdoa_offset=3845
-ant1.ant3.ch9.pdoa_offset=647
+ant1.ant3.ch5.pdoa_offset=0
+ant1.ant3.ch9.pdoa_offset=-6159
 ant2.ant3.ch5.pdoa_offset=0
 ant2.ant3.ch9.pdoa_offset=0
 ch5.pll_locking_code=0
 ch9.pll_locking_code=0
-ant1.ant2.ch5.pdoa_lut=3d:ea:7b:0a:66:ea:c3:09:a4:ea:0a:09:cd:ea:66:08:0a:eb:ae:07:33:eb:f6:06:48:eb:52:06:71:eb:9a:05:c3:eb:e1:04:e1:ec:29:04:c3:ef:85:03:a4:f4:cd:02:14:f8:14:02:b8:fa:5c:01:8f:fc:b8:00:e1:fe:00:00:48:01:48:ff:85:03:a4:fe:ae:05:ec:fd:00:08:33:fd:d7:09:7b:fc:85:0b:d7:fb:0a:0d:1f:fb:66:0e:66:fa:33:0f:ae:f9:00:10:0a:f9:a4:10:52:f8:1f:11:9a:f7:5c:11:f6:f6:9a:11:3d:f6:ae:11:85:f5
-ant1.ant2.ch9.pdoa_lut=c3:ed:7b:0a:29:ee:c3:09:3d:ee:0a:09:cd:ee:66:08:c3:ef:ae:07:f6:f0:f6:06:3d:f2:52:06:52:f2:9a:05:cd:f2:e1:04:5c:f3:29:04:c3:f3:85:03:b8:f4:cd:02:71:f7:14:02:52:fa:5c:01:85:fd:b8:00:00:00:00:00:0a:01:48:ff:5c:01:a4:fe:14:02:ec:fd:5c:03:33:fd:48:05:7b:fc:b8:06:d7:fb:14:08:1f:fb:33:09:66:fa:ec:09:ae:f9:3d:0a:0a:f9:0a:0b:52:f8:1f:0b:9a:f7:48:0b:f6:f6:85:0b:3d:f6:9a:0b:85:f5
-ant1.ant3.ch5.pdoa_lut=66:ec:7b:0a:e1:ec:c3:09:14:ee:0a:09:d7:ef:66:08:8f:f2:ae:07:00:f6:f6:06:cd:f6:52:06:33:f7:9a:05:d7:f7:e1:04:48:f9:29:04:33:fd:85:03:d7:fd:cd:02:3d:fe:14:02:ec:ff:5c:01:14:00:b8:00:3d:00:00:00:cd:02:48:ff:29:04:a4:fe:a4:04:ec:fd:85:05:33:fd:e1:06:7b:fc:b8:08:d7:fb:14:0a:1f:fb:e1:0a:66:fa:1f:0b:0a:f9:1f:0b:ae:f9:5c:0b:52:f8:c3:0b:9a:f7:52:0c:f6:f6:0a:0d:3d:f6:00:0e:85:f5
-ant1.ant3.ch9.pdoa_lut=0a:ef:7b:0a:c3:ef:c3:09:00:f0:0a:09:14:f0:66:08:7b:f0:ae:07:48:f1:f6:06:00:f2:52:06:c3:f3:9a:05:00:f6:e1:04:d7:f7:29:04:1f:f9:85:03:ae:f9:cd:02:e1:fa:14:02:e1:fc:5c:01:b8:fe:b8:00:c3:ff:00:00:00:02:48:ff:5c:05:a4:fe:52:08:ec:fd:14:0a:33:fd:e1:0a:7b:fc:14:0c:d7:fb:14:0e:1f:fb:1f:0f:66:fa:00:10:ae:f9:b8:10:0a:f9:29:12:52:f8:00:14:9a:f7:7b:16:f6:f6:d7:17:3d:f6:29:18:85:f5
+ant1.ant2.ch5.pdoa_lut=0a:f4:77:0a:d9:f4:c5:09:c1:f5:12:09:df:f5:60:08:7f:f6:ac:07:dd:f6:fa:06:f2:f6:48:06:89:f7:96:05:d1:f7:e3:04:54:f8:2f:04:f0:f8:7d:03:46:fa:cb:02:b0:fb:19:02:23:fd:64:01:a2:fe:b2:00:00:00:00:00:31:01:4e:ff:a6:02:9c:fe:0a:04:e7:fd:52:05:35:fd:73:06:83:fc:cb:07:d1:fb:be:08:1d:fb:f8:09:6a:fa:39:0b:b8:f9:81:0c:06:f9:1b:0d:54:f8:87:0d:a0:f7:a0:0e:ee:f6:06:0f:3b:f6:2d:0f:89:f5
+ant1.ant2.ch9.pdoa_lut=d7:f1:85:f5:66:f2:3d:f6:b8:f2:f6:f6:48:f3:9a:f7:9a:f3:52:f8:00:f4:0a:f9:a4:f4:ae:f9:85:f5:66:fa:b8:f6:1f:fb:ec:f7:d7:fb:ae:f9:7b:fc:33:fb:33:fd:e1:fc:ec:fd:29:fe:a4:fe:e1:fe:48:ff:d7:ff:00:00:b8:00:b8:00:d7:01:5c:01:5c:03:14:02:1f:05:cd:02:52:06:85:03:d7:07:29:04:0a:09:e1:04:3d:0a:9a:05:33:0b:52:06:29:0c:f6:06:c3:0d:ae:07:5c:0f:66:08:1f:11:0a:09:66:12:c3:09:00:14:7b:0a
+ant1.ant3.ch5.pdoa_lut=89:f4:ac:07:a2:f4:60:08:ae:f4:77:0a:0a:f5:12:09:7d:f5:c5:09:8d:f5:fa:06:0a:f7:48:06:9a:f7:96:05:fa:f7:e3:04:68:f8:2f:04:f0:f9:7d:03:fa:fb:cb:02:6d:fd:19:02:2f:fe:64:01:98:fe:b2:00:00:00:00:00:1d:02:4e:ff:2d:02:e7:fd:33:02:9c:fe:0a:03:35:fd:6f:04:83:fc:db:05:d1:fb:85:07:1d:fb:b0:08:6a:fa:06:09:b8:f9:71:09:06:f9:48:0a:54:f8:4e:0b:a0:f7:58:0c:3b:f6:62:0c:ee:f6:c5:0c:89:f5
+ant1.ant3.ch9.pdoa_lut=3d:f2:85:f5:52:f2:3d:f6:cd:f2:f6:f6:e1:f2:9a:f7:0a:f3:52:f8:1f:f3:0a:f9:33:f3:ae:f9:71:f3:66:fa:52:f4:1f:fb:85:f5:d7:fb:9a:f7:7b:fc:0a:f9:33:fd:29:fa:ec:fd:ae:fb:a4:fe:ec:fd:48:ff:1f:ff:00:00:cd:00:b8:00:0a:03:5c:01:8f:04:14:02:b8:06:cd:02:66:08:85:03:3d:0a:29:04:7b:0c:e1:04:0a:0d:9a:05:29:0e:52:06:8f:0e:f6:06:a4:0e:ae:07:b8:0e:66:08:cd:0e:0a:09:33:0f:c3:09:c3:0f:7b:0a
 xtal_trim=23
 temperature_reference=85
 smart_tx_power=1
 auto_sleep_margin=20000
+alternate_pulse_shape=0x00
 restricted_channels=0
-[HAL]aoa_capability=1
-[HAL]ant_sets.ch5.range.rx_ant_set_nonranging = 6
-[HAL]ant_sets.ch5.range.rx_ant_set_ranging = 4
-[HAL]ant_sets.ch5.range.tx_ant_set_nonranging = 0
-[HAL]ant_sets.ch5.range.tx_ant_set_ranging = 0
-[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging = 6
-[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging = 4
-[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging = 0
-[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging = 0
-[HAL]ant_sets.ch9.range.rx_ant_set_nonranging = 6
-[HAL]ant_sets.ch9.range.rx_ant_set_ranging = 4
-[HAL]ant_sets.ch9.range.tx_ant_set_nonranging = 0
-[HAL]ant_sets.ch9.range.tx_ant_set_ranging = 0
-[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging = 6
-[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging = 4
-[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging = 0
-[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging = 0
-[HAL]minimum_system_offset_uwbtime0=300
+[HAL]aoa_restricted_channels=0x20
+[HAL]aoa_capability=2
+[HAL]ant_sets.ch5.range.rx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.rx_ant_set_ranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_nonranging=6
+[HAL]ant_sets.ch5.range.tx_ant_set_ranging=6
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.range.rx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.rx_ant_set_ranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.range.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch5.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch5.elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.elevation.rx_ant_set_nonranging=4
+[HAL]ant_sets.ch9.elevation.rx_ant_set_ranging=4
+[HAL]ant_sets.ch9.elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.elevation.tx_ant_set_ranging=8
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth.rx_ant_set_ranging=3
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth.tx_ant_set_ranging=8
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging=0
+[HAL]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging=0
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth=3
+[HAL]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation=4
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging=8
+[HAL]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging=8
+[HAL]minimum_system_offset_uwbtime0=250
 coex_gpio=4
 coex_delay_us=1000
 coex_margin_us=500
diff --git a/uwb/country_conf_gen.sh b/uwb/country_conf_gen.sh
new file mode 100755
index 0000000..7e398c0
--- /dev/null
+++ b/uwb/country_conf_gen.sh
@@ -0,0 +1,31 @@
+#!/bin/bash
+
+# This script is used to generate uwb conuntry configuration file,
+# and the PRODUCT_COPY_FILES list in uwb.mk based on uwb_country.conf
+# Bug: 196073172, 233619860
+
+count=1
+
+mkdir -p $2
+
+while read line ; do
+    if [[ "$line" =~ ^"*" ]]; then
+        header=${line:1}
+    elif [[ "$line" =~ ^"\"" ]]; then
+        #line=$(echo ${line/,} | tr -d "\"")
+        country[count]=$(echo $line | cut -d ':' -f1 | tr -d "\"")
+        code[count]=$(echo $line | cut -d ':' -f2 | tr -d "\"" | tr -d " ")
+            if [ "$header" = "FCC" ]; then
+                cp $1/UWB-calibration-fcc.conf $2/UWB-calibration-${code[$count]}.conf
+            elif [ "$header" = "CE" ]; then
+                cp $1/UWB-calibration-ce.conf $2/UWB-calibration-${code[$count]}.conf
+            elif [ "$header" = "JP" ]; then
+                cp $1/UWB-calibration-jp.conf $2/UWB-calibration-${code[$count]}.conf
+            elif [ "$header" = "TW" ]; then
+                cp $1/UWB-calibration-tw.conf $2/UWB-calibration-${code[$count]}.conf
+            elif [ "$header" = "Restricted" ]; then
+                cp $1/UWB-calibration-restricted.conf $2/UWB-calibration-${code[$count]}.conf
+            fi
+    fi
+((count++))
+done < $1/uwb_country.conf
diff --git a/uwb/init.uwb.calib.xtal.sh b/uwb/init.uwb.calib.xtal.sh
new file mode 100644
index 0000000..1fcb876
--- /dev/null
+++ b/uwb/init.uwb.calib.xtal.sh
@@ -0,0 +1,26 @@
+#!/vendor/bin/sh
+# only use xtal_trim from factory calibration
+if [ -z "$2" ]
+then
+    echo "usage is $0 input-calibration output_calibration"
+    exit 0
+fi
+OUTPUT_CALIB="$2"
+if [ ! -f "$OUTPUT_CALIB" ]; then
+    touch $OUTPUT_CALIB
+    chmod 0644 $OUTPUT_CALIB
+    file="$1"
+    while IFS=, read -r f1 f2
+    do
+        case $f1 in
+            "UWB_cal_tx_xtal_reg_final_value")
+                if [ $((0x$f2)) -gt 63 ]; then
+                    f2=63
+                fi
+                echo 'xtal_trim=0x'$f2 >> $OUTPUT_CALIB
+                ;;
+        esac
+    done <"$file"
+    exit 0
+fi
+
diff --git a/uwb/uwb_calibration.mk b/uwb/uwb_calibration.mk
index d2340e7..d6c9d0a 100644
--- a/uwb/uwb_calibration.mk
+++ b/uwb/uwb_calibration.mk
@@ -13,9 +13,16 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+# UWB - ultra wide band
+$(call inherit-product-if-exists, vendor/qorvo/uwb/uwb.mk)
+
 LOCAL_UWB_CAL_DIR=device/google/felix/uwb
 
 PRODUCT_COPY_FILES += \
-    $(LOCAL_UWB_CAL_DIR)/UWB-calibration.conf:$(TARGET_COPY_OUT_VENDOR)/etc/UWB-calibration.conf \
-    $(LOCAL_UWB_CAL_DIR)/UWB-calibration.conf:$(TARGET_COPY_OUT_VENDOR)/etc/UWB-calibration-unknown.conf \
-    $(LOCAL_UWB_CAL_DIR)/UWB-calibration.conf:$(TARGET_COPY_OUT_VENDOR)/etc/UWB-calibration-default.conf \
+    $(LOCAL_UWB_CAL_DIR)/UWB-calibration-restricted.conf:$(TARGET_COPY_OUT_VENDOR)/etc/uwb/UWB-calibration-unknown.conf \
+    $(LOCAL_UWB_CAL_DIR)/UWB-calibration-default.conf:$(TARGET_COPY_OUT_VENDOR)/etc/uwb/UWB-calibration-default.conf \
+    $(LOCAL_UWB_CAL_DIR)/UWB-calibration-default.conf:$(TARGET_COPY_OUT_VENDOR)/etc/uwb/UWB-calibration.conf \
+    $(LOCAL_UWB_CAL_DIR)/init.uwb.calib.xtal.sh:$(TARGET_COPY_OUT_VENDOR)/bin/init.uwb.calib.sh \
+
+PRODUCT_COPY_FILES += \
+    frameworks/native/data/etc/android.hardware.uwb.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.uwb.xml
diff --git a/uwb/uwb_country.conf b/uwb/uwb_country.conf
new file mode 100644
index 0000000..93a5e2e
--- /dev/null
+++ b/uwb/uwb_country.conf
@@ -0,0 +1,62 @@
+*FCC
+"United States": "us"
+"Canada": "ca"
+
+*CE
+"Austria": "at"
+"Belgium": "be"
+"Bulgaria": "bg"
+"Croatia": "hr"
+"Cyprus": "cy"
+"Czech Republic": "cz"
+"Denmark": "dk"
+"Estonia": "ee"
+"Finland": "fi"
+"France": "fr"
+"Germany": "de"
+"Greece": "gr"
+"Hungary": "hu"
+"Ireland Republic of (EIRE)": "ie"
+"Italy": "it"
+"Latvia": "lv"
+"Lithuania": "lt"
+"Luxembourg": "lu"
+"Malta": "mt"
+"Netherlands": "nl"
+"Poland": "pl"
+"Portugal": "pt"
+"Romania": "ro"
+"Slovakia": "sk"
+"Slovenia": "si"
+"Spain": "es"
+"Sweden": "se"
+"United Kingdom (Great Britain)": "gb"
+"Northern Ireland": "ni"
+"Iceland": "is"
+"Liechtenstein": "li"
+"Norway": "no"
+"Switzerland": "ch"
+
+*JP
+"Japan": "jp"
+
+*TW
+"Taiwan": "tw"
+
+*Restricted
+"Argentina": "ar"
+"Armenia": "am"
+"Azerbaijan": "az"
+"Belarus": "by"
+"Indonesia": "id"
+"Kazakhstan": "kz"
+"Kyrgyzstan": "kg"
+"Nepal": "np"
+"Pakistan": "pk"
+"Paraguay": "py"
+"Russia": "ru"
+"Solomon Islands": "sb"
+"Tajikistan": "tj"
+"Turkmenistanr": "tm"
+"Ukraine": "ua"
+"Uzbekistan": "uz"
diff --git a/vibrator/Android.bp b/vibrator/Android.bp
new file mode 100644
index 0000000..5d6d481
--- /dev/null
+++ b/vibrator/Android.bp
@@ -0,0 +1,52 @@
+//
+// Copyright (C) 2019 The Android Open Source Project
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package {
+    default_applicable_licenses: ["Android-Apache-2.0"],
+}
+
+cc_defaults {
+    name: "PixelVibratorDefaultsPrivate",
+    relative_install_path: "hw",
+    static_libs: [
+        "PixelVibratorCommonPrivate",
+    ],
+    shared_libs: [
+        "libbase",
+        "libbinder_ndk",
+        "libcutils",
+        "libhardware",
+        "liblog",
+        "libutils",
+    ],
+}
+
+cc_defaults {
+    name: "PixelVibratorBinaryDefaultsPrivate",
+    defaults: ["PixelVibratorDefaultsPrivate"],
+    shared_libs: [
+        "android.hardware.vibrator-V2-ndk",
+    ],
+}
+
+cc_defaults {
+    name: "PixelVibratorTestDefaultsPrivate",
+    defaults: ["PixelVibratorDefaultsPrivate"],
+    static_libs: [
+        "android.hardware.vibrator-V2-ndk",
+    ],
+    test_suites: ["device-tests"],
+    require_root: true,
+}
diff --git a/vibrator/OWNERS b/vibrator/OWNERS
new file mode 100644
index 0000000..859c7e0
--- /dev/null
+++ b/vibrator/OWNERS
@@ -0,0 +1,4 @@
+chrispaulo@google.com
+michaelwr@google.com
+nathankulczak@google.com
+taikuo@google.com
diff --git a/vibrator/common/Android.bp b/vibrator/common/Android.bp
new file mode 100644
index 0000000..c80f07c
--- /dev/null
+++ b/vibrator/common/Android.bp
@@ -0,0 +1,37 @@
+//
+// Copyright (C) 2019 The Android Open Source Project
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package {
+    default_applicable_licenses: ["Android-Apache-2.0"],
+}
+
+cc_library {
+    name: "PixelVibratorCommonPrivate",
+    srcs: [
+        "HardwareBase.cpp",
+    ],
+    shared_libs: [
+        "libbase",
+        "libcutils",
+        "liblog",
+        "libutils",
+    ],
+    cflags: [
+        "-DATRACE_TAG=(ATRACE_TAG_VIBRATOR | ATRACE_TAG_HAL)",
+        "-DLOG_TAG=\"android.hardware.vibrator@1.x-common\"",
+    ],
+    export_include_dirs: ["."],
+    vendor_available: true,
+}
diff --git a/vibrator/common/HardwareBase.cpp b/vibrator/common/HardwareBase.cpp
new file mode 100644
index 0000000..7d61b57
--- /dev/null
+++ b/vibrator/common/HardwareBase.cpp
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2019 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "HardwareBase.h"
+
+#include <cutils/properties.h>
+#include <log/log.h>
+
+#include <fstream>
+#include <sstream>
+
+#include "utils.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+HwApiBase::HwApiBase() {
+    mPathPrefix = std::getenv("HWAPI_PATH_PREFIX") ?: "";
+    if (mPathPrefix.empty()) {
+        ALOGE("Failed get HWAPI path prefix!");
+    }
+}
+
+void HwApiBase::saveName(const std::string &name, const std::ios *stream) {
+    mNames[stream] = name;
+}
+
+bool HwApiBase::has(const std::ios &stream) {
+    return !!stream;
+}
+
+void HwApiBase::debug(int fd) {
+    dprintf(fd, "Kernel:\n");
+
+    for (auto &entry : utils::pathsFromEnv("HWAPI_DEBUG_PATHS", mPathPrefix)) {
+        auto &path = entry.first;
+        auto &stream = entry.second;
+        std::string line;
+
+        dprintf(fd, "  %s:\n", path.c_str());
+        while (std::getline(stream, line)) {
+            dprintf(fd, "    %s\n", line.c_str());
+        }
+    }
+
+    mRecordsMutex.lock();
+    dprintf(fd, "  Records:\n");
+    for (auto &r : mRecords) {
+        if (r == nullptr) {
+            continue;
+        }
+        dprintf(fd, "    %s\n", r->toString(mNames).c_str());
+    }
+    mRecordsMutex.unlock();
+}
+
+HwCalBase::HwCalBase() {
+    std::ifstream calfile;
+    std::ifstream calfile_dual;
+    auto propertyPrefix = std::getenv("PROPERTY_PREFIX");
+
+    if (propertyPrefix != NULL) {
+        mPropertyPrefix = std::string(propertyPrefix);
+    } else {
+        ALOGE("Failed get property prefix!");
+    }
+
+    utils::fileFromEnv("CALIBRATION_FILEPATH", &calfile);
+
+    for (std::string line; std::getline(calfile, line);) {
+        if (line.empty() || line[0] == '#') {
+            continue;
+        }
+        std::istringstream is_line(line);
+        std::string key, value;
+        if (std::getline(is_line, key, ':') && std::getline(is_line, value)) {
+            mCalData[utils::trim(key)] = utils::trim(value);
+        }
+    }
+
+    utils::fileFromEnv("CALIBRATION_FILEPATH_DUAL", &calfile_dual);
+
+    for (std::string line; std::getline(calfile_dual, line);) {
+        if (line.empty() || line[0] == '#') {
+            continue;
+        }
+        std::istringstream is_line(line);
+        std::string key, value;
+        if (std::getline(is_line, key, ':') && std::getline(is_line, value)) {
+            key = utils::trim(key) + "_dual";
+            mCalData[key] = utils::trim(value);
+        }
+    }
+}
+
+void HwCalBase::debug(int fd) {
+    std::ifstream stream;
+    std::string path;
+    std::string line;
+    struct context {
+        HwCalBase *obj;
+        int fd;
+    } context{this, fd};
+
+    dprintf(fd, "Properties:\n");
+
+    property_list(
+            [](const char *key, const char *value, void *cookie) {
+                struct context *context = static_cast<struct context *>(cookie);
+                HwCalBase *obj = context->obj;
+                int fd = context->fd;
+                const std::string expect{obj->mPropertyPrefix};
+                const std::string actual{key, std::min(strlen(key), expect.size())};
+                if (actual == expect) {
+                    dprintf(fd, "  %s:\n", key);
+                    dprintf(fd, "    %s\n", value);
+                }
+            },
+            &context);
+
+    dprintf(fd, "\n");
+
+    dprintf(fd, "Persist:\n");
+
+    utils::fileFromEnv("CALIBRATION_FILEPATH", &stream, &path);
+
+    dprintf(fd, "  %s:\n", path.c_str());
+    while (std::getline(stream, line)) {
+        dprintf(fd, "    %s\n", line.c_str());
+    }
+}
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/common/HardwareBase.h b/vibrator/common/HardwareBase.h
new file mode 100644
index 0000000..448d29c
--- /dev/null
+++ b/vibrator/common/HardwareBase.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2019 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#pragma once
+
+#include <android-base/unique_fd.h>
+#include <log/log.h>
+#include <sys/epoll.h>
+#include <utils/Trace.h>
+
+#include <list>
+#include <map>
+#include <sstream>
+#include <string>
+
+#include "utils.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+using ::android::base::unique_fd;
+
+class HwApiBase {
+  private:
+    using NamesMap = std::map<const std::ios *, std::string>;
+
+    class RecordInterface {
+      public:
+        virtual std::string toString(const NamesMap &names) = 0;
+        virtual ~RecordInterface() {}
+    };
+    template <typename T>
+    class Record : public RecordInterface {
+      public:
+        Record(const char *func, const T &value, const std::ios *stream)
+            : mFunc(func), mValue(value), mStream(stream) {}
+        std::string toString(const NamesMap &names) override;
+
+      private:
+        const char *mFunc;
+        const T mValue;
+        const std::ios *mStream;
+    };
+    using Records = std::list<std::unique_ptr<RecordInterface>>;
+
+    static constexpr uint32_t RECORDS_SIZE = 32;
+
+  public:
+    HwApiBase();
+    void debug(int fd);
+
+  protected:
+    void saveName(const std::string &name, const std::ios *stream);
+    template <typename T>
+    void open(const std::string &name, T *stream);
+    bool has(const std::ios &stream);
+    template <typename T>
+    bool get(T *value, std::istream *stream);
+    template <typename T>
+    bool set(const T &value, std::ostream *stream);
+    template <typename T>
+    bool poll(const T &value, std::istream *stream, const int32_t timeout = -1);
+    template <typename T>
+    void record(const char *func, const T &value, const std::ios *stream);
+
+  private:
+    std::string mPathPrefix;
+    NamesMap mNames;
+    Records mRecords{RECORDS_SIZE};
+    std::mutex mRecordsMutex;
+    std::mutex mIoMutex;
+};
+
+#define HWAPI_RECORD(args...) HwApiBase::record(__FUNCTION__, ##args)
+
+template <typename T>
+void HwApiBase::open(const std::string &name, T *stream) {
+    saveName(name, stream);
+    utils::openNoCreate(mPathPrefix + name, stream);
+}
+
+template <typename T>
+bool HwApiBase::get(T *value, std::istream *stream) {
+    ATRACE_NAME("HwApi::get");
+    std::scoped_lock ioLock{mIoMutex};
+    bool ret;
+    stream->seekg(0);
+    *stream >> *value;
+    if (!(ret = !!*stream)) {
+        ALOGE("Failed to read %s (%d): %s", mNames[stream].c_str(), errno, strerror(errno));
+    }
+    stream->clear();
+    HWAPI_RECORD(*value, stream);
+    return ret;
+}
+
+template <typename T>
+bool HwApiBase::set(const T &value, std::ostream *stream) {
+    ATRACE_NAME("HwApi::set");
+    using utils::operator<<;
+    std::scoped_lock ioLock{mIoMutex};
+    bool ret;
+    *stream << value << std::endl;
+    if (!(ret = !!*stream)) {
+        ALOGE("Failed to write %s (%d): %s", mNames[stream].c_str(), errno, strerror(errno));
+        stream->clear();
+    }
+    HWAPI_RECORD(value, stream);
+    return ret;
+}
+
+template <typename T>
+bool HwApiBase::poll(const T &value, std::istream *stream, const int32_t timeoutMs) {
+    ATRACE_NAME("HwApi::poll");
+    auto path = mPathPrefix + mNames[stream];
+    unique_fd fileFd{::open(path.c_str(), O_RDONLY)};
+    unique_fd epollFd{epoll_create(1)};
+    epoll_event event = {
+            .events = EPOLLPRI | EPOLLET,
+    };
+    T actual;
+    bool ret;
+    int epollRet;
+
+    if (timeoutMs < -1) {
+        ALOGE("Invalid polling timeout!");
+        return false;
+    }
+
+    if (epoll_ctl(epollFd, EPOLL_CTL_ADD, fileFd, &event)) {
+        ALOGE("Failed to poll %s (%d): %s", mNames[stream].c_str(), errno, strerror(errno));
+        return false;
+    }
+
+    while ((ret = get(&actual, stream)) && (actual != value)) {
+        epollRet = epoll_wait(epollFd, &event, 1, timeoutMs);
+        if (epollRet <= 0) {
+            ALOGE("Polling error or timeout! (%d)", epollRet);
+            return false;
+        }
+    }
+
+    HWAPI_RECORD(value, stream);
+    return ret;
+}
+
+template <typename T>
+void HwApiBase::record(const char *func, const T &value, const std::ios *stream) {
+    std::lock_guard<std::mutex> lock(mRecordsMutex);
+    mRecords.emplace_back(std::make_unique<Record<T>>(func, value, stream));
+    mRecords.pop_front();
+}
+
+template <typename T>
+std::string HwApiBase::Record<T>::toString(const NamesMap &names) {
+    using utils::operator<<;
+    std::stringstream ret;
+
+    ret << mFunc << " '" << names.at(mStream) << "' = '" << mValue << "'";
+
+    return ret.str();
+}
+
+class HwCalBase {
+  public:
+    HwCalBase();
+    void debug(int fd);
+
+  protected:
+    template <typename T>
+    bool getProperty(const char *key, T *value, const T defval);
+    template <typename T>
+    bool getPersist(const char *key, T *value);
+
+  private:
+    std::string mPropertyPrefix;
+    std::map<std::string, std::string> mCalData;
+};
+
+template <typename T>
+bool HwCalBase::getProperty(const char *key, T *outval, const T defval) {
+    ATRACE_NAME("HwCal::getProperty");
+    *outval = utils::getProperty(mPropertyPrefix + key, defval);
+    return true;
+}
+
+template <typename T>
+bool HwCalBase::getPersist(const char *key, T *value) {
+    ATRACE_NAME("HwCal::getPersist");
+    auto it = mCalData.find(key);
+    if (it == mCalData.end()) {
+        ALOGE("Missing %s config!", key);
+        return false;
+    }
+    std::stringstream stream{it->second};
+    utils::unpack(stream, value);
+    if (!stream || !stream.eof()) {
+        ALOGE("Invalid %s config!", key);
+        return false;
+    }
+    return true;
+}
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/common/utils.h b/vibrator/common/utils.h
new file mode 100644
index 0000000..188554d
--- /dev/null
+++ b/vibrator/common/utils.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2019 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#pragma once
+
+#include <android-base/macros.h>
+#include <android-base/parsedouble.h>
+#include <android-base/properties.h>
+#include <log/log.h>
+
+#include <fstream>
+#include <map>
+#include <sstream>
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+namespace utils {
+
+template <typename T>
+class Is_Iterable {
+  private:
+    template <typename U>
+    static std::true_type test(typename U::iterator *u);
+
+    template <typename U>
+    static std::false_type test(U *u);
+
+  public:
+    static const bool value = decltype(test<T>(0))::value;
+};
+
+template <typename T, bool B>
+using Enable_If_Iterable = std::enable_if_t<Is_Iterable<T>::value == B>;
+
+template <typename T, typename U = void>
+using Enable_If_Signed = std::enable_if_t<std::is_signed_v<T>, U>;
+
+template <typename T, typename U = void>
+using Enable_If_Unsigned = std::enable_if_t<std::is_unsigned_v<T>, U>;
+
+// override for default behavior of printing as a character
+inline std::ostream &operator<<(std::ostream &stream, const int8_t value) {
+    return stream << +value;
+}
+// override for default behavior of printing as a character
+inline std::ostream &operator<<(std::ostream &stream, const uint8_t value) {
+    return stream << +value;
+}
+
+template <typename T>
+inline auto toUnderlying(const T value) {
+    return static_cast<std::underlying_type_t<T>>(value);
+}
+
+template <typename T>
+inline Enable_If_Iterable<T, true> unpack(std::istream &stream, T *value) {
+    for (auto &entry : *value) {
+        stream >> entry;
+    }
+}
+
+template <typename T>
+inline Enable_If_Iterable<T, false> unpack(std::istream &stream, T *value) {
+    stream >> *value;
+}
+
+template <>
+inline void unpack<std::string>(std::istream &stream, std::string *value) {
+    *value = std::string(std::istreambuf_iterator(stream), {});
+    stream.setstate(std::istream::eofbit);
+}
+
+template <typename T>
+inline Enable_If_Signed<T, T> getProperty(const std::string &key, const T def) {
+    if (std::is_floating_point_v<T>) {
+        float result;
+        std::string value = ::android::base::GetProperty(key, "");
+        if (!value.empty() && ::android::base::ParseFloat(value, &result)) {
+            return result;
+        }
+        return def;
+    } else {
+        return ::android::base::GetIntProperty(key, def);
+    }
+}
+
+template <typename T>
+inline Enable_If_Unsigned<T, T> getProperty(const std::string &key, const T def) {
+    return ::android::base::GetUintProperty(key, def);
+}
+
+template <>
+inline bool getProperty<bool>(const std::string &key, const bool def) {
+    return ::android::base::GetBoolProperty(key, def);
+}
+
+template <typename T>
+static void openNoCreate(const std::string &file, T *outStream) {
+    auto mode = std::is_base_of_v<std::ostream, T> ? std::ios_base::out : std::ios_base::in;
+
+    // Force 'in' mode to prevent file creation
+    outStream->open(file, mode | std::ios_base::in);
+    if (!*outStream) {
+        ALOGE("Failed to open %s (%d): %s", file.c_str(), errno, strerror(errno));
+    }
+}
+
+template <typename T>
+static void fileFromEnv(const char *env, T *outStream, std::string *outName = nullptr) {
+    auto file = std::getenv(env);
+
+    if (file == nullptr) {
+        ALOGE("Failed get env %s", env);
+        return;
+    }
+
+    if (outName != nullptr) {
+        *outName = std::string(file);
+    }
+
+    openNoCreate(file, outStream);
+}
+
+static ATTRIBUTE_UNUSED auto pathsFromEnv(const char *env, const std::string &prefix = "") {
+    std::map<std::string, std::ifstream> ret;
+    auto value = std::getenv(env);
+
+    if (value == nullptr) {
+        return ret;
+    }
+
+    std::istringstream paths{value};
+    std::string path;
+
+    while (paths >> path) {
+        ret[path].open(prefix + path);
+    }
+
+    return ret;
+}
+
+static ATTRIBUTE_UNUSED std::string trim(const std::string &str,
+                                         const std::string &whitespace = " \t") {
+    const auto str_begin = str.find_first_not_of(whitespace);
+    if (str_begin == std::string::npos) {
+        return "";
+    }
+
+    const auto str_end = str.find_last_not_of(whitespace);
+    const auto str_range = str_end - str_begin + 1;
+
+    return str.substr(str_begin, str_range);
+}
+
+}  // namespace utils
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/Android.bp b/vibrator/cs40l26/Android.bp
new file mode 100644
index 0000000..9ac51d1
--- /dev/null
+++ b/vibrator/cs40l26/Android.bp
@@ -0,0 +1,78 @@
+//
+// Copyright (C) 2021 The Android Open Source Project
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package {
+    default_applicable_licenses: ["Android-Apache-2.0"],
+}
+
+cc_defaults {
+    name: "android.hardware.vibrator-defaults.cs40l26-private",
+    cflags: [
+        "-DATRACE_TAG=(ATRACE_TAG_VIBRATOR | ATRACE_TAG_HAL)",
+    ],
+    shared_libs: [
+        "libbinder",
+    ],
+}
+
+cc_defaults {
+    name: "VibratorHalCs40l26BinaryDefaultsPrivate",
+    defaults: [
+        "PixelVibratorBinaryDefaultsPrivate",
+        "android.hardware.vibrator-defaults.cs40l26-private",
+    ],
+    shared_libs: [
+        "libcutils",
+        "libtinyalsa",
+    ],
+    include_dirs: [
+        "external/tinyalsa/include",
+    ],
+}
+
+cc_defaults {
+    name: "VibratorHalCs40l26TestDefaultsPrivate",
+    defaults: [
+        "PixelVibratorTestDefaultsPrivate",
+        "android.hardware.vibrator-defaults.cs40l26-private",
+    ],
+    static_libs: [
+        "android.hardware.vibrator-impl.cs40l26-private",
+        "libtinyalsa",
+    ],
+}
+
+cc_library {
+    name: "android.hardware.vibrator-impl.cs40l26-private",
+    defaults: ["VibratorHalCs40l26BinaryDefaultsPrivate"],
+    srcs: [
+        "Vibrator.cpp",
+    ],
+    export_include_dirs: ["."],
+    vendor_available: true,
+    visibility: [":__subpackages__"],
+}
+
+cc_binary {
+    name: "android.hardware.vibrator-service.cs40l26-private",
+    defaults: ["VibratorHalCs40l26BinaryDefaultsPrivate"],
+    init_rc: ["android.hardware.vibrator-service.cs40l26-private.rc"],
+    vintf_fragments: ["android.hardware.vibrator-service.cs40l26-private.xml"],
+    srcs: ["service.cpp"],
+    shared_libs: [
+        "android.hardware.vibrator-impl.cs40l26-private",
+    ],
+    proprietary: true,
+}
diff --git a/vibrator/cs40l26/Hardware.h b/vibrator/cs40l26/Hardware.h
new file mode 100644
index 0000000..00ae2d2
--- /dev/null
+++ b/vibrator/cs40l26/Hardware.h
@@ -0,0 +1,385 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#pragma once
+
+#include <algorithm>
+#include <cmath>
+
+#include "HardwareBase.h"
+#include "Vibrator.h"
+
+#define PROC_SND_PCM "/proc/asound/pcm"
+#define HAPTIC_PCM_DEVICE_SYMBOL "haptic nohost playback"
+
+static struct pcm_config haptic_nohost_config = {
+        .channels = 1,
+        .rate = 48000,
+        .period_size = 80,
+        .period_count = 2,
+        .format = PCM_FORMAT_S16_LE,
+};
+
+enum WaveformIndex : uint16_t {
+    /* Physical waveform */
+    WAVEFORM_LONG_VIBRATION_EFFECT_INDEX = 0,
+    WAVEFORM_RESERVED_INDEX_1 = 1,
+    WAVEFORM_CLICK_INDEX = 2,
+    WAVEFORM_SHORT_VIBRATION_EFFECT_INDEX = 3,
+    WAVEFORM_THUD_INDEX = 4,
+    WAVEFORM_SPIN_INDEX = 5,
+    WAVEFORM_QUICK_RISE_INDEX = 6,
+    WAVEFORM_SLOW_RISE_INDEX = 7,
+    WAVEFORM_QUICK_FALL_INDEX = 8,
+    WAVEFORM_LIGHT_TICK_INDEX = 9,
+    WAVEFORM_LOW_TICK_INDEX = 10,
+    WAVEFORM_RESERVED_MFG_1,
+    WAVEFORM_RESERVED_MFG_2,
+    WAVEFORM_RESERVED_MFG_3,
+    WAVEFORM_MAX_PHYSICAL_INDEX,
+    /* OWT waveform */
+    WAVEFORM_COMPOSE = WAVEFORM_MAX_PHYSICAL_INDEX,
+    WAVEFORM_PWLE,
+    /*
+     * Refer to <linux/input.h>, the WAVEFORM_MAX_INDEX must not exceed 96.
+     * #define FF_GAIN          0x60  // 96 in decimal
+     * #define FF_MAX_EFFECTS   FF_GAIN
+     */
+    WAVEFORM_MAX_INDEX,
+};
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+class HwApi : public Vibrator::HwApi, private HwApiBase {
+  public:
+    static std::unique_ptr<HwApi> Create() {
+        auto hwapi = std::unique_ptr<HwApi>(new HwApi());
+        return hwapi;
+    }
+    HwApi() {
+        open("calibration/f0_stored", &mF0);
+        open("default/f0_offset", &mF0Offset);
+        open("calibration/redc_stored", &mRedc);
+        open("calibration/q_stored", &mQ);
+        open("default/vibe_state", &mVibeState);
+        open("default/num_waves", &mEffectCount);
+        open("default/owt_free_space", &mOwtFreeSpace);
+        open("default/f0_comp_enable", &mF0CompEnable);
+        open("default/redc_comp_enable", &mRedcCompEnable);
+        open("default/delay_before_stop_playback_us", &mMinOnOffInterval);
+    }
+
+    bool setF0(std::string value) override { return set(value, &mF0); }
+    bool setF0Offset(uint32_t value) override { return set(value, &mF0Offset); }
+    bool setRedc(std::string value) override { return set(value, &mRedc); }
+    bool setQ(std::string value) override { return set(value, &mQ); }
+    bool getEffectCount(uint32_t *value) override { return get(value, &mEffectCount); }
+    bool pollVibeState(uint32_t value, int32_t timeoutMs) override {
+        return poll(value, &mVibeState, timeoutMs);
+    }
+    bool hasOwtFreeSpace() override { return has(mOwtFreeSpace); }
+    bool getOwtFreeSpace(uint32_t *value) override { return get(value, &mOwtFreeSpace); }
+    bool setF0CompEnable(bool value) override { return set(value, &mF0CompEnable); }
+    bool setRedcCompEnable(bool value) override { return set(value, &mRedcCompEnable); }
+    bool setMinOnOffInterval(uint32_t value) override { return set(value, &mMinOnOffInterval); }
+    // TODO(b/234338136): Need to add the force feedback HW API test cases
+    bool setFFGain(int fd, uint16_t value) override {
+        struct input_event gain = {
+                .type = EV_FF,
+                .code = FF_GAIN,
+                .value = value,
+        };
+        if (write(fd, (const void *)&gain, sizeof(gain)) != sizeof(gain)) {
+            return false;
+        }
+        return true;
+    }
+    bool setFFEffect(int fd, struct ff_effect *effect, uint16_t timeoutMs) override {
+        if (((*effect).replay.length != timeoutMs) || (ioctl(fd, EVIOCSFF, effect) < 0)) {
+            ALOGE("setFFEffect fail");
+            return false;
+        } else {
+            return true;
+        }
+    }
+    bool setFFPlay(int fd, int8_t index, bool value) override {
+        struct input_event play = {
+                .type = EV_FF,
+                .code = static_cast<uint16_t>(index),
+                .value = value,
+        };
+        if (write(fd, (const void *)&play, sizeof(play)) != sizeof(play)) {
+            return false;
+        } else {
+            return true;
+        }
+    }
+    bool getHapticAlsaDevice(int *card, int *device) override {
+        std::string line;
+        std::ifstream myfile(PROC_SND_PCM);
+        if (myfile.is_open()) {
+            while (getline(myfile, line)) {
+                if (line.find(HAPTIC_PCM_DEVICE_SYMBOL) != std::string::npos) {
+                    std::stringstream ss(line);
+                    std::string currentToken;
+                    std::getline(ss, currentToken, ':');
+                    sscanf(currentToken.c_str(), "%d-%d", card, device);
+                    return true;
+                }
+            }
+            myfile.close();
+        } else {
+            ALOGE("Failed to read file: %s", PROC_SND_PCM);
+        }
+        return false;
+    }
+    bool setHapticPcmAmp(struct pcm **haptic_pcm, bool enable, int card, int device) override {
+        int ret = 0;
+
+        if (enable) {
+            *haptic_pcm = pcm_open(card, device, PCM_OUT, &haptic_nohost_config);
+            if (!pcm_is_ready(*haptic_pcm)) {
+                ALOGE("cannot open pcm_out driver: %s", pcm_get_error(*haptic_pcm));
+                goto fail;
+            }
+
+            ret = pcm_prepare(*haptic_pcm);
+            if (ret < 0) {
+                ALOGE("cannot prepare haptic_pcm: %s", pcm_get_error(*haptic_pcm));
+                goto fail;
+            }
+
+            ret = pcm_start(*haptic_pcm);
+            if (ret < 0) {
+                ALOGE("cannot start haptic_pcm: %s", pcm_get_error(*haptic_pcm));
+                goto fail;
+            }
+
+            return true;
+        } else {
+            if (*haptic_pcm) {
+                pcm_close(*haptic_pcm);
+                *haptic_pcm = NULL;
+            }
+            return true;
+        }
+
+    fail:
+        pcm_close(*haptic_pcm);
+        *haptic_pcm = NULL;
+        return false;
+    }
+    bool uploadOwtEffect(int fd, uint8_t *owtData, uint32_t numBytes, struct ff_effect *effect,
+                         uint32_t *outEffectIndex, int *status) override {
+        (*effect).u.periodic.custom_len = numBytes / sizeof(uint16_t);
+        delete[] ((*effect).u.periodic.custom_data);
+        (*effect).u.periodic.custom_data = new int16_t[(*effect).u.periodic.custom_len]{0x0000};
+        if ((*effect).u.periodic.custom_data == nullptr) {
+            ALOGE("Failed to allocate memory for custom data\n");
+            *status = EX_NULL_POINTER;
+            return false;
+        }
+        memcpy((*effect).u.periodic.custom_data, owtData, numBytes);
+
+        if ((*effect).id != -1) {
+            ALOGE("(*effect).id != -1");
+        }
+
+        /* Create a new OWT waveform to update the PWLE or composite effect. */
+        (*effect).id = -1;
+        if (ioctl(fd, EVIOCSFF, effect) < 0) {
+            ALOGE("Failed to upload effect %d (%d): %s", *outEffectIndex, errno, strerror(errno));
+            delete[] ((*effect).u.periodic.custom_data);
+            *status = EX_ILLEGAL_STATE;
+            return false;
+        }
+
+        if ((*effect).id >= FF_MAX_EFFECTS || (*effect).id < 0) {
+            ALOGE("Invalid waveform index after upload OWT effect: %d", (*effect).id);
+            *status = EX_ILLEGAL_ARGUMENT;
+            return false;
+        }
+        *outEffectIndex = (*effect).id;
+        *status = 0;
+        return true;
+    }
+    bool eraseOwtEffect(int fd, int8_t effectIndex, std::vector<ff_effect> *effect) override {
+        uint32_t effectCountBefore, effectCountAfter, i, successFlush = 0;
+
+        if (effectIndex < WAVEFORM_MAX_PHYSICAL_INDEX) {
+            ALOGE("Invalid waveform index for OWT erase: %d", effectIndex);
+            return false;
+        }
+        // Turn off the waiting time for SVC init phase to complete since chip
+        // should already under STOP state
+        setMinOnOffInterval(0);
+        // Do erase flow
+        if (effectIndex < WAVEFORM_MAX_INDEX) {
+            /* Normal situation. Only erase the effect which we just played. */
+            if (ioctl(fd, EVIOCRMFF, effectIndex) < 0) {
+                ALOGE("Failed to erase effect %d (%d): %s", effectIndex, errno, strerror(errno));
+            }
+            for (i = WAVEFORM_MAX_PHYSICAL_INDEX; i < WAVEFORM_MAX_INDEX; i++) {
+                if ((*effect)[i].id == effectIndex) {
+                    (*effect)[i].id = -1;
+                    break;
+                }
+            }
+        } else {
+            /* Flush all non-prestored effects of ff-core and driver. */
+            getEffectCount(&effectCountBefore);
+            for (i = WAVEFORM_MAX_PHYSICAL_INDEX; i < FF_MAX_EFFECTS; i++) {
+                if (ioctl(fd, EVIOCRMFF, i) >= 0) {
+                    successFlush++;
+                }
+            }
+            getEffectCount(&effectCountAfter);
+            ALOGW("Flushed effects: ff: %d; driver: %d -> %d; success: %d", effectIndex,
+                  effectCountBefore, effectCountAfter, successFlush);
+            /* Reset all OWT effect index of HAL. */
+            for (i = WAVEFORM_MAX_PHYSICAL_INDEX; i < WAVEFORM_MAX_INDEX; i++) {
+                (*effect)[i].id = -1;
+            }
+        }
+        // Turn on the waiting time for SVC init phase to complete
+        setMinOnOffInterval(Vibrator::MIN_ON_OFF_INTERVAL_US);
+        return true;
+    }
+
+    void debug(int fd) override { HwApiBase::debug(fd); }
+
+  private:
+    std::ofstream mF0;
+    std::ofstream mF0Offset;
+    std::ofstream mRedc;
+    std::ofstream mQ;
+    std::ifstream mEffectCount;
+    std::ifstream mVibeState;
+    std::ifstream mOwtFreeSpace;
+    std::ofstream mF0CompEnable;
+    std::ofstream mRedcCompEnable;
+    std::ofstream mMinOnOffInterval;
+};
+
+class HwCal : public Vibrator::HwCal, private HwCalBase {
+  private:
+    static constexpr char VERSION[] = "version";
+    static constexpr char F0_CONFIG[] = "f0_measured";
+    static constexpr char F0_CONFIG_DUAL[] = "f0_measured_dual";
+    static constexpr char REDC_CONFIG[] = "redc_measured";
+    static constexpr char Q_CONFIG[] = "q_measured";
+    static constexpr char TICK_VOLTAGES_CONFIG[] = "v_tick";
+    static constexpr char CLICK_VOLTAGES_CONFIG[] = "v_click";
+    static constexpr char LONG_VOLTAGES_CONFIG[] = "v_long";
+
+    static constexpr uint32_t VERSION_DEFAULT = 2;
+    static constexpr int32_t DEFAULT_FREQUENCY_SHIFT = 0;
+    static constexpr std::array<uint32_t, 2> V_TICK_DEFAULT = {1, 100};
+    static constexpr std::array<uint32_t, 2> V_CLICK_DEFAULT = {1, 100};
+    static constexpr std::array<uint32_t, 2> V_LONG_DEFAULT = {1, 100};
+
+  public:
+    HwCal() {}
+    static std::unique_ptr<HwCal> Create() {
+        auto hwcal = std::unique_ptr<HwCal>(new HwCal());
+        return hwcal;
+    }
+
+    bool getVersion(uint32_t *value) override {
+        if (getPersist(VERSION, value)) {
+            return true;
+        }
+        *value = VERSION_DEFAULT;
+        return true;
+    }
+    bool getLongFrequencyShift(int32_t *value) override {
+        return getProperty("long.frequency.shift", value, DEFAULT_FREQUENCY_SHIFT);
+    }
+    bool getF0(std::string *value) override { return getPersist(F0_CONFIG, value); }
+    bool getF0SyncOffset(uint32_t *value) override {
+        std::string cal_0{8, '0'};
+        std::string cal_1{8, '0'};
+
+        if (getPersist(F0_CONFIG, &cal_0) && getPersist(F0_CONFIG_DUAL, &cal_1)) {
+            float f0_0 = static_cast<float>(std::stoul(cal_0, nullptr, 16)) / (1 << 14);
+            float f0_1 = static_cast<float>(std::stoul(cal_1, nullptr, 16)) / (1 << 14);
+            float f0_offset = std::abs(f0_0 - f0_1)/2;
+
+            if (f0_0 < f0_1) {
+                *value = static_cast<uint32_t>(f0_offset * std::pow(2, 14));
+            } else if (f0_0 > f0_1) {
+                *value = static_cast<uint32_t>(std::pow(2, 24) - std::abs(f0_offset) * std::pow(2, 14));
+            } else {
+                *value = 0;
+            }
+
+            return true;
+        } else {
+            ALOGE("Vibrator: Unable to load F0_CONFIG or F0_CONFIG_DUAL config");
+            *value = 0;
+            return false;
+        }
+    }
+    bool getRedc(std::string *value) override { return getPersist(REDC_CONFIG, value); }
+    bool getQ(std::string *value) override { return getPersist(Q_CONFIG, value); }
+    bool getTickVolLevels(std::array<uint32_t, 2> *value) override {
+        if (getPersist(TICK_VOLTAGES_CONFIG, value)) {
+            return true;
+        }
+        *value = V_TICK_DEFAULT;
+        return true;
+    }
+    bool getClickVolLevels(std::array<uint32_t, 2> *value) override {
+        if (getPersist(CLICK_VOLTAGES_CONFIG, value)) {
+            return true;
+        }
+        *value = V_CLICK_DEFAULT;
+        return true;
+    }
+    bool getLongVolLevels(std::array<uint32_t, 2> *value) override {
+        if (getPersist(LONG_VOLTAGES_CONFIG, value)) {
+            return true;
+        }
+        *value = V_LONG_DEFAULT;
+        return true;
+    }
+    bool isChirpEnabled() override {
+        bool value;
+        getProperty("chirp.enabled", &value, false);
+        return value;
+    }
+    bool getSupportedPrimitives(uint32_t *value) override {
+        return getProperty("supported_primitives", value, (uint32_t)0);
+    }
+    bool isF0CompEnabled() override {
+        bool value;
+        getProperty("f0.comp.enabled", &value, true);
+        return value;
+    }
+    bool isRedcCompEnabled() override {
+        bool value;
+        getProperty("redc.comp.enabled", &value, true);
+        return value;
+    }
+    void debug(int fd) override { HwCalBase::debug(fd); }
+};
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/TEST_MAPPING b/vibrator/cs40l26/TEST_MAPPING
new file mode 100644
index 0000000..1d8ff7a
--- /dev/null
+++ b/vibrator/cs40l26/TEST_MAPPING
@@ -0,0 +1,10 @@
+{
+  "presubmit": [
+    {
+      "name": "VibratorHalCs40l26TestSuite",
+      "keywords": [
+        "nextgen"
+      ]
+    }
+  ]
+}
diff --git a/vibrator/cs40l26/VibMgrHwApi.h b/vibrator/cs40l26/VibMgrHwApi.h
new file mode 100644
index 0000000..a243f69
--- /dev/null
+++ b/vibrator/cs40l26/VibMgrHwApi.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#pragma once
+
+#include <fcntl.h>
+#include <linux/gpio.h>
+#include <log/log.h>
+
+#include <map>
+
+#include "Vibrator.h"
+#include "utils.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+class VibMgrHwApi : public Vibrator::HwGPIO {
+  private:
+    const uint32_t DEBUG_GPI_PIN = UINT16_MAX;
+    const uint32_t DEBUG_GPI_PIN_SHIFT = UINT16_MAX;
+    std::string mPropertyPrefix;
+    uint32_t mGPIOPin;
+    uint32_t mGPIOShift;
+    struct gpiohandle_request mRq;
+
+  public:
+    static std::unique_ptr<VibMgrHwApi> Create() {
+        auto hwapi = std::unique_ptr<VibMgrHwApi>(new VibMgrHwApi());
+        return hwapi;
+    }
+    bool getGPIO() override {
+        auto propertyPrefix = std::getenv("PROPERTY_PREFIX");
+
+        if (propertyPrefix != NULL) {
+            mPropertyPrefix = std::string(propertyPrefix);
+        } else {
+            ALOGE("GetGPIO: Failed get property prefix!");
+            return false;
+        }
+        mGPIOPin = utils::getProperty(mPropertyPrefix + "gpio.num", DEBUG_GPI_PIN);
+        if (mGPIOPin == DEBUG_GPI_PIN) {
+            ALOGE("GetGPIO: Failed to get the GPIO num: %s", strerror(errno));
+            return false;
+        }
+        mGPIOShift = utils::getProperty(mPropertyPrefix + "gpio.shift", DEBUG_GPI_PIN_SHIFT);
+
+        if (mGPIOShift == DEBUG_GPI_PIN_SHIFT) {
+            ALOGE("GetGPIO: Failed to get the GPIO shift num: %s", strerror(errno));
+            return false;
+        }
+
+        return true;
+    }
+    bool initGPIO() override {
+        const auto gpio_dev = std::string() + "/dev/gpiochip" + std::to_string(mGPIOPin);
+        int fd = open(gpio_dev.c_str(), O_CREAT | O_WRONLY, 0777);
+        if (fd < 0) {
+            ALOGE("InitGPIO: Unable to open gpio dev: %s", strerror(errno));
+            return false;
+        }
+
+        mRq.lineoffsets[0] = mGPIOShift;
+        mRq.lines = 1;
+        mRq.flags = GPIOHANDLE_REQUEST_OUTPUT;
+
+        int ret = ioctl(fd, GPIO_GET_LINEHANDLE_IOCTL, &mRq);
+        if (ret == -1) {
+            ALOGE("InitGPIO: Unable to line handle from ioctl : %s", strerror(errno));
+            close(fd);
+            return false;
+        }
+        if (close(fd) == -1) {
+            ALOGE("Failed to close GPIO char dev");
+            return false;
+        }
+        // Reset gpio status to LOW
+        struct gpiohandle_data data;
+        data.values[0] = 0;
+
+        ret = ioctl(mRq.fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, &data);
+        if (ret == -1) {
+            ALOGE("InitGPIO: Unable to set line value using ioctl : %s", strerror(errno));
+            close(mRq.fd);
+            return false;
+        }
+        return true;
+    }
+    bool setGPIOOutput(bool value) override {
+        struct gpiohandle_data data;
+        data.values[0] = value;
+
+        int ret = ioctl(mRq.fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, &data);
+        if (ret == -1) {
+            ALOGE("SetTrigger: Unable to set line value using ioctl : %s", strerror(errno));
+            close(mRq.fd);
+            return false;
+        }
+
+        return true;
+    }
+    void debug(int fd) override { ALOGD("Debug: %d", fd); }
+
+  private:
+    VibMgrHwApi() { ALOGD("Constructor"); }
+};
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/Vibrator.cpp b/vibrator/cs40l26/Vibrator.cpp
new file mode 100644
index 0000000..5ad996a
--- /dev/null
+++ b/vibrator/cs40l26/Vibrator.cpp
@@ -0,0 +1,1703 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Vibrator.h"
+
+#include <glob.h>
+#include <hardware/hardware.h>
+#include <hardware/vibrator.h>
+#include <log/log.h>
+#include <stdio.h>
+#include <utils/Trace.h>
+
+#include <cinttypes>
+#include <cmath>
+#include <fstream>
+#include <iostream>
+#include <sstream>
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof((x)) / sizeof((x)[0]))
+#endif
+
+#ifdef LOG_TAG
+#undef LOG_TAG
+#define LOG_TAG std::getenv("HAPTIC_NAME")
+#endif
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+static constexpr uint8_t FF_CUSTOM_DATA_LEN = 2;
+static constexpr uint16_t FF_CUSTOM_DATA_LEN_MAX_COMP = 2044;  // (COMPOSE_SIZE_MAX + 1) * 8 + 4
+static constexpr uint16_t FF_CUSTOM_DATA_LEN_MAX_PWLE = 2302;
+
+static constexpr uint32_t WAVEFORM_DOUBLE_CLICK_SILENCE_MS = 100;
+
+static constexpr uint32_t WAVEFORM_LONG_VIBRATION_THRESHOLD_MS = 50;
+
+static constexpr uint8_t VOLTAGE_SCALE_MAX = 100;
+
+static constexpr int8_t MAX_COLD_START_LATENCY_MS = 6;  // I2C Transaction + DSP Return-From-Standby
+static constexpr int8_t MAX_PAUSE_TIMING_ERROR_MS = 1;  // ALERT Irq Handling
+static constexpr uint32_t MAX_TIME_MS = UINT16_MAX;
+static constexpr float SETTING_TIME_OVERHEAD = 26;  // This time was combined by
+                                                    // HAL set the effect to
+                                                    // driver and the kernel
+                                                    // executes the effect before
+                                                    // chip play the effect
+
+static constexpr auto ASYNC_COMPLETION_TIMEOUT = std::chrono::milliseconds(100);
+static constexpr auto POLLING_TIMEOUT = 20;
+static constexpr int32_t COMPOSE_DELAY_MAX_MS = 10000;
+
+/* nsections is 8 bits. Need to preserve 1 section for the first delay before the first effect. */
+static constexpr int32_t COMPOSE_SIZE_MAX = 254;
+static constexpr int32_t COMPOSE_PWLE_SIZE_MAX_DEFAULT = 127;
+
+// Measured resonant frequency, f0_measured, is represented by Q10.14 fixed
+// point format on cs40l26 devices. The expression to calculate f0 is:
+//   f0 = f0_measured / 2^Q14_BIT_SHIFT
+// See the LRA Calibration Support documentation for more details.
+static constexpr int32_t Q14_BIT_SHIFT = 14;
+
+// Measured Q factor, q_measured, is represented by Q8.16 fixed
+// point format on cs40l26 devices. The expression to calculate q is:
+//   q = q_measured / 2^Q16_BIT_SHIFT
+// See the LRA Calibration Support documentation for more details.
+static constexpr int32_t Q16_BIT_SHIFT = 16;
+
+static constexpr int32_t COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS = 16383;
+
+static constexpr uint32_t WT_LEN_CALCD = 0x00800000;
+static constexpr uint8_t PWLE_CHIRP_BIT = 0x8;  // Dynamic/static frequency and voltage
+static constexpr uint8_t PWLE_BRAKE_BIT = 0x4;
+static constexpr uint8_t PWLE_AMP_REG_BIT = 0x2;
+
+static constexpr float PWLE_LEVEL_MIN = 0.0;
+static constexpr float PWLE_LEVEL_MAX = 1.0;
+static constexpr float CS40L26_PWLE_LEVEL_MIX = -1.0;
+static constexpr float CS40L26_PWLE_LEVEL_MAX = 0.9995118;
+static constexpr float PWLE_FREQUENCY_RESOLUTION_HZ = 1.00;
+static constexpr float PWLE_FREQUENCY_MIN_HZ = 1.00;
+static constexpr float PWLE_FREQUENCY_MAX_HZ = 1000.00;
+static constexpr float PWLE_BW_MAP_SIZE =
+        1 + ((PWLE_FREQUENCY_MAX_HZ - PWLE_FREQUENCY_MIN_HZ) / PWLE_FREQUENCY_RESOLUTION_HZ);
+
+/*
+ * [15] Edge, 0:Falling, 1:Rising
+ * [14:12] GPI_NUM, 1:GPI1 (with CS40L26A, 1 is the only supported GPI)
+ * [8] BANK, 0:RAM, 1:R0M
+ * [7] USE_BUZZGEN, 0:Not buzzgen, 1:buzzgen
+ * [6:0] WAVEFORM_INDEX
+ * 0x9100 = 1001 0001 0000 0000: Rising + GPI1 + RAM + Not buzzgen
+ */
+static constexpr uint16_t GPIO_TRIGGER_CONFIG = 0x9100;
+
+static uint16_t amplitudeToScale(float amplitude, float maximum) {
+    float ratio = 100; /* Unit: % */
+    if (maximum != 0)
+        ratio = amplitude / maximum * 100;
+
+    if (maximum == 0 || ratio > 100)
+        ratio = 100;
+
+    return std::round(ratio);
+}
+
+enum WaveformBankID : uint8_t {
+    RAM_WVFRM_BANK,
+    ROM_WVFRM_BANK,
+    OWT_WVFRM_BANK,
+};
+
+enum WaveformIndex : uint16_t {
+    /* Physical waveform */
+    WAVEFORM_LONG_VIBRATION_EFFECT_INDEX = 0,
+    WAVEFORM_RESERVED_INDEX_1 = 1,
+    WAVEFORM_CLICK_INDEX = 2,
+    WAVEFORM_SHORT_VIBRATION_EFFECT_INDEX = 3,
+    WAVEFORM_THUD_INDEX = 4,
+    WAVEFORM_SPIN_INDEX = 5,
+    WAVEFORM_QUICK_RISE_INDEX = 6,
+    WAVEFORM_SLOW_RISE_INDEX = 7,
+    WAVEFORM_QUICK_FALL_INDEX = 8,
+    WAVEFORM_LIGHT_TICK_INDEX = 9,
+    WAVEFORM_LOW_TICK_INDEX = 10,
+    WAVEFORM_RESERVED_MFG_1,
+    WAVEFORM_RESERVED_MFG_2,
+    WAVEFORM_RESERVED_MFG_3,
+    WAVEFORM_MAX_PHYSICAL_INDEX,
+    /* OWT waveform */
+    WAVEFORM_COMPOSE = WAVEFORM_MAX_PHYSICAL_INDEX,
+    WAVEFORM_PWLE,
+    /*
+     * Refer to <linux/input.h>, the WAVEFORM_MAX_INDEX must not exceed 96.
+     * #define FF_GAIN		0x60  // 96 in decimal
+     * #define FF_MAX_EFFECTS	FF_GAIN
+     */
+    WAVEFORM_MAX_INDEX,
+};
+
+std::vector<CompositePrimitive> defaultSupportedPrimitives = {
+        ndk::enum_range<CompositePrimitive>().begin(), ndk::enum_range<CompositePrimitive>().end()};
+
+enum vibe_state {
+    VIBE_STATE_STOPPED = 0,
+    VIBE_STATE_HAPTIC,
+    VIBE_STATE_ASP,
+};
+
+static int min(int x, int y) {
+    return x < y ? x : y;
+}
+
+static int floatToUint16(float input, uint16_t *output, float scale, float min, float max) {
+    if (input < min || input > max)
+        return -ERANGE;
+
+    *output = roundf(input * scale);
+    return 0;
+}
+
+struct dspmem_chunk {
+    uint8_t *head;
+    uint8_t *current;
+    uint8_t *max;
+    int bytes;
+
+    uint32_t cache;
+    int cachebits;
+};
+
+static dspmem_chunk *dspmem_chunk_create(void *data, int size) {
+    auto ch = new dspmem_chunk{
+            .head = reinterpret_cast<uint8_t *>(data),
+            .current = reinterpret_cast<uint8_t *>(data),
+            .max = reinterpret_cast<uint8_t *>(data) + size,
+    };
+
+    return ch;
+}
+
+static bool dspmem_chunk_end(struct dspmem_chunk *ch) {
+    return ch->current == ch->max;
+}
+
+static int dspmem_chunk_bytes(struct dspmem_chunk *ch) {
+    return ch->bytes;
+}
+
+static int dspmem_chunk_write(struct dspmem_chunk *ch, int nbits, uint32_t val) {
+    int nwrite, i;
+
+    nwrite = min(24 - ch->cachebits, nbits);
+    ch->cache <<= nwrite;
+    ch->cache |= val >> (nbits - nwrite);
+    ch->cachebits += nwrite;
+    nbits -= nwrite;
+
+    if (ch->cachebits == 24) {
+        if (dspmem_chunk_end(ch))
+            return -ENOSPC;
+
+        ch->cache &= 0xFFFFFF;
+        for (i = 0; i < sizeof(ch->cache); i++, ch->cache <<= 8)
+            *ch->current++ = (ch->cache & 0xFF000000) >> 24;
+
+        ch->bytes += sizeof(ch->cache);
+        ch->cachebits = 0;
+    }
+
+    if (nbits)
+        return dspmem_chunk_write(ch, nbits, val);
+
+    return 0;
+}
+
+static int dspmem_chunk_flush(struct dspmem_chunk *ch) {
+    if (!ch->cachebits)
+        return 0;
+
+    return dspmem_chunk_write(ch, 24 - ch->cachebits, 0);
+}
+
+Vibrator::Vibrator(std::unique_ptr<HwApi> hwApiDefault, std::unique_ptr<HwCal> hwCalDefault,
+                   std::unique_ptr<HwApi> hwApiDual, std::unique_ptr<HwCal> hwCalDual,
+                   std::unique_ptr<HwGPIO> hwgpio)
+    : mHwApiDef(std::move(hwApiDefault)),
+      mHwCalDef(std::move(hwCalDefault)),
+      mHwApiDual(std::move(hwApiDual)),
+      mHwCalDual(std::move(hwCalDual)),
+      mHwGPIO(std::move(hwgpio)),
+      mAsyncHandle(std::async([] {})) {
+    int32_t longFrequencyShift;
+    std::string caldata{8, '0'};
+    uint32_t calVer;
+
+    // ==================Single actuators and dual actuators checking =============================
+    if ((mHwApiDual != nullptr) && (mHwCalDual != nullptr))
+        mIsDual = true;
+
+    // ==================INPUT Devices== Base =================
+    const char *inputEventName = std::getenv("INPUT_EVENT_NAME");
+    const char *inputEventPathName = std::getenv("INPUT_EVENT_PATH");
+    if ((strstr(inputEventName, "cs40l26") != nullptr) ||
+        (strstr(inputEventName, "cs40l26_dual_input") != nullptr)) {
+        glob_t inputEventPaths;
+        int fd = -1;
+        int ret;
+        uint32_t val = 0;
+        char str[20] = {0x00};
+        for (uint8_t retry = 0; retry < 10; retry++) {
+            ret = glob(inputEventPathName, 0, nullptr, &inputEventPaths);
+            if (ret) {
+                ALOGE("Failed to get input event paths (%d): %s", errno, strerror(errno));
+            } else {
+                for (int i = 0; i < inputEventPaths.gl_pathc; i++) {
+                    fd = TEMP_FAILURE_RETRY(open(inputEventPaths.gl_pathv[i], O_RDWR));
+                    if (fd > 0) {
+                        if (ioctl(fd, EVIOCGBIT(0, sizeof(val)), &val) > 0 &&
+                            (val & (1 << EV_FF)) && ioctl(fd, EVIOCGNAME(sizeof(str)), &str) > 0 &&
+                            strstr(str, inputEventName) != nullptr) {
+                            mInputFd.reset(fd);
+                            ALOGI("Control %s through %s", inputEventName,
+                                  inputEventPaths.gl_pathv[i]);
+                            break;
+                        }
+                        close(fd);
+                    }
+                }
+            }
+
+            if (ret == 0) {
+                globfree(&inputEventPaths);
+            }
+            if (mInputFd.ok()) {
+                break;
+            }
+
+            sleep(1);
+            ALOGW("Retry #%d to search in %zu input devices.", retry, inputEventPaths.gl_pathc);
+        }
+
+        if (!mInputFd.ok()) {
+            ALOGE("Failed to get an input event with name %s", inputEventName);
+        }
+    } else {
+        ALOGE("The input name %s is not cs40l26_input or cs40l26_dual_input", inputEventName);
+    }
+
+    // ==================INPUT Devices== Flip =================
+    if (mIsDual) {
+        const char *inputEventNameDual = std::getenv("INPUT_EVENT_NAME_DUAL");
+        if ((strstr(inputEventNameDual, "cs40l26_dual_input") != nullptr)) {
+            glob_t inputEventPaths;
+            int fd = -1;
+            int ret;
+            uint32_t val = 0;
+            char str[20] = {0x00};
+            for (uint8_t retry = 0; retry < 10; retry++) {
+                ret = glob(inputEventPathName, 0, nullptr, &inputEventPaths);
+                if (ret) {
+                    ALOGE("Failed to get flip's input event paths (%d): %s", errno,
+                          strerror(errno));
+                } else {
+                    for (int i = 0; i < inputEventPaths.gl_pathc; i++) {
+                        fd = TEMP_FAILURE_RETRY(open(inputEventPaths.gl_pathv[i], O_RDWR));
+                        if (fd > 0) {
+                            if (ioctl(fd, EVIOCGBIT(0, sizeof(val)), &val) > 0 &&
+                                (val & (1 << EV_FF)) &&
+                                ioctl(fd, EVIOCGNAME(sizeof(str)), &str) > 0 &&
+                                strstr(str, inputEventNameDual) != nullptr) {
+                                mInputFdDual.reset(fd);
+                                ALOGI("Control %s through %s", inputEventNameDual,
+                                      inputEventPaths.gl_pathv[i]);
+                                break;
+                            }
+                            close(fd);
+                        }
+                    }
+                }
+
+                if (ret == 0) {
+                    globfree(&inputEventPaths);
+                }
+                if (mInputFdDual.ok()) {
+                    break;
+                }
+
+                sleep(1);
+                ALOGW("Retry #%d to search in %zu input devices.", retry, inputEventPaths.gl_pathc);
+            }
+
+            if (!mInputFdDual.ok()) {
+                ALOGE("Failed to get an input event with name %s", inputEventNameDual);
+            }
+            ALOGE("HWAPI: %s", std::getenv("HWAPI_PATH_PREFIX"));
+        } else {
+            ALOGE("The input name %s is not cs40l26_dual_input", inputEventNameDual);
+        }
+    }
+    // ====================HAL internal effect table== Base ==================================
+
+    mFfEffects.resize(WAVEFORM_MAX_INDEX);
+    mEffectDurations.resize(WAVEFORM_MAX_INDEX);
+    mEffectDurations = {
+            1000, 100, 32, 1000, 300, 130, 150, 500, 100, 10, 12, 1000, 1000, 1000,
+    }; /* 11+3 waveforms. The duration must < UINT16_MAX */
+
+    uint8_t effectIndex;
+    for (effectIndex = 0; effectIndex < WAVEFORM_MAX_INDEX; effectIndex++) {
+        if (effectIndex < WAVEFORM_MAX_PHYSICAL_INDEX) {
+            /* Initialize physical waveforms. */
+            mFfEffects[effectIndex] = {
+                    .type = FF_PERIODIC,
+                    .id = -1,
+                    .replay.length = static_cast<uint16_t>(mEffectDurations[effectIndex]),
+                    .u.periodic.waveform = FF_CUSTOM,
+                    .u.periodic.custom_data = new int16_t[2]{RAM_WVFRM_BANK, effectIndex},
+                    .u.periodic.custom_len = FF_CUSTOM_DATA_LEN,
+            };
+            // Bypass the waveform update due to different input name
+            if ((strstr(inputEventName, "cs40l26") != nullptr) ||
+                (strstr(inputEventName, "cs40l26_dual_input") != nullptr)) {
+                if (!mHwApiDef->setFFEffect(
+                            mInputFd, &mFfEffects[effectIndex],
+                            static_cast<uint16_t>(mFfEffects[effectIndex].replay.length))) {
+                    ALOGE("Failed upload effect %d (%d): %s", effectIndex, errno, strerror(errno));
+                }
+            }
+            if (mFfEffects[effectIndex].id != effectIndex) {
+                ALOGW("Unexpected effect index: %d -> %d", effectIndex, mFfEffects[effectIndex].id);
+            }
+        } else {
+            /* Initiate placeholders for OWT effects. */
+            mFfEffects[effectIndex] = {
+                    .type = FF_PERIODIC,
+                    .id = -1,
+                    .replay.length = 0,
+                    .u.periodic.waveform = FF_CUSTOM,
+                    .u.periodic.custom_data = nullptr,
+                    .u.periodic.custom_len = 0,
+            };
+        }
+    }
+
+    // ====================HAL internal effect table== Flip ==================================
+    if (mIsDual) {
+        mFfEffectsDual.resize(WAVEFORM_MAX_INDEX);
+
+        for (effectIndex = 0; effectIndex < WAVEFORM_MAX_INDEX; effectIndex++) {
+            if (effectIndex < WAVEFORM_MAX_PHYSICAL_INDEX) {
+                /* Initialize physical waveforms. */
+                mFfEffectsDual[effectIndex] = {
+                        .type = FF_PERIODIC,
+                        .id = -1,
+                        .replay.length = static_cast<uint16_t>(mEffectDurations[effectIndex]),
+                        .u.periodic.waveform = FF_CUSTOM,
+                        .u.periodic.custom_data = new int16_t[2]{RAM_WVFRM_BANK, effectIndex},
+                        .u.periodic.custom_len = FF_CUSTOM_DATA_LEN,
+                };
+                // Bypass the waveform update due to different input name
+                if ((strstr(inputEventName, "cs40l26") != nullptr) ||
+                    (strstr(inputEventName, "cs40l26_dual_input") != nullptr)) {
+                    if (!mHwApiDual->setFFEffect(
+                                mInputFdDual, &mFfEffectsDual[effectIndex],
+                                static_cast<uint16_t>(mFfEffectsDual[effectIndex].replay.length))) {
+                        ALOGE("Failed upload flip's effect %d (%d): %s", effectIndex, errno,
+                              strerror(errno));
+                    }
+                }
+                if (mFfEffectsDual[effectIndex].id != effectIndex) {
+                    ALOGW("Unexpected effect index: %d -> %d", effectIndex,
+                          mFfEffectsDual[effectIndex].id);
+                }
+            } else {
+                /* Initiate placeholders for OWT effects. */
+                mFfEffectsDual[effectIndex] = {
+                        .type = FF_PERIODIC,
+                        .id = -1,
+                        .replay.length = 0,
+                        .u.periodic.waveform = FF_CUSTOM,
+                        .u.periodic.custom_data = nullptr,
+                        .u.periodic.custom_len = 0,
+                };
+            }
+        }
+    }
+    // ==============Calibration data checking======================================
+
+    if (mHwCalDef->getF0(&caldata)) {
+        mHwApiDef->setF0(caldata);
+    }
+    if (mHwCalDef->getRedc(&caldata)) {
+        mHwApiDef->setRedc(caldata);
+    }
+    if (mHwCalDef->getQ(&caldata)) {
+        mHwApiDef->setQ(caldata);
+    }
+
+    if (mHwCalDef->getF0SyncOffset(&mF0Offset)) {
+        ALOGD("Vibrator::Vibrator: F0 offset calculated from both base and flip calibration data: "
+              "%u",
+              mF0Offset);
+    } else {
+        mHwCalDef->getLongFrequencyShift(&longFrequencyShift);
+        if (longFrequencyShift > 0) {
+            mF0Offset = longFrequencyShift * std::pow(2, 14);
+        } else if (longFrequencyShift < 0) {
+            mF0Offset = std::pow(2, 24) - std::abs(longFrequencyShift) * std::pow(2, 14);
+        } else {
+            mF0Offset = 0;
+        }
+        ALOGD("Vibrator::Vibrator: F0 offset calculated from long shift frequency: %u", mF0Offset);
+    }
+
+    if (mIsDual) {
+        if (mHwCalDual->getF0(&caldata)) {
+            mHwApiDual->setF0(caldata);
+        }
+        if (mHwCalDual->getRedc(&caldata)) {
+            mHwApiDual->setRedc(caldata);
+        }
+        if (mHwCalDual->getQ(&caldata)) {
+            mHwApiDual->setQ(caldata);
+        }
+
+        if (mHwCalDual->getF0SyncOffset(&mF0OffsetDual)) {
+            ALOGD("Vibrator::Vibrator: Dual: F0 offset calculated from both base and flip "
+                  "calibration data: "
+                  "%u",
+                  mF0OffsetDual);
+        }
+    }
+
+    mHwCalDef->getVersion(&calVer);
+    if (calVer == 2) {
+        mHwCalDef->getTickVolLevels(&(mTickEffectVol));
+        mHwCalDef->getClickVolLevels(&(mClickEffectVol));
+        mHwCalDef->getLongVolLevels(&(mLongEffectVol));
+    } else {
+        ALOGW("Unsupported calibration version! Using the default calibration value");
+        mHwCalDef->getTickVolLevels(&(mTickEffectVol));
+        mHwCalDef->getClickVolLevels(&(mClickEffectVol));
+        mHwCalDef->getLongVolLevels(&(mLongEffectVol));
+    }
+
+    // ================Project specific setting to driver===============================
+
+    mHwApiDef->setF0CompEnable(mHwCalDef->isF0CompEnabled());
+    mHwApiDef->setRedcCompEnable(mHwCalDef->isRedcCompEnabled());
+    mHwApiDef->setMinOnOffInterval(MIN_ON_OFF_INTERVAL_US);
+    if (mIsDual) {
+        mHwApiDual->setF0CompEnable(mHwCalDual->isF0CompEnabled());
+        mHwApiDual->setRedcCompEnable(mHwCalDual->isRedcCompEnabled());
+        mHwApiDual->setMinOnOffInterval(MIN_ON_OFF_INTERVAL_US);
+    }
+    // ===============Audio coupled haptics bool init ========
+    mIsUnderExternalControl = false;
+
+    // =============== Compose PWLE check =====================================
+    mIsChirpEnabled = mHwCalDef->isChirpEnabled();
+
+    mHwCalDef->getSupportedPrimitives(&mSupportedPrimitivesBits);
+    if (mSupportedPrimitivesBits > 0) {
+        for (auto e : defaultSupportedPrimitives) {
+            if (mSupportedPrimitivesBits & (1 << uint32_t(e))) {
+                mSupportedPrimitives.emplace_back(e);
+            }
+        }
+    } else {
+        for (auto e : defaultSupportedPrimitives) {
+            mSupportedPrimitivesBits |= (1 << uint32_t(e));
+        }
+        mSupportedPrimitives = defaultSupportedPrimitives;
+    }
+
+    mPrimitiveMaxScale = {1.0f, 0.95f, 0.75f, 0.9f, 1.0f, 1.0f, 1.0f, 0.75f, 0.75f};
+    mPrimitiveMinScale = {0.0f, 0.01f, 0.11f, 0.23f, 0.0f, 0.25f, 0.02f, 0.03f, 0.16f};
+
+    // ====== Get GPIO status and init it ================
+    mGPIOStatus = mHwGPIO->getGPIO();
+    if (!mGPIOStatus || !mHwGPIO->initGPIO()) {
+        ALOGE("Vibrator: GPIO initialization process error");
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getCapabilities(int32_t *_aidl_return) {
+    ATRACE_NAME("Vibrator::getCapabilities");
+
+    int32_t ret = IVibrator::CAP_ON_CALLBACK | IVibrator::CAP_PERFORM_CALLBACK |
+                  IVibrator::CAP_AMPLITUDE_CONTROL | IVibrator::CAP_GET_RESONANT_FREQUENCY |
+                  IVibrator::CAP_GET_Q_FACTOR;
+    if (hasHapticAlsaDevice()) {
+        ret |= IVibrator::CAP_EXTERNAL_CONTROL;
+    } else {
+        ALOGE("No haptics ALSA device");
+    }
+    if (mHwApiDef->hasOwtFreeSpace()) {
+        ret |= IVibrator::CAP_COMPOSE_EFFECTS;
+        if (mIsChirpEnabled) {
+            ret |= IVibrator::CAP_FREQUENCY_CONTROL | IVibrator::CAP_COMPOSE_PWLE_EFFECTS;
+        }
+    }
+    *_aidl_return = ret;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::off() {
+    ATRACE_NAME("Vibrator::off");
+    bool ret{true};
+    const std::scoped_lock<std::mutex> lock(mActiveId_mutex);
+
+    if (mActiveId >= 0) {
+        ALOGD("Off: Stop the active effect: %d", mActiveId);
+        /* Stop the active effect. */
+        if (!mHwApiDef->setFFPlay(mInputFd, mActiveId, false)) {
+            ALOGE("Off: Failed to stop effect %d (%d): %s", mActiveId, errno, strerror(errno));
+            ret = false;
+        }
+        if (mIsDual && (!mHwApiDual->setFFPlay(mInputFdDual, mActiveId, false))) {
+            ALOGE("Off: Failed to stop flip's effect %d (%d): %s", mActiveId, errno,
+                  strerror(errno));
+            ret = false;
+        }
+
+        if (!mHwGPIO->setGPIOOutput(false)) {
+            ALOGE("Off: Failed to reset GPIO(%d): %s", errno, strerror(errno));
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+        }
+    } else {
+        ALOGD("Off: Vibrator is already off");
+    }
+
+    setGlobalAmplitude(false);
+    if (mF0Offset) {
+        mHwApiDef->setF0Offset(0);
+        if (mIsDual && mF0OffsetDual) {
+            mHwApiDual->setF0Offset(0);
+        }
+    }
+
+    if (ret) {
+        ALOGD("Off: Done.");
+        mActiveId = -1;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::on(int32_t timeoutMs,
+                                const std::shared_ptr<IVibratorCallback> &callback) {
+    ATRACE_NAME("Vibrator::on");
+    ALOGD("Vibrator::on");
+
+    if (timeoutMs > MAX_TIME_MS) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+    const uint16_t index = (timeoutMs < WAVEFORM_LONG_VIBRATION_THRESHOLD_MS)
+                                   ? WAVEFORM_SHORT_VIBRATION_EFFECT_INDEX
+                                   : WAVEFORM_LONG_VIBRATION_EFFECT_INDEX;
+    if (MAX_COLD_START_LATENCY_MS <= MAX_TIME_MS - timeoutMs) {
+        timeoutMs += MAX_COLD_START_LATENCY_MS;
+    }
+    setGlobalAmplitude(true);
+    if (mF0Offset) {
+        mHwApiDef->setF0Offset(mF0Offset);
+        if (mIsDual && mF0OffsetDual) {
+            mHwApiDual->setF0Offset(mF0OffsetDual);
+        }
+    }
+    return on(timeoutMs, index, nullptr /*ignored*/, callback);
+}
+
+ndk::ScopedAStatus Vibrator::perform(Effect effect, EffectStrength strength,
+                                     const std::shared_ptr<IVibratorCallback> &callback,
+                                     int32_t *_aidl_return) {
+    ATRACE_NAME("Vibrator::perform");
+    ALOGD("Vibrator::perform");
+    return performEffect(effect, strength, callback, _aidl_return);
+}
+
+ndk::ScopedAStatus Vibrator::getSupportedEffects(std::vector<Effect> *_aidl_return) {
+    *_aidl_return = {Effect::TEXTURE_TICK, Effect::TICK, Effect::CLICK, Effect::HEAVY_CLICK,
+                     Effect::DOUBLE_CLICK};
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::setAmplitude(float amplitude) {
+    ATRACE_NAME("Vibrator::setAmplitude");
+
+    if (amplitude <= 0.0f || amplitude > 1.0f) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+
+    mLongEffectScale = amplitude;
+    if (!isUnderExternalControl()) {
+        return setGlobalAmplitude(true);
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::setExternalControl(bool enabled) {
+    ATRACE_NAME("Vibrator::setExternalControl");
+
+    setGlobalAmplitude(enabled);
+
+    if (mHasHapticAlsaDevice || mConfigHapticAlsaDeviceDone || hasHapticAlsaDevice()) {
+        if (!mHwApiDef->setHapticPcmAmp(&mHapticPcm, enabled, mCard, mDevice)) {
+            ALOGE("Failed to %s haptic pcm device: %d", (enabled ? "enable" : "disable"), mDevice);
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+        }
+    } else {
+        ALOGE("No haptics ALSA device");
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+
+    mIsUnderExternalControl = enabled;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getCompositionDelayMax(int32_t *maxDelayMs) {
+    ATRACE_NAME("Vibrator::getCompositionDelayMax");
+    *maxDelayMs = COMPOSE_DELAY_MAX_MS;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getCompositionSizeMax(int32_t *maxSize) {
+    ATRACE_NAME("Vibrator::getCompositionSizeMax");
+    *maxSize = COMPOSE_SIZE_MAX;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getSupportedPrimitives(std::vector<CompositePrimitive> *supported) {
+    *supported = mSupportedPrimitives;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getPrimitiveDuration(CompositePrimitive primitive,
+                                                  int32_t *durationMs) {
+    ndk::ScopedAStatus status;
+    uint32_t effectIndex;
+    if (primitive != CompositePrimitive::NOOP) {
+        status = getPrimitiveDetails(primitive, &effectIndex);
+        if (!status.isOk()) {
+            return status;
+        }
+        // Please check the overhead time detail in b/261841035
+        *durationMs = mEffectDurations[effectIndex] + SETTING_TIME_OVERHEAD;
+    } else {
+        *durationMs = 0;
+    }
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::compose(const std::vector<CompositeEffect> &composite,
+                                     const std::shared_ptr<IVibratorCallback> &callback) {
+    ATRACE_NAME("Vibrator::compose");
+    ALOGD("Vibrator::compose");
+    uint16_t size;
+    uint16_t nextEffectDelay;
+    uint16_t totalDuration = 0;
+
+    auto ch = dspmem_chunk_create(new uint8_t[FF_CUSTOM_DATA_LEN_MAX_COMP]{0x00},
+                                  FF_CUSTOM_DATA_LEN_MAX_COMP);
+
+    if (composite.size() > COMPOSE_SIZE_MAX || composite.empty()) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+
+    /* Check if there is a wait before the first effect. */
+    nextEffectDelay = composite.front().delayMs;
+    totalDuration += nextEffectDelay;
+    if (nextEffectDelay > COMPOSE_DELAY_MAX_MS || nextEffectDelay < 0) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    } else if (nextEffectDelay > 0) {
+        size = composite.size() + 1;
+    } else {
+        size = composite.size();
+    }
+
+    dspmem_chunk_write(ch, 8, 0);                      /* Padding */
+    dspmem_chunk_write(ch, 8, (uint8_t)(0xFF & size)); /* nsections */
+    dspmem_chunk_write(ch, 8, 0);                      /* repeat */
+    uint8_t header_count = dspmem_chunk_bytes(ch);
+
+    /* Insert 1 section for a wait before the first effect. */
+    if (nextEffectDelay) {
+        dspmem_chunk_write(ch, 32, 0); /* amplitude, index, repeat & flags */
+        dspmem_chunk_write(ch, 16, (uint16_t)(0xFFFF & nextEffectDelay)); /* delay */
+    }
+
+    for (uint32_t i_curr = 0, i_next = 1; i_curr < composite.size(); i_curr++, i_next++) {
+        auto &e_curr = composite[i_curr];
+        uint32_t effectIndex = 0;
+        uint32_t effectVolLevel = 0;
+        float effectScale = e_curr.scale;
+        if (effectScale < 0.0f || effectScale > 1.0f) {
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        }
+
+        if (e_curr.primitive != CompositePrimitive::NOOP) {
+            ndk::ScopedAStatus status;
+            status = getPrimitiveDetails(e_curr.primitive, &effectIndex);
+            if (!status.isOk()) {
+                return status;
+            }
+            // Add a max and min threshold to prevent the device crash(overcurrent) or no
+            // feeling
+            if (effectScale > mPrimitiveMaxScale[static_cast<uint32_t>(e_curr.primitive)]) {
+                effectScale = mPrimitiveMaxScale[static_cast<uint32_t>(e_curr.primitive)];
+            }
+            if (effectScale < mPrimitiveMinScale[static_cast<uint32_t>(e_curr.primitive)]) {
+                effectScale = mPrimitiveMinScale[static_cast<uint32_t>(e_curr.primitive)];
+            }
+            effectVolLevel = intensityToVolLevel(effectScale, effectIndex);
+            totalDuration += mEffectDurations[effectIndex];
+        }
+
+        /* Fetch the next composite effect delay and fill into the current section */
+        nextEffectDelay = 0;
+        if (i_next < composite.size()) {
+            auto &e_next = composite[i_next];
+            int32_t delay = e_next.delayMs;
+
+            if (delay > COMPOSE_DELAY_MAX_MS || delay < 0) {
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+            }
+            nextEffectDelay = delay;
+            totalDuration += delay;
+        }
+
+        if (effectIndex == 0 && nextEffectDelay == 0) {
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        }
+
+        dspmem_chunk_write(ch, 8, (uint8_t)(0xFF & effectVolLevel));      /* amplitude */
+        dspmem_chunk_write(ch, 8, (uint8_t)(0xFF & effectIndex));         /* index */
+        dspmem_chunk_write(ch, 8, 0);                                     /* repeat */
+        dspmem_chunk_write(ch, 8, 0);                                     /* flags */
+        dspmem_chunk_write(ch, 16, (uint16_t)(0xFFFF & nextEffectDelay)); /* delay */
+    }
+    dspmem_chunk_flush(ch);
+    if (header_count == dspmem_chunk_bytes(ch)) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    } else {
+        mFfEffects[WAVEFORM_COMPOSE].replay.length = totalDuration;
+        if (mIsDual) {
+            mFfEffectsDual[WAVEFORM_COMPOSE].replay.length = totalDuration;
+        }
+        return performEffect(WAVEFORM_MAX_INDEX /*ignored*/, VOLTAGE_SCALE_MAX /*ignored*/, ch,
+                             callback);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::on(uint32_t timeoutMs, uint32_t effectIndex, dspmem_chunk *ch,
+                                const std::shared_ptr<IVibratorCallback> &callback) {
+    ndk::ScopedAStatus status = ndk::ScopedAStatus::ok();
+
+    if (effectIndex >= FF_MAX_EFFECTS) {
+        ALOGE("Invalid waveform index %d", effectIndex);
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+    if (mAsyncHandle.wait_for(ASYNC_COMPLETION_TIMEOUT) != std::future_status::ready) {
+        ALOGE("Previous vibration pending: prev: %d, curr: %d", mActiveId, effectIndex);
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+
+    if (ch) {
+        /* Upload OWT effect. */
+        if (ch->head == nullptr) {
+            ALOGE("Invalid OWT bank");
+            delete ch;
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        }
+        bool isPwle = (*reinterpret_cast<uint16_t *>(ch->head) != 0x0000);
+        effectIndex = isPwle ? WAVEFORM_PWLE : WAVEFORM_COMPOSE;
+
+        uint32_t freeBytes;
+        mHwApiDef->getOwtFreeSpace(&freeBytes);
+        if (dspmem_chunk_bytes(ch) > freeBytes) {
+            ALOGE("Invalid OWT length: Effect %d: %d > %d!", effectIndex, dspmem_chunk_bytes(ch),
+                  freeBytes);
+            delete ch;
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        }
+        if (mIsDual) {
+            mHwApiDual->getOwtFreeSpace(&freeBytes);
+            if (dspmem_chunk_bytes(ch) > freeBytes) {
+                ALOGE("Invalid OWT length in flip: Effect %d: %d > %d!", effectIndex,
+                      dspmem_chunk_bytes(ch), freeBytes);
+                delete ch;
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+            }
+        }
+
+        int errorStatus;
+        if (mGPIOStatus && mIsDual) {
+            mFfEffects[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+            mFfEffectsDual[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+        } else {
+            ALOGD("Not dual haptics HAL and GPIO status fail");
+        }
+
+        if (!mHwApiDef->uploadOwtEffect(mInputFd, ch->head, dspmem_chunk_bytes(ch),
+                                        &mFfEffects[effectIndex], &effectIndex, &errorStatus)) {
+            delete ch;
+            ALOGE("Invalid uploadOwtEffect");
+            return ndk::ScopedAStatus::fromExceptionCode(errorStatus);
+        }
+        if (mIsDual && !mHwApiDual->uploadOwtEffect(mInputFdDual, ch->head, dspmem_chunk_bytes(ch),
+                                                    &mFfEffectsDual[effectIndex], &effectIndex,
+                                                    &errorStatus)) {
+            delete ch;
+            ALOGE("Invalid uploadOwtEffect in flip");
+            return ndk::ScopedAStatus::fromExceptionCode(errorStatus);
+        }
+        delete ch;
+
+    } else if (effectIndex == WAVEFORM_SHORT_VIBRATION_EFFECT_INDEX ||
+               effectIndex == WAVEFORM_LONG_VIBRATION_EFFECT_INDEX) {
+        /* Update duration for long/short vibration. */
+        mFfEffects[effectIndex].replay.length = static_cast<uint16_t>(timeoutMs);
+        if (mGPIOStatus && mIsDual) {
+            mFfEffects[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+            mFfEffectsDual[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+        } else {
+            ALOGD("Not dual haptics HAL and GPIO status fail");
+        }
+        if (!mHwApiDef->setFFEffect(mInputFd, &mFfEffects[effectIndex],
+                                    static_cast<uint16_t>(timeoutMs))) {
+            ALOGE("Failed to edit effect %d (%d): %s", effectIndex, errno, strerror(errno));
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+        }
+        if (mIsDual) {
+            mFfEffectsDual[effectIndex].replay.length = static_cast<uint16_t>(timeoutMs);
+            if (!mHwApiDual->setFFEffect(mInputFdDual, &mFfEffectsDual[effectIndex],
+                                         static_cast<uint16_t>(timeoutMs))) {
+                ALOGE("Failed to edit flip's effect %d (%d): %s", effectIndex, errno,
+                      strerror(errno));
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+            }
+        }
+    }
+
+    {
+        const std::scoped_lock<std::mutex> lock(mActiveId_mutex);
+        /* Play the event now. */
+        mActiveId = effectIndex;
+        if (!mGPIOStatus) {
+            ALOGE("GetVibrator: GPIO status error");
+            // Do playcode to play effect
+            if (!mHwApiDef->setFFPlay(mInputFd, effectIndex, true)) {
+                ALOGE("Failed to play effect %d (%d): %s", effectIndex, errno, strerror(errno));
+                mActiveId = -1;
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+            }
+            if (mIsDual && !mHwApiDual->setFFPlay(mInputFdDual, effectIndex, true)) {
+                ALOGE("Failed to play flip's effect %d (%d): %s", effectIndex, errno,
+                      strerror(errno));
+                mActiveId = -1;
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+            }
+        } else {
+            // Using GPIO to play effect
+            if ((effectIndex == WAVEFORM_CLICK_INDEX || effectIndex == WAVEFORM_LIGHT_TICK_INDEX)) {
+                mFfEffects[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+                if (!mHwApiDef->setFFEffect(mInputFd, &mFfEffects[effectIndex],
+                                            mFfEffects[effectIndex].replay.length)) {
+                    ALOGE("Failed to edit effect %d (%d): %s", effectIndex, errno, strerror(errno));
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+                }
+                if (mIsDual) {
+                    mFfEffectsDual[effectIndex].trigger.button = GPIO_TRIGGER_CONFIG | effectIndex;
+                    if (!mHwApiDual->setFFEffect(mInputFdDual, &mFfEffectsDual[effectIndex],
+                                                 mFfEffectsDual[effectIndex].replay.length)) {
+                        ALOGE("Failed to edit flip's effect %d (%d): %s", effectIndex, errno,
+                              strerror(errno));
+                        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+                    }
+                }
+            }
+            if (!mHwGPIO->setGPIOOutput(true)) {
+                ALOGE("Failed to trigger effect %d (%d) by GPIO: %s", effectIndex, errno,
+                      strerror(errno));
+                return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+            }
+        }
+    }
+
+    mAsyncHandle = std::async(&Vibrator::waitForComplete, this, callback);
+    ALOGD("Vibrator::on, set done.");
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::setEffectAmplitude(float amplitude, float maximum) {
+    uint16_t scale = amplitudeToScale(amplitude, maximum);
+    if (!mHwApiDef->setFFGain(mInputFd, scale)) {
+        ALOGE("Failed to set the gain to %u (%d): %s", scale, errno, strerror(errno));
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+    if (mIsDual) {
+        if (!mHwApiDual->setFFGain(mInputFdDual, scale)) {
+            ALOGE("Failed to set flip's gain to %u (%d): %s", scale, errno, strerror(errno));
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+        }
+    }
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::setGlobalAmplitude(bool set) {
+    uint8_t amplitude = set ? roundf(mLongEffectScale * mLongEffectVol[1]) : VOLTAGE_SCALE_MAX;
+    if (!set) {
+        mLongEffectScale = 1.0;  // Reset the scale for the later new effect.
+    }
+
+    return setEffectAmplitude(amplitude, VOLTAGE_SCALE_MAX);
+}
+
+ndk::ScopedAStatus Vibrator::getSupportedAlwaysOnEffects(std::vector<Effect> * /*_aidl_return*/) {
+    return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+}
+
+ndk::ScopedAStatus Vibrator::alwaysOnEnable(int32_t /*id*/, Effect /*effect*/,
+                                            EffectStrength /*strength*/) {
+    return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+}
+ndk::ScopedAStatus Vibrator::alwaysOnDisable(int32_t /*id*/) {
+    return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+}
+
+ndk::ScopedAStatus Vibrator::getResonantFrequency(float *resonantFreqHz) {
+    std::string caldata{8, '0'};
+    if (!mHwCalDef->getF0(&caldata)) {
+        ALOGE("Failed to get resonant frequency (%d): %s", errno, strerror(errno));
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+    *resonantFreqHz = static_cast<float>(std::stoul(caldata, nullptr, 16)) / (1 << Q14_BIT_SHIFT);
+
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getQFactor(float *qFactor) {
+    std::string caldata{8, '0'};
+    if (!mHwCalDef->getQ(&caldata)) {
+        ALOGE("Failed to get q factor (%d): %s", errno, strerror(errno));
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_STATE);
+    }
+    *qFactor = static_cast<float>(std::stoul(caldata, nullptr, 16)) / (1 << Q16_BIT_SHIFT);
+
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getFrequencyResolution(float *freqResolutionHz) {
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_FREQUENCY_CONTROL) {
+        *freqResolutionHz = PWLE_FREQUENCY_RESOLUTION_HZ;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getFrequencyMinimum(float *freqMinimumHz) {
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_FREQUENCY_CONTROL) {
+        *freqMinimumHz = PWLE_FREQUENCY_MIN_HZ;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getBandwidthAmplitudeMap(std::vector<float> *_aidl_return) {
+    // TODO(b/170919640): complete implementation
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_FREQUENCY_CONTROL) {
+        std::vector<float> bandwidthAmplitudeMap(PWLE_BW_MAP_SIZE, 1.0);
+        *_aidl_return = bandwidthAmplitudeMap;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getPwlePrimitiveDurationMax(int32_t *durationMs) {
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_COMPOSE_PWLE_EFFECTS) {
+        *durationMs = COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getPwleCompositionSizeMax(int32_t *maxSize) {
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_COMPOSE_PWLE_EFFECTS) {
+        *maxSize = COMPOSE_PWLE_SIZE_MAX_DEFAULT;
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+ndk::ScopedAStatus Vibrator::getSupportedBraking(std::vector<Braking> *supported) {
+    int32_t capabilities;
+    Vibrator::getCapabilities(&capabilities);
+    if (capabilities & IVibrator::CAP_COMPOSE_PWLE_EFFECTS) {
+        *supported = {
+                Braking::NONE,
+        };
+        return ndk::ScopedAStatus::ok();
+    } else {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+}
+
+static void resetPreviousEndAmplitudeEndFrequency(float *prevEndAmplitude,
+                                                  float *prevEndFrequency) {
+    const float reset = -1.0;
+    *prevEndAmplitude = reset;
+    *prevEndFrequency = reset;
+}
+
+static void incrementIndex(int *index) {
+    *index += 1;
+}
+
+static void constructPwleSegment(dspmem_chunk *ch, uint16_t delay, uint16_t amplitude,
+                                 uint16_t frequency, uint8_t flags, uint32_t vbemfTarget = 0) {
+    dspmem_chunk_write(ch, 16, delay);
+    dspmem_chunk_write(ch, 12, amplitude);
+    dspmem_chunk_write(ch, 12, frequency);
+    /* feature flags to control the chirp, CLAB braking, back EMF amplitude regulation */
+    dspmem_chunk_write(ch, 8, (flags | 1) << 4);
+    if (flags & PWLE_AMP_REG_BIT) {
+        dspmem_chunk_write(ch, 24, vbemfTarget); /* target back EMF voltage */
+    }
+}
+
+static int constructActiveSegment(dspmem_chunk *ch, int duration, float amplitude, float frequency,
+                                  bool chirp) {
+    uint16_t delay = 0;
+    uint16_t amp = 0;
+    uint16_t freq = 0;
+    uint8_t flags = 0x0;
+    if ((floatToUint16(duration, &delay, 4, 0.0f, COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS) < 0) ||
+        (floatToUint16(amplitude, &amp, 2048, CS40L26_PWLE_LEVEL_MIX, CS40L26_PWLE_LEVEL_MAX) <
+         0) ||
+        (floatToUint16(frequency, &freq, 4, PWLE_FREQUENCY_MIN_HZ, PWLE_FREQUENCY_MAX_HZ) < 0)) {
+        ALOGE("Invalid argument: %d, %f, %f", duration, amplitude, frequency);
+        return -ERANGE;
+    }
+    if (chirp) {
+        flags |= PWLE_CHIRP_BIT;
+    }
+    constructPwleSegment(ch, delay, amp, freq, flags, 0 /*ignored*/);
+    return 0;
+}
+
+static int constructBrakingSegment(dspmem_chunk *ch, int duration, Braking brakingType) {
+    uint16_t delay = 0;
+    uint16_t freq = 0;
+    uint8_t flags = 0x00;
+    if (floatToUint16(duration, &delay, 4, 0.0f, COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS) < 0) {
+        ALOGE("Invalid argument: %d", duration);
+        return -ERANGE;
+    }
+    floatToUint16(PWLE_FREQUENCY_MIN_HZ, &freq, 4, PWLE_FREQUENCY_MIN_HZ, PWLE_FREQUENCY_MAX_HZ);
+    if (static_cast<std::underlying_type<Braking>::type>(brakingType)) {
+        flags |= PWLE_BRAKE_BIT;
+    }
+
+    constructPwleSegment(ch, delay, 0 /*ignored*/, freq, flags, 0 /*ignored*/);
+    return 0;
+}
+
+static void updateWLength(dspmem_chunk *ch, uint32_t totalDuration) {
+    totalDuration *= 8;            /* Unit: 0.125 ms (since wlength played @ 8kHz). */
+    totalDuration |= WT_LEN_CALCD; /* Bit 23 is for WT_LEN_CALCD; Bit 22 is for WT_INDEFINITE. */
+    *(ch->head + 0) = (totalDuration >> 24) & 0xFF;
+    *(ch->head + 1) = (totalDuration >> 16) & 0xFF;
+    *(ch->head + 2) = (totalDuration >> 8) & 0xFF;
+    *(ch->head + 3) = totalDuration & 0xFF;
+}
+
+static void updateNSection(dspmem_chunk *ch, int segmentIdx) {
+    *(ch->head + 7) |= (0xF0 & segmentIdx) >> 4; /* Bit 4 to 7 */
+    *(ch->head + 9) |= (0x0F & segmentIdx) << 4; /* Bit 3 to 0 */
+}
+
+ndk::ScopedAStatus Vibrator::composePwle(const std::vector<PrimitivePwle> &composite,
+                                         const std::shared_ptr<IVibratorCallback> &callback) {
+    ATRACE_NAME("Vibrator::composePwle");
+    int32_t capabilities;
+
+    Vibrator::getCapabilities(&capabilities);
+    if ((capabilities & IVibrator::CAP_COMPOSE_PWLE_EFFECTS) == 0) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    if (composite.empty() || composite.size() > COMPOSE_PWLE_SIZE_MAX_DEFAULT) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+
+    std::vector<Braking> supported;
+    Vibrator::getSupportedBraking(&supported);
+    bool isClabSupported =
+            std::find(supported.begin(), supported.end(), Braking::CLAB) != supported.end();
+
+    int segmentIdx = 0;
+    uint32_t totalDuration = 0;
+    float prevEndAmplitude;
+    float prevEndFrequency;
+    resetPreviousEndAmplitudeEndFrequency(&prevEndAmplitude, &prevEndFrequency);
+    auto ch = dspmem_chunk_create(new uint8_t[FF_CUSTOM_DATA_LEN_MAX_PWLE]{0x00},
+                                  FF_CUSTOM_DATA_LEN_MAX_PWLE);
+    bool chirp = false;
+
+    dspmem_chunk_write(ch, 24, 0x000000); /* Waveform length placeholder */
+    dspmem_chunk_write(ch, 8, 0);         /* Repeat */
+    dspmem_chunk_write(ch, 12, 0);        /* Wait time between repeats */
+    dspmem_chunk_write(ch, 8, 0x00);      /* nsections placeholder */
+
+    for (auto &e : composite) {
+        switch (e.getTag()) {
+            case PrimitivePwle::active: {
+                auto active = e.get<PrimitivePwle::active>();
+                if (active.duration < 0 ||
+                    active.duration > COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+                if (active.startAmplitude < PWLE_LEVEL_MIN ||
+                    active.startAmplitude > PWLE_LEVEL_MAX ||
+                    active.endAmplitude < PWLE_LEVEL_MIN || active.endAmplitude > PWLE_LEVEL_MAX) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+                if (active.startAmplitude > CS40L26_PWLE_LEVEL_MAX) {
+                    active.startAmplitude = CS40L26_PWLE_LEVEL_MAX;
+                }
+                if (active.endAmplitude > CS40L26_PWLE_LEVEL_MAX) {
+                    active.endAmplitude = CS40L26_PWLE_LEVEL_MAX;
+                }
+
+                if (active.startFrequency < PWLE_FREQUENCY_MIN_HZ ||
+                    active.startFrequency > PWLE_FREQUENCY_MAX_HZ ||
+                    active.endFrequency < PWLE_FREQUENCY_MIN_HZ ||
+                    active.endFrequency > PWLE_FREQUENCY_MAX_HZ) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+
+                if (!((active.startAmplitude == prevEndAmplitude) &&
+                      (active.startFrequency == prevEndFrequency))) {
+                    if (constructActiveSegment(ch, 0, active.startAmplitude, active.startFrequency,
+                                               false) < 0) {
+                        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                    }
+                    incrementIndex(&segmentIdx);
+                }
+
+                if (active.startFrequency != active.endFrequency) {
+                    chirp = true;
+                }
+                if (constructActiveSegment(ch, active.duration, active.endAmplitude,
+                                           active.endFrequency, chirp) < 0) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+                incrementIndex(&segmentIdx);
+
+                prevEndAmplitude = active.endAmplitude;
+                prevEndFrequency = active.endFrequency;
+                totalDuration += active.duration;
+                chirp = false;
+                break;
+            }
+            case PrimitivePwle::braking: {
+                auto braking = e.get<PrimitivePwle::braking>();
+                if (braking.braking > Braking::CLAB) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                } else if (!isClabSupported && (braking.braking == Braking::CLAB)) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+
+                if (braking.duration > COMPOSE_PWLE_PRIMITIVE_DURATION_MAX_MS) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+
+                if (constructBrakingSegment(ch, 0, braking.braking) < 0) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+                incrementIndex(&segmentIdx);
+
+                if (constructBrakingSegment(ch, braking.duration, braking.braking) < 0) {
+                    return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+                }
+                incrementIndex(&segmentIdx);
+
+                resetPreviousEndAmplitudeEndFrequency(&prevEndAmplitude, &prevEndFrequency);
+                totalDuration += braking.duration;
+                break;
+            }
+        }
+
+        if (segmentIdx > COMPOSE_PWLE_SIZE_MAX_DEFAULT) {
+            ALOGE("Too many PrimitivePwle section!");
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        }
+    }
+    dspmem_chunk_flush(ch);
+
+    /* Update wlength */
+    totalDuration += MAX_COLD_START_LATENCY_MS;
+    if (totalDuration > 0x7FFFF) {
+        ALOGE("Total duration is too long (%d)!", totalDuration);
+        return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+    }
+    updateWLength(ch, totalDuration);
+
+    /* Update nsections */
+    updateNSection(ch, segmentIdx);
+
+    return performEffect(WAVEFORM_MAX_INDEX /*ignored*/, VOLTAGE_SCALE_MAX /*ignored*/, ch,
+                         callback);
+}
+
+bool Vibrator::isUnderExternalControl() {
+    return mIsUnderExternalControl;
+}
+
+// BnCInterface APIs
+
+binder_status_t Vibrator::dump(int fd, const char **args, uint32_t numArgs) {
+    if (fd < 0) {
+        ALOGE("Called debug() with invalid fd.");
+        return STATUS_OK;
+    }
+
+    (void)args;
+    (void)numArgs;
+
+    dprintf(fd, "AIDL:\n");
+
+    dprintf(fd, "  F0 Offset: base: %" PRIu32 " flip: %" PRIu32 "\n", mF0Offset, mF0OffsetDual);
+
+    dprintf(fd, "  Voltage Levels:\n");
+    dprintf(fd, "     Tick Effect Min: %" PRIu32 " Max: %" PRIu32 "\n", mTickEffectVol[0],
+            mTickEffectVol[1]);
+    dprintf(fd, "     Click Effect Min: %" PRIu32 " Max: %" PRIu32 "\n", mClickEffectVol[0],
+            mClickEffectVol[1]);
+    dprintf(fd, "     Long Effect Min: %" PRIu32 " Max: %" PRIu32 "\n", mLongEffectVol[0],
+            mLongEffectVol[1]);
+
+    dprintf(fd, "  FF effect:\n");
+    dprintf(fd, "    Physical waveform:\n");
+    dprintf(fd, "==== Base ====\n\tId\tIndex\tt   ->\tt'\ttrigger button\n");
+    uint8_t effectId;
+    for (effectId = 0; effectId < WAVEFORM_MAX_PHYSICAL_INDEX; effectId++) {
+        dprintf(fd, "\t%d\t%d\t%d\t%d\t%X\n", mFfEffects[effectId].id,
+                mFfEffects[effectId].u.periodic.custom_data[1], mEffectDurations[effectId],
+                mFfEffects[effectId].replay.length, mFfEffects[effectId].trigger.button);
+    }
+    if (mIsDual) {
+        dprintf(fd, "==== Flip ====\n\tId\tIndex\tt   ->\tt'\ttrigger button\n");
+        for (effectId = 0; effectId < WAVEFORM_MAX_PHYSICAL_INDEX; effectId++) {
+            dprintf(fd, "\t%d\t%d\t%d\t%d\t%X\n", mFfEffectsDual[effectId].id,
+                    mFfEffectsDual[effectId].u.periodic.custom_data[1], mEffectDurations[effectId],
+                    mFfEffectsDual[effectId].replay.length,
+                    mFfEffectsDual[effectId].trigger.button);
+        }
+    }
+
+    dprintf(fd, "Base: OWT waveform:\n");
+    dprintf(fd, "\tId\tBytes\tData\tt\ttrigger button\n");
+    for (effectId = WAVEFORM_MAX_PHYSICAL_INDEX; effectId < WAVEFORM_MAX_INDEX; effectId++) {
+        uint32_t numBytes = mFfEffects[effectId].u.periodic.custom_len * 2;
+        std::stringstream ss;
+        ss << " ";
+        for (int i = 0; i < numBytes; i++) {
+            ss << std::uppercase << std::setfill('0') << std::setw(2) << std::hex
+               << (uint16_t)(*(
+                          reinterpret_cast<uint8_t *>(mFfEffects[effectId].u.periodic.custom_data) +
+                          i))
+               << " ";
+        }
+        dprintf(fd, "\t%d\t%d\t{%s}\t%u\t%X\n", mFfEffects[effectId].id, numBytes, ss.str().c_str(),
+                mFfEffectsDual[effectId].replay.length, mFfEffects[effectId].trigger.button);
+    }
+    if (mIsDual) {
+        dprintf(fd, "Flip: OWT waveform:\n");
+        dprintf(fd, "\tId\tBytes\tData\tt\ttrigger button\n");
+        for (effectId = WAVEFORM_MAX_PHYSICAL_INDEX; effectId < WAVEFORM_MAX_INDEX; effectId++) {
+            uint32_t numBytes = mFfEffectsDual[effectId].u.periodic.custom_len * 2;
+            std::stringstream ss;
+            ss << " ";
+            for (int i = 0; i < numBytes; i++) {
+                ss << std::uppercase << std::setfill('0') << std::setw(2) << std::hex
+                   << (uint16_t)(*(reinterpret_cast<uint8_t *>(
+                                           mFfEffectsDual[effectId].u.periodic.custom_data) +
+                                   i))
+                   << " ";
+            }
+            dprintf(fd, "\t%d\t%d\t{%s}\t%u\t%X\n", mFfEffectsDual[effectId].id, numBytes,
+                    ss.str().c_str(), mFfEffectsDual[effectId].replay.length,
+                    mFfEffectsDual[effectId].trigger.button);
+        }
+    }
+    dprintf(fd, "\n");
+    dprintf(fd, "\n");
+
+    mHwApiDef->debug(fd);
+
+    dprintf(fd, "\n");
+
+    mHwCalDef->debug(fd);
+
+    if (mIsDual) {
+        mHwApiDual->debug(fd);
+        dprintf(fd, "\n");
+        mHwCalDual->debug(fd);
+    }
+
+    fsync(fd);
+    return STATUS_OK;
+}
+
+bool Vibrator::hasHapticAlsaDevice() {
+    // We need to call findHapticAlsaDevice once only. Calling in the
+    // constructor is too early in the boot process and the pcm file contents
+    // are empty. Hence we make the call here once only right before we need to.
+    if (!mConfigHapticAlsaDeviceDone) {
+        if (mHwApiDef->getHapticAlsaDevice(&mCard, &mDevice)) {
+            mHasHapticAlsaDevice = true;
+            mConfigHapticAlsaDeviceDone = true;
+        } else {
+            ALOGE("Haptic ALSA device not supported");
+        }
+    } else {
+        ALOGD("Haptic ALSA device configuration done.");
+    }
+    return mHasHapticAlsaDevice;
+}
+
+ndk::ScopedAStatus Vibrator::getSimpleDetails(Effect effect, EffectStrength strength,
+                                              uint32_t *outEffectIndex, uint32_t *outTimeMs,
+                                              uint32_t *outVolLevel) {
+    uint32_t effectIndex;
+    uint32_t timeMs;
+    float intensity;
+    uint32_t volLevel;
+    switch (strength) {
+        case EffectStrength::LIGHT:
+            intensity = 0.5f;
+            break;
+        case EffectStrength::MEDIUM:
+            intensity = 0.7f;
+            break;
+        case EffectStrength::STRONG:
+            intensity = 1.0f;
+            break;
+        default:
+            return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    switch (effect) {
+        case Effect::TEXTURE_TICK:
+            effectIndex = WAVEFORM_LIGHT_TICK_INDEX;
+            intensity *= 0.5f;
+            break;
+        case Effect::TICK:
+            effectIndex = WAVEFORM_CLICK_INDEX;
+            intensity *= 0.5f;
+            break;
+        case Effect::CLICK:
+            effectIndex = WAVEFORM_CLICK_INDEX;
+            intensity *= 0.7f;
+            break;
+        case Effect::HEAVY_CLICK:
+            effectIndex = WAVEFORM_CLICK_INDEX;
+            intensity *= 1.0f;
+            // WAVEFORM_CLICK_INDEX is 2, but the primitive CLICK index is 1.
+            if (intensity > mPrimitiveMaxScale[WAVEFORM_CLICK_INDEX - 1]) {
+                intensity = mPrimitiveMaxScale[WAVEFORM_CLICK_INDEX - 1];
+            }
+            break;
+        default:
+            return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    volLevel = intensityToVolLevel(intensity, effectIndex);
+    timeMs = mEffectDurations[effectIndex] + MAX_COLD_START_LATENCY_MS;
+
+    *outEffectIndex = effectIndex;
+    *outTimeMs = timeMs;
+    *outVolLevel = volLevel;
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getCompoundDetails(Effect effect, EffectStrength strength,
+                                                uint32_t *outTimeMs, dspmem_chunk *outCh) {
+    ndk::ScopedAStatus status;
+    uint32_t timeMs = 0;
+    uint32_t thisEffectIndex;
+    uint32_t thisTimeMs;
+    uint32_t thisVolLevel;
+    switch (effect) {
+        case Effect::DOUBLE_CLICK:
+            dspmem_chunk_write(outCh, 8, 0); /* Padding */
+            dspmem_chunk_write(outCh, 8, 2); /* nsections */
+            dspmem_chunk_write(outCh, 8, 0); /* repeat */
+
+            status = getSimpleDetails(Effect::CLICK, strength, &thisEffectIndex, &thisTimeMs,
+                                      &thisVolLevel);
+            if (!status.isOk()) {
+                return status;
+            }
+            timeMs += thisTimeMs;
+
+            dspmem_chunk_write(outCh, 8, (uint8_t)(0xFF & thisVolLevel));    /* amplitude */
+            dspmem_chunk_write(outCh, 8, (uint8_t)(0xFF & thisEffectIndex)); /* index */
+            dspmem_chunk_write(outCh, 8, 0);                                 /* repeat */
+            dspmem_chunk_write(outCh, 8, 0);                                 /* flags */
+            dspmem_chunk_write(outCh, 16,
+                               (uint16_t)(0xFFFF & WAVEFORM_DOUBLE_CLICK_SILENCE_MS)); /* delay */
+
+            timeMs += WAVEFORM_DOUBLE_CLICK_SILENCE_MS + MAX_PAUSE_TIMING_ERROR_MS;
+
+            status = getSimpleDetails(Effect::HEAVY_CLICK, strength, &thisEffectIndex, &thisTimeMs,
+                                      &thisVolLevel);
+            if (!status.isOk()) {
+                return status;
+            }
+            timeMs += thisTimeMs;
+
+            dspmem_chunk_write(outCh, 8, (uint8_t)(0xFF & thisVolLevel));    /* amplitude */
+            dspmem_chunk_write(outCh, 8, (uint8_t)(0xFF & thisEffectIndex)); /* index */
+            dspmem_chunk_write(outCh, 8, 0);                                 /* repeat */
+            dspmem_chunk_write(outCh, 8, 0);                                 /* flags */
+            dspmem_chunk_write(outCh, 16, 0);                                /* delay */
+            dspmem_chunk_flush(outCh);
+
+            break;
+        default:
+            return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    *outTimeMs = timeMs;
+    mFfEffects[WAVEFORM_COMPOSE].replay.length = static_cast<uint16_t>(timeMs);
+    if (mIsDual) {
+        mFfEffectsDual[WAVEFORM_COMPOSE].replay.length = static_cast<uint16_t>(timeMs);
+    }
+
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::getPrimitiveDetails(CompositePrimitive primitive,
+                                                 uint32_t *outEffectIndex) {
+    uint32_t effectIndex;
+    uint32_t primitiveBit = 1 << int32_t(primitive);
+    if ((primitiveBit & mSupportedPrimitivesBits) == 0x0) {
+        return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    switch (primitive) {
+        case CompositePrimitive::NOOP:
+            return ndk::ScopedAStatus::fromExceptionCode(EX_ILLEGAL_ARGUMENT);
+        case CompositePrimitive::CLICK:
+            effectIndex = WAVEFORM_CLICK_INDEX;
+            break;
+        case CompositePrimitive::THUD:
+            effectIndex = WAVEFORM_THUD_INDEX;
+            break;
+        case CompositePrimitive::SPIN:
+            effectIndex = WAVEFORM_SPIN_INDEX;
+            break;
+        case CompositePrimitive::QUICK_RISE:
+            effectIndex = WAVEFORM_QUICK_RISE_INDEX;
+            break;
+        case CompositePrimitive::SLOW_RISE:
+            effectIndex = WAVEFORM_SLOW_RISE_INDEX;
+            break;
+        case CompositePrimitive::QUICK_FALL:
+            effectIndex = WAVEFORM_QUICK_FALL_INDEX;
+            break;
+        case CompositePrimitive::LIGHT_TICK:
+            effectIndex = WAVEFORM_LIGHT_TICK_INDEX;
+            break;
+        case CompositePrimitive::LOW_TICK:
+            effectIndex = WAVEFORM_LOW_TICK_INDEX;
+            break;
+        default:
+            return ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+    }
+
+    *outEffectIndex = effectIndex;
+
+    return ndk::ScopedAStatus::ok();
+}
+
+ndk::ScopedAStatus Vibrator::performEffect(Effect effect, EffectStrength strength,
+                                           const std::shared_ptr<IVibratorCallback> &callback,
+                                           int32_t *outTimeMs) {
+    ndk::ScopedAStatus status;
+    uint32_t effectIndex;
+    uint32_t timeMs = 0;
+    uint32_t volLevel;
+    dspmem_chunk *ch = nullptr;
+    switch (effect) {
+        case Effect::TEXTURE_TICK:
+            // fall-through
+        case Effect::TICK:
+            // fall-through
+        case Effect::CLICK:
+            // fall-through
+        case Effect::HEAVY_CLICK:
+            status = getSimpleDetails(effect, strength, &effectIndex, &timeMs, &volLevel);
+            break;
+        case Effect::DOUBLE_CLICK:
+            ch = dspmem_chunk_create(new uint8_t[FF_CUSTOM_DATA_LEN_MAX_COMP]{0x00},
+                                     FF_CUSTOM_DATA_LEN_MAX_COMP);
+            status = getCompoundDetails(effect, strength, &timeMs, ch);
+            volLevel = VOLTAGE_SCALE_MAX;
+            break;
+        default:
+            status = ndk::ScopedAStatus::fromExceptionCode(EX_UNSUPPORTED_OPERATION);
+            break;
+    }
+    if (!status.isOk()) {
+        goto exit;
+    }
+
+    status = performEffect(effectIndex, volLevel, ch, callback);
+
+exit:
+    *outTimeMs = timeMs;
+    return status;
+}
+
+ndk::ScopedAStatus Vibrator::performEffect(uint32_t effectIndex, uint32_t volLevel,
+                                           dspmem_chunk *ch,
+                                           const std::shared_ptr<IVibratorCallback> &callback) {
+    setEffectAmplitude(volLevel, VOLTAGE_SCALE_MAX);
+
+    return on(MAX_TIME_MS, effectIndex, ch, callback);
+}
+
+void Vibrator::waitForComplete(std::shared_ptr<IVibratorCallback> &&callback) {
+    ALOGD("waitForComplete: Callback status in waitForComplete(): callBack: %d",
+          (callback != nullptr));
+
+    // Bypass checking flip part's haptic state
+    if (!mHwApiDef->pollVibeState(VIBE_STATE_HAPTIC, POLLING_TIMEOUT)) {
+        ALOGD("Failed to get state \"Haptic\"");
+    }
+
+    mHwApiDef->pollVibeState(VIBE_STATE_STOPPED);
+    // Check flip's state after base was done
+    if (mIsDual) {
+        mHwApiDual->pollVibeState(VIBE_STATE_STOPPED);
+    }
+    ALOGD("waitForComplete: get STOP");
+    {
+        const std::scoped_lock<std::mutex> lock(mActiveId_mutex);
+        if (mActiveId >= WAVEFORM_MAX_PHYSICAL_INDEX) {
+            if (!mHwApiDef->eraseOwtEffect(mInputFd, mActiveId, &mFfEffects)) {
+                ALOGE("Failed to clean up the composed effect %d", mActiveId);
+            }
+            if (mIsDual &&
+                (!mHwApiDual->eraseOwtEffect(mInputFdDual, mActiveId, &mFfEffectsDual))) {
+                ALOGE("Failed to clean up flip's composed effect %d", mActiveId);
+            }
+        } else {
+            ALOGD("waitForComplete: Vibrator is already off");
+        }
+        mActiveId = -1;
+        if (mGPIOStatus && !mHwGPIO->setGPIOOutput(false)) {
+            ALOGE("waitForComplete: Failed to reset GPIO(%d): %s", errno, strerror(errno));
+        }
+        // Do waveform number checking
+        uint32_t effectCount = WAVEFORM_MAX_PHYSICAL_INDEX;
+        mHwApiDef->getEffectCount(&effectCount);
+        if (effectCount > WAVEFORM_MAX_PHYSICAL_INDEX) {
+            // Forcibly clean all OWT waveforms
+            if (!mHwApiDef->eraseOwtEffect(mInputFd, WAVEFORM_MAX_INDEX, &mFfEffects)) {
+                ALOGE("Failed to clean up all base's composed effect");
+            }
+        }
+
+        if (mIsDual) {
+            // Forcibly clean all OWT waveforms
+            effectCount = WAVEFORM_MAX_PHYSICAL_INDEX;
+            mHwApiDual->getEffectCount(&effectCount);
+            if ((effectCount > WAVEFORM_MAX_PHYSICAL_INDEX) &&
+                (!mHwApiDual->eraseOwtEffect(mInputFdDual, WAVEFORM_MAX_INDEX, &mFfEffectsDual))) {
+                ALOGE("Failed to clean up all flip's composed effect");
+            }
+        }
+    }
+
+    if (callback) {
+        auto ret = callback->onComplete();
+        if (!ret.isOk()) {
+            ALOGE("Failed completion callback: %d", ret.getExceptionCode());
+        }
+    }
+    ALOGD("waitForComplete: Done.");
+}
+
+uint32_t Vibrator::intensityToVolLevel(float intensity, uint32_t effectIndex) {
+    uint32_t volLevel;
+    auto calc = [](float intst, std::array<uint32_t, 2> v) -> uint32_t {
+        return std::lround(intst * (v[1] - v[0])) + v[0];
+    };
+
+    switch (effectIndex) {
+        case WAVEFORM_LIGHT_TICK_INDEX:
+            volLevel = calc(intensity, mTickEffectVol);
+            break;
+        case WAVEFORM_QUICK_RISE_INDEX:
+            // fall-through
+        case WAVEFORM_QUICK_FALL_INDEX:
+            volLevel = calc(intensity, mLongEffectVol);
+            break;
+        case WAVEFORM_CLICK_INDEX:
+            // fall-through
+        case WAVEFORM_THUD_INDEX:
+            // fall-through
+        case WAVEFORM_SPIN_INDEX:
+            // fall-through
+        case WAVEFORM_SLOW_RISE_INDEX:
+            // fall-through
+        default:
+            volLevel = calc(intensity, mClickEffectVol);
+            break;
+    }
+    return volLevel;
+}
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/Vibrator.h b/vibrator/cs40l26/Vibrator.h
new file mode 100644
index 0000000..5b1ff90
--- /dev/null
+++ b/vibrator/cs40l26/Vibrator.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#pragma once
+
+#include <aidl/android/hardware/vibrator/BnVibrator.h>
+#include <android-base/unique_fd.h>
+#include <linux/input.h>
+#include <tinyalsa/asoundlib.h>
+
+#include <array>
+#include <fstream>
+#include <future>
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+class Vibrator : public BnVibrator {
+  public:
+    // APIs for interfacing with the GPIO pin.
+    class HwGPIO {
+      public:
+        virtual ~HwGPIO() = default;
+        // Get the GPIO pin num and address shift information
+        virtual bool getGPIO() = 0;
+        // Init the GPIO function
+        virtual bool initGPIO() = 0;
+        // Trigger the GPIO pin to synchronize both vibrators's play
+        virtual bool setGPIOOutput(bool value) = 0;
+        // Emit diagnostic information to the given file.
+        virtual void debug(int fd) = 0;
+    };
+
+    // APIs for interfacing with the kernel driver.
+    class HwApi {
+      public:
+        virtual ~HwApi() = default;
+        // Stores the LRA resonant frequency to be used for PWLE playback
+        // and click compensation.
+        virtual bool setF0(std::string value) = 0;
+        // Stores the frequency offset for long vibrations.
+        virtual bool setF0Offset(uint32_t value) = 0;
+        // Stores the LRA series resistance to be used for click
+        // compensation.
+        virtual bool setRedc(std::string value) = 0;
+        // Stores the LRA Q factor to be used for Q-dependent waveform
+        // selection.
+        virtual bool setQ(std::string value) = 0;
+        // Reports the number of effect waveforms loaded in firmware.
+        virtual bool getEffectCount(uint32_t *value) = 0;
+        // Blocks until timeout or vibrator reaches desired state
+        // (2 = ASP enabled, 1 = haptic enabled, 0 = disabled).
+        virtual bool pollVibeState(uint32_t value, int32_t timeoutMs = -1) = 0;
+        // Reports whether getOwtFreeSpace() is supported.
+        virtual bool hasOwtFreeSpace() = 0;
+        // Reports the available OWT bytes.
+        virtual bool getOwtFreeSpace(uint32_t *value) = 0;
+        // Enables/Disables F0 compensation enable status
+        virtual bool setF0CompEnable(bool value) = 0;
+        // Enables/Disables Redc compensation enable status
+        virtual bool setRedcCompEnable(bool value) = 0;
+        // Stores the minumun delay time between playback and stop effects.
+        virtual bool setMinOnOffInterval(uint32_t value) = 0;
+        // Indicates the number of 0.125-dB steps of attenuation to apply to
+        // waveforms triggered in response to vibration calls from the
+        // Android vibrator HAL.
+        virtual bool setFFGain(int fd, uint16_t value) = 0;
+        // Create/modify custom effects for all physical waveforms.
+        virtual bool setFFEffect(int fd, struct ff_effect *effect, uint16_t timeoutMs) = 0;
+        // Activates/deactivates the effect index after setFFGain() and setFFEffect().
+        virtual bool setFFPlay(int fd, int8_t index, bool value) = 0;
+        // Get the Alsa device for the audio coupled haptics effect
+        virtual bool getHapticAlsaDevice(int *card, int *device) = 0;
+        // Set haptics PCM amplifier before triggering audio haptics feature
+        virtual bool setHapticPcmAmp(struct pcm **haptic_pcm, bool enable, int card,
+                                     int device) = 0;
+        // Set OWT waveform for compose or compose PWLE request
+        virtual bool uploadOwtEffect(int fd, uint8_t *owtData, uint32_t numBytes,
+                                     struct ff_effect *effect, uint32_t *outEffectIndex,
+                                     int *status) = 0;
+        // Erase OWT waveform
+        virtual bool eraseOwtEffect(int fd, int8_t effectIndex, std::vector<ff_effect> *effect) = 0;
+        // Emit diagnostic information to the given file.
+        virtual void debug(int fd) = 0;
+    };
+
+    // APIs for obtaining calibration/configuration data from persistent memory.
+    class HwCal {
+      public:
+        virtual ~HwCal() = default;
+        // Obtain the calibration version
+        virtual bool getVersion(uint32_t *value) = 0;
+        // Obtains the LRA resonant frequency to be used for PWLE playback
+        // and click compensation.
+        virtual bool getF0(std::string *value) = 0;
+        // Obtains the offset for actuator that will adjust configured F0 to target
+        // frequency for dual actuators
+        virtual bool getF0SyncOffset(uint32_t *value) = 0;
+        // Obtains the LRA series resistance to be used for click
+        // compensation.
+        virtual bool getRedc(std::string *value) = 0;
+        // Obtains the LRA Q factor to be used for Q-dependent waveform
+        // selection.
+        virtual bool getQ(std::string *value) = 0;
+        // Obtains frequency shift for long vibrations.
+        virtual bool getLongFrequencyShift(int32_t *value) = 0;
+        // Obtains the v0/v1(min/max) voltage levels to be applied for
+        // tick/click/long in units of 1%.
+        virtual bool getTickVolLevels(std::array<uint32_t, 2> *value) = 0;
+        virtual bool getClickVolLevels(std::array<uint32_t, 2> *value) = 0;
+        virtual bool getLongVolLevels(std::array<uint32_t, 2> *value) = 0;
+        // Checks if the chirp feature is enabled.
+        virtual bool isChirpEnabled() = 0;
+        // Obtains the supported primitive effects.
+        virtual bool getSupportedPrimitives(uint32_t *value) = 0;
+        // Checks if the f0 compensation feature needs to be enabled.
+        virtual bool isF0CompEnabled() = 0;
+        // Checks if the redc compensation feature needs to be enabled.
+        virtual bool isRedcCompEnabled() = 0;
+        // Emit diagnostic information to the given file.
+        virtual void debug(int fd) = 0;
+    };
+
+  public:
+    Vibrator(std::unique_ptr<HwApi> hwApiDefault, std::unique_ptr<HwCal> hwCalDefault,
+             std::unique_ptr<HwApi> hwApiDual, std::unique_ptr<HwCal> hwCalDual,
+             std::unique_ptr<HwGPIO> hwgpio);
+
+    // BnVibrator APIs
+    ndk::ScopedAStatus getCapabilities(int32_t *_aidl_return) override;
+    ndk::ScopedAStatus off() override;
+    ndk::ScopedAStatus on(int32_t timeoutMs,
+                          const std::shared_ptr<IVibratorCallback> &callback) override;
+    ndk::ScopedAStatus perform(Effect effect, EffectStrength strength,
+                               const std::shared_ptr<IVibratorCallback> &callback,
+                               int32_t *_aidl_return) override;
+    ndk::ScopedAStatus getSupportedEffects(std::vector<Effect> *_aidl_return) override;
+    ndk::ScopedAStatus setAmplitude(float amplitude) override;
+    ndk::ScopedAStatus setExternalControl(bool enabled) override;
+    ndk::ScopedAStatus getCompositionDelayMax(int32_t *maxDelayMs);
+    ndk::ScopedAStatus getCompositionSizeMax(int32_t *maxSize);
+    ndk::ScopedAStatus getSupportedPrimitives(std::vector<CompositePrimitive> *supported) override;
+    ndk::ScopedAStatus getPrimitiveDuration(CompositePrimitive primitive,
+                                            int32_t *durationMs) override;
+    ndk::ScopedAStatus compose(const std::vector<CompositeEffect> &composite,
+                               const std::shared_ptr<IVibratorCallback> &callback) override;
+    ndk::ScopedAStatus getSupportedAlwaysOnEffects(std::vector<Effect> *_aidl_return) override;
+    ndk::ScopedAStatus alwaysOnEnable(int32_t id, Effect effect, EffectStrength strength) override;
+    ndk::ScopedAStatus alwaysOnDisable(int32_t id) override;
+    ndk::ScopedAStatus getResonantFrequency(float *resonantFreqHz) override;
+    ndk::ScopedAStatus getQFactor(float *qFactor) override;
+    ndk::ScopedAStatus getFrequencyResolution(float *freqResolutionHz) override;
+    ndk::ScopedAStatus getFrequencyMinimum(float *freqMinimumHz) override;
+    ndk::ScopedAStatus getBandwidthAmplitudeMap(std::vector<float> *_aidl_return) override;
+    ndk::ScopedAStatus getPwlePrimitiveDurationMax(int32_t *durationMs) override;
+    ndk::ScopedAStatus getPwleCompositionSizeMax(int32_t *maxSize) override;
+    ndk::ScopedAStatus getSupportedBraking(std::vector<Braking> *supported) override;
+    ndk::ScopedAStatus composePwle(const std::vector<PrimitivePwle> &composite,
+                                   const std::shared_ptr<IVibratorCallback> &callback) override;
+
+    // BnCInterface APIs
+    binder_status_t dump(int fd, const char **args, uint32_t numArgs) override;
+
+    static constexpr uint32_t MIN_ON_OFF_INTERVAL_US = 8500;  // SVC initialization time
+
+  private:
+    ndk::ScopedAStatus on(uint32_t timeoutMs, uint32_t effectIndex, struct dspmem_chunk *ch,
+                          const std::shared_ptr<IVibratorCallback> &callback);
+    // set 'amplitude' based on an arbitrary scale determined by 'maximum'
+    ndk::ScopedAStatus setEffectAmplitude(float amplitude, float maximum);
+    ndk::ScopedAStatus setGlobalAmplitude(bool set);
+    // 'simple' effects are those precompiled and loaded into the controller
+    ndk::ScopedAStatus getSimpleDetails(Effect effect, EffectStrength strength,
+                                        uint32_t *outEffectIndex, uint32_t *outTimeMs,
+                                        uint32_t *outVolLevel);
+    // 'compound' effects are those composed by stringing multiple 'simple' effects
+    ndk::ScopedAStatus getCompoundDetails(Effect effect, EffectStrength strength,
+                                          uint32_t *outTimeMs, struct dspmem_chunk *outCh);
+    ndk::ScopedAStatus getPrimitiveDetails(CompositePrimitive primitive, uint32_t *outEffectIndex);
+    ndk::ScopedAStatus performEffect(Effect effect, EffectStrength strength,
+                                     const std::shared_ptr<IVibratorCallback> &callback,
+                                     int32_t *outTimeMs);
+    ndk::ScopedAStatus performEffect(uint32_t effectIndex, uint32_t volLevel,
+                                     struct dspmem_chunk *ch,
+                                     const std::shared_ptr<IVibratorCallback> &callback);
+    ndk::ScopedAStatus setPwle(const std::string &pwleQueue);
+    bool isUnderExternalControl();
+    void waitForComplete(std::shared_ptr<IVibratorCallback> &&callback);
+    uint32_t intensityToVolLevel(float intensity, uint32_t effectIndex);
+    bool findHapticAlsaDevice(int *card, int *device);
+    bool hasHapticAlsaDevice();
+    bool enableHapticPcmAmp(struct pcm **haptic_pcm, bool enable, int card, int device);
+
+    std::unique_ptr<HwApi> mHwApiDef;
+    std::unique_ptr<HwCal> mHwCalDef;
+    std::unique_ptr<HwApi> mHwApiDual;
+    std::unique_ptr<HwCal> mHwCalDual;
+    std::unique_ptr<HwGPIO> mHwGPIO;
+    uint32_t mF0Offset;
+    uint32_t mF0OffsetDual;
+    std::array<uint32_t, 2> mTickEffectVol;
+    std::array<uint32_t, 2> mClickEffectVol;
+    std::array<uint32_t, 2> mLongEffectVol;
+    std::vector<ff_effect> mFfEffects;
+    std::vector<ff_effect> mFfEffectsDual;
+    std::vector<uint32_t> mEffectDurations;
+    std::future<void> mAsyncHandle;
+    ::android::base::unique_fd mInputFd;
+    ::android::base::unique_fd mInputFdDual;
+    int8_t mActiveId{-1};
+    struct pcm *mHapticPcm;
+    int mCard;
+    int mDevice;
+    bool mHasHapticAlsaDevice{false};
+    bool mIsUnderExternalControl;
+    float mLongEffectScale{1.0};
+    bool mIsChirpEnabled;
+    uint32_t mSupportedPrimitivesBits = 0x0;
+    std::vector<CompositePrimitive> mSupportedPrimitives;
+    std::vector<float> mPrimitiveMaxScale;
+    std::vector<float> mPrimitiveMinScale;
+    bool mConfigHapticAlsaDeviceDone{false};
+    bool mGPIOStatus;
+    bool mIsDual{false};
+    std::mutex mActiveId_mutex;  // protects mActiveId
+};
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.rc b/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.rc
new file mode 100644
index 0000000..2799cdc
--- /dev/null
+++ b/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.rc
@@ -0,0 +1,65 @@
+on property:vendor.all.modules.ready=1
+    wait /sys/bus/i2c/devices/i2c-cs40l26a/calibration/redc_cal_time_ms
+
+    mkdir /mnt/vendor/persist/haptics 0770 system system
+    chmod 770 /mnt/vendor/persist/haptics
+    chmod 440 /mnt/vendor/persist/haptics/cs40l26.cal
+    chmod 440 /mnt/vendor/persist/haptics/cs40l26_dual.cal
+    chown system system /mnt/vendor/persist/haptics
+    chown system system /mnt/vendor/persist/haptics/cs40l26.cal
+    chown system system /mnt/vendor/persist/haptics/cs40l26_dual.cal
+
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/calibration/f0_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/calibration/f0_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/calibration/q_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/calibration/q_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/calibration/redc_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/calibration/redc_stored
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/vibe_state
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/vibe_state
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/num_waves
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/num_waves
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/f0_offset
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/f0_offset
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/owt_free_space
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/owt_free_space
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/f0_comp_enable
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/f0_comp_enable
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/redc_comp_enable
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/redc_comp_enable
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a/default/delay_before_stop_playback_us
+    chown system system /sys/bus/i2c/devices/i2c-cs40l26a-dual/default/delay_before_stop_playback_us
+    chown system system /dev/gpiochip44
+
+    enable vendor.vibrator.cs40l26
+
+service vendor.vibrator.cs40l26 /vendor/bin/hw/android.hardware.vibrator-service.cs40l26-private
+    class hal
+    user system
+    group system input
+
+    setenv HAPTIC_NAME Haptics
+    setenv INPUT_EVENT_NAME cs40l26_input
+    setenv INPUT_EVENT_NAME_DUAL cs40l26_dual_input
+    setenv INPUT_EVENT_PATH /dev/input/event*
+    setenv PROPERTY_PREFIX ro.vendor.vibrator.hal.
+    setenv CALIBRATION_FILEPATH /mnt/vendor/persist/haptics/cs40l26.cal
+    setenv CALIBRATION_FILEPATH_DUAL /mnt/vendor/persist/haptics/cs40l26_dual.cal
+
+    setenv HWAPI_PATH_PREFIX /sys/bus/i2c/devices/i2c-cs40l26a/
+    setenv HWAPI_PATH_PREFIX_DUAL /sys/bus/i2c/devices/i2c-cs40l26a-dual/
+    setenv HWAPI_DEBUG_PATHS "
+        calibration/f0_stored
+        calibration/redc_stored
+        calibration/q_stored
+        default/vibe_state
+        default/num_waves
+        default/f0_offset
+        default/owt_free_space
+        default/f0_comp_enable
+        default/redc_comp_enable
+        default/delay_before_stop_playback_us
+        "
+
+    disabled
+
diff --git a/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.xml b/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.xml
new file mode 100644
index 0000000..4db8f8c
--- /dev/null
+++ b/vibrator/cs40l26/android.hardware.vibrator-service.cs40l26-private.xml
@@ -0,0 +1,7 @@
+<manifest version="1.0" type="device">
+    <hal format="aidl">
+        <name>android.hardware.vibrator</name>
+        <version>2</version>
+        <fqname>IVibrator/default</fqname>
+    </hal>
+</manifest>
diff --git a/vibrator/cs40l26/device.mk b/vibrator/cs40l26/device.mk
new file mode 100644
index 0000000..2c4b2e2
--- /dev/null
+++ b/vibrator/cs40l26/device.mk
@@ -0,0 +1,6 @@
+PRODUCT_PACKAGES += \
+    android.hardware.vibrator-service.cs40l26-private
+
+BOARD_SEPOLICY_DIRS += \
+    hardware/google/pixel-sepolicy/vibrator/common \
+    hardware/google/pixel-sepolicy/vibrator/cs40l26
diff --git a/vibrator/cs40l26/service.cpp b/vibrator/cs40l26/service.cpp
new file mode 100644
index 0000000..605de43
--- /dev/null
+++ b/vibrator/cs40l26/service.cpp
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <android/binder_manager.h>
+#include <android/binder_process.h>
+#include <binder/IServiceManager.h>
+#include <binder/ProcessState.h>
+#include <log/log.h>
+
+#include "Hardware.h"
+#include "VibMgrHwApi.h"
+#include "Vibrator.h"
+
+using ::aidl::android::hardware::vibrator::HwApi;
+using ::aidl::android::hardware::vibrator::HwCal;
+using ::aidl::android::hardware::vibrator::VibMgrHwApi;
+using ::aidl::android::hardware::vibrator::Vibrator;
+using ::android::defaultServiceManager;
+using ::android::ProcessState;
+using ::android::sp;
+using ::android::String16;
+
+#if !defined(VIBRATOR_NAME)
+#define VIBRATOR_NAME "default"
+#endif
+
+int main() {
+    const char *hwApiPathPrefixDual = std::getenv("HWAPI_PATH_PREFIX_DUAL");
+    const char *calFilePath = std::getenv("CALIBRATION_FILEPATH");
+    const char *calFilePathDual = std::getenv("CALIBRATION_FILEPATH_DUAL");
+
+    auto hwgpio = VibMgrHwApi::Create();
+    if (!hwgpio) {
+        return EXIT_FAILURE;
+    }
+    auto hwApiDef = HwApi::Create();
+    if (!hwApiDef) {
+        return EXIT_FAILURE;
+    }
+    auto hwCalDef = HwCal::Create();
+    if (!hwCalDef) {
+        return EXIT_FAILURE;
+    }
+
+    std::shared_ptr<Vibrator> svc;
+    // Synchronize base and flip actuator F0.
+    // Replace dual cal file path to base and copy the base to dual's path.
+    if ((hwApiPathPrefixDual != nullptr) && !setenv("HWAPI_PATH_PREFIX", hwApiPathPrefixDual, 1) &&
+        (calFilePathDual != nullptr) && !setenv("CALIBRATION_FILEPATH", calFilePathDual, 1) &&
+        !setenv("CALIBRATION_FILEPATH_DUAL", calFilePath, 1)) {
+        ALOGD("Init dual HAL: %s", std::getenv("HWAPI_PATH_PREFIX"));
+        svc = ndk::SharedRefBase::make<Vibrator>(std::move(hwApiDef), std::move(hwCalDef),
+                                                 std::make_unique<HwApi>(),
+                                                 std::make_unique<HwCal>(), std::move(hwgpio));
+    } else {
+        ALOGD("Failed to init dual HAL");
+        svc = ndk::SharedRefBase::make<Vibrator>(std::move(hwApiDef), std::move(hwCalDef), nullptr,
+                                                 nullptr, std::move(hwgpio));
+    }
+
+    const auto svcName = std::string() + svc->descriptor + "/" + VIBRATOR_NAME;
+
+    ProcessState::initWithDriver("/dev/vndbinder");
+
+    auto svcBinder = svc->asBinder();
+    binder_status_t status = AServiceManager_addService(svcBinder.get(), svcName.c_str());
+    LOG_ALWAYS_FATAL_IF(status != STATUS_OK);
+
+    ProcessState::self()->setThreadPoolMaxThreadCount(1);
+    ProcessState::self()->startThreadPool();
+
+    ABinderProcess_setThreadPoolMaxThreadCount(0);
+    ABinderProcess_joinThreadPool();
+
+    return EXIT_FAILURE;  // should not reach
+}
diff --git a/vibrator/cs40l26/tests/Android.bp b/vibrator/cs40l26/tests/Android.bp
new file mode 100644
index 0000000..48baa90
--- /dev/null
+++ b/vibrator/cs40l26/tests/Android.bp
@@ -0,0 +1,35 @@
+//
+// Copyright (C) 2022 The Android Open Source Project
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package {
+    default_applicable_licenses: ["Android-Apache-2.0"],
+}
+
+cc_test {
+    name: "VibratorHalCs40l26TestSuitePrivate",
+    defaults: ["VibratorHalCs40l26TestDefaultsPrivate"],
+    srcs: [
+        "test-hwcal.cpp",
+        "test-hwapi.cpp",
+        "test-vibrator.cpp",
+    ],
+    static_libs: [
+        "libc++fs",
+        "libgmock",
+    ],
+    shared_libs: [
+        "libbase",
+    ],
+}
diff --git a/vibrator/cs40l26/tests/mocks.h b/vibrator/cs40l26/tests/mocks.h
new file mode 100644
index 0000000..c85b0b5
--- /dev/null
+++ b/vibrator/cs40l26/tests/mocks.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ANDROID_HARDWARE_VIBRATOR_TEST_MOCKS_H
+#define ANDROID_HARDWARE_VIBRATOR_TEST_MOCKS_H
+
+#include <aidl/android/hardware/vibrator/BnVibratorCallback.h>
+
+#include "Vibrator.h"
+
+class MockGPIO : public ::aidl::android::hardware::vibrator::Vibrator::HwGPIO {
+  public:
+    MOCK_METHOD0(destructor, void());
+    MOCK_METHOD0(getGPIO, bool());
+    MOCK_METHOD0(initGPIO, bool());
+    MOCK_METHOD1(setGPIOOutput, bool(bool value));
+    MOCK_METHOD1(debug, void(int fd));
+
+    ~MockGPIO() override { destructor(); };
+};
+
+class MockApi : public ::aidl::android::hardware::vibrator::Vibrator::HwApi {
+  public:
+    MOCK_METHOD0(destructor, void());
+    MOCK_METHOD1(setF0, bool(std::string value));
+    MOCK_METHOD1(setF0Offset, bool(uint32_t value));
+    MOCK_METHOD1(setRedc, bool(std::string value));
+    MOCK_METHOD1(setQ, bool(std::string value));
+    MOCK_METHOD1(getEffectCount, bool(uint32_t *value));
+    MOCK_METHOD2(pollVibeState, bool(uint32_t value, int32_t timeoutMs));
+    MOCK_METHOD0(hasOwtFreeSpace, bool());
+    MOCK_METHOD1(getOwtFreeSpace, bool(uint32_t *value));
+    MOCK_METHOD1(setF0CompEnable, bool(bool value));
+    MOCK_METHOD1(setRedcCompEnable, bool(bool value));
+    MOCK_METHOD1(setMinOnOffInterval, bool(uint32_t value));
+    MOCK_METHOD2(setFFGain, bool(int fd, uint16_t value));
+    MOCK_METHOD3(setFFEffect, bool(int fd, struct ff_effect *effect, uint16_t timeoutMs));
+    MOCK_METHOD3(setFFPlay, bool(int fd, int8_t index, bool value));
+    MOCK_METHOD2(getHapticAlsaDevice, bool(int *card, int *device));
+    MOCK_METHOD4(setHapticPcmAmp, bool(struct pcm **haptic_pcm, bool enable, int card, int device));
+    MOCK_METHOD6(uploadOwtEffect,
+                 bool(int fd, uint8_t *owtData, uint32_t numBytes, struct ff_effect *effect,
+                      uint32_t *outEffectIndex, int *status));
+    MOCK_METHOD3(eraseOwtEffect, bool(int fd, int8_t effectIndex, std::vector<ff_effect> *effect));
+    MOCK_METHOD1(debug, void(int fd));
+
+    ~MockApi() override { destructor(); };
+};
+
+class MockCal : public ::aidl::android::hardware::vibrator::Vibrator::HwCal {
+  public:
+    MOCK_METHOD0(destructor, void());
+    MOCK_METHOD1(getVersion, bool(uint32_t *value));
+    MOCK_METHOD1(getF0, bool(std::string &value));
+    MOCK_METHOD1(getF0SyncOffset, bool(uint32_t *value));
+    MOCK_METHOD1(getRedc, bool(std::string &value));
+    MOCK_METHOD1(getQ, bool(std::string &value));
+    MOCK_METHOD1(getLongFrequencyShift, bool(int32_t *value));
+    MOCK_METHOD1(getTickVolLevels, bool(std::array<uint32_t, 2> *value));
+    MOCK_METHOD1(getClickVolLevels, bool(std::array<uint32_t, 2> *value));
+    MOCK_METHOD1(getLongVolLevels, bool(std::array<uint32_t, 2> *value));
+    MOCK_METHOD0(isChirpEnabled, bool());
+    MOCK_METHOD1(getSupportedPrimitives, bool(uint32_t *value));
+    MOCK_METHOD0(isF0CompEnabled, bool());
+    MOCK_METHOD0(isRedcCompEnabled, bool());
+    MOCK_METHOD1(debug, void(int fd));
+
+    ~MockCal() override { destructor(); };
+    // b/132668253: Workaround gMock Compilation Issue
+    bool getF0(std::string *value) { return getF0(*value); }
+    bool getRedc(std::string *value) { return getRedc(*value); }
+    bool getQ(std::string *value) { return getQ(*value); }
+};
+
+class MockVibratorCallback : public aidl::android::hardware::vibrator::BnVibratorCallback {
+  public:
+    MOCK_METHOD(ndk::ScopedAStatus, onComplete, ());
+};
+
+#endif  // ANDROID_HARDWARE_VIBRATOR_TEST_MOCKS_H
diff --git a/vibrator/cs40l26/tests/test-hwapi.cpp b/vibrator/cs40l26/tests/test-hwapi.cpp
new file mode 100644
index 0000000..cc4d465
--- /dev/null
+++ b/vibrator/cs40l26/tests/test-hwapi.cpp
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <android-base/file.h>
+#include <cutils/fs.h>
+#include <gtest/gtest.h>
+
+#include <cstdlib>
+#include <fstream>
+
+#include "Hardware.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+using ::testing::Test;
+using ::testing::TestParamInfo;
+using ::testing::ValuesIn;
+using ::testing::WithParamInterface;
+
+class HwApiTest : public Test {
+  private:
+    static constexpr const char *FILE_NAMES[]{
+            "calibration/f0_stored",
+            "default/f0_offset",
+            "calibration/redc_stored",
+            "calibration/q_stored",
+            "default/f0_comp_enable",
+            "default/redc_comp_enable",
+            "default/owt_free_space",
+            "default/num_waves",
+            "default/delay_before_stop_playback_us",
+    };
+
+  public:
+    void SetUp() override {
+        std::string prefix;
+        for (auto n : FILE_NAMES) {
+            auto name = std::filesystem::path(n);
+            auto path = std::filesystem::path(mFilesDir.path) / name;
+            fs_mkdirs(path.c_str(), S_IRWXU);
+            std::ofstream touch{path};
+            mFileMap[name] = path;
+        }
+        prefix = std::filesystem::path(mFilesDir.path) / "";
+        setenv("HWAPI_PATH_PREFIX", prefix.c_str(), true);
+        mHwApi = std::make_unique<HwApi>();
+
+        for (auto n : FILE_NAMES) {
+            auto name = std::filesystem::path(n);
+            auto path = std::filesystem::path(mEmptyDir.path) / name;
+        }
+        prefix = std::filesystem::path(mEmptyDir.path) / "";
+        setenv("HWAPI_PATH_PREFIX", prefix.c_str(), true);
+        mNoApi = std::make_unique<HwApi>();
+    }
+
+    void TearDown() override { verifyContents(); }
+
+    static auto ParamNameFixup(std::string str) {
+        std::replace(str.begin(), str.end(), '/', '_');
+        return str;
+    }
+
+  protected:
+    // Set expected file content for a test.
+    template <typename T>
+    void expectContent(const std::string &name, const T &value) {
+        mExpectedContent[name] << value << std::endl;
+    }
+
+    // Set actual file content for an input test.
+    template <typename T>
+    void updateContent(const std::string &name, const T &value) {
+        std::ofstream(mFileMap[name]) << value << std::endl;
+    }
+
+    template <typename T>
+    void expectAndUpdateContent(const std::string &name, const T &value) {
+        expectContent(name, value);
+        updateContent(name, value);
+    }
+
+    // Compare all file contents against expected contents.
+    void verifyContents() {
+        for (auto &a : mFileMap) {
+            std::ifstream file{a.second};
+            std::string expect = mExpectedContent[a.first].str();
+            std::string actual = std::string(std::istreambuf_iterator<char>(file),
+                                             std::istreambuf_iterator<char>());
+            EXPECT_EQ(expect, actual) << a.first;
+        }
+    }
+
+  protected:
+    std::unique_ptr<Vibrator::HwApi> mHwApi;
+    std::unique_ptr<Vibrator::HwApi> mNoApi;
+    std::map<std::string, std::string> mFileMap;
+    TemporaryDir mFilesDir;
+    TemporaryDir mEmptyDir;
+    std::map<std::string, std::stringstream> mExpectedContent;
+};
+
+template <typename T>
+class HwApiTypedTest : public HwApiTest,
+                       public WithParamInterface<std::tuple<std::string, std::function<T>>> {
+  public:
+    static auto PrintParam(const TestParamInfo<typename HwApiTypedTest::ParamType> &info) {
+        return ParamNameFixup(std::get<0>(info.param));
+    }
+    static auto MakeParam(std::string name, std::function<T> func) {
+        return std::make_tuple(name, func);
+    }
+};
+
+using HasTest = HwApiTypedTest<bool(Vibrator::HwApi &)>;
+
+TEST_P(HasTest, success_returnsTrue) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+
+    EXPECT_TRUE(func(*mHwApi));
+}
+
+TEST_P(HasTest, success_returnsFalse) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+
+    EXPECT_FALSE(func(*mNoApi));
+}
+
+INSTANTIATE_TEST_CASE_P(HwApiTests, HasTest,
+                        ValuesIn({
+                                HasTest::MakeParam("default/owt_free_space",
+                                                   &Vibrator::HwApi::hasOwtFreeSpace),
+                        }),
+                        HasTest::PrintParam);
+
+using GetUint32Test = HwApiTypedTest<bool(Vibrator::HwApi &, uint32_t *)>;
+
+TEST_P(GetUint32Test, success) {
+    auto param = GetParam();
+    auto name = std::get<0>(param);
+    auto func = std::get<1>(param);
+    uint32_t expect = std::rand();
+    uint32_t actual = ~expect;
+
+    expectAndUpdateContent(name, expect);
+
+    EXPECT_TRUE(func(*mHwApi, &actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_P(GetUint32Test, failure) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+    uint32_t value;
+
+    EXPECT_FALSE(func(*mNoApi, &value));
+}
+
+INSTANTIATE_TEST_CASE_P(HwApiTests, GetUint32Test,
+                        ValuesIn({
+                                GetUint32Test::MakeParam("default/num_waves",
+                                                         &Vibrator::HwApi::getEffectCount),
+                                GetUint32Test::MakeParam("default/owt_free_space",
+                                                         &Vibrator::HwApi::getOwtFreeSpace),
+                        }),
+                        GetUint32Test::PrintParam);
+
+using SetBoolTest = HwApiTypedTest<bool(Vibrator::HwApi &, bool)>;
+
+TEST_P(SetBoolTest, success_returnsTrue) {
+    auto param = GetParam();
+    auto name = std::get<0>(param);
+    auto func = std::get<1>(param);
+
+    expectContent(name, "1");
+
+    EXPECT_TRUE(func(*mHwApi, true));
+}
+
+TEST_P(SetBoolTest, success_returnsFalse) {
+    auto param = GetParam();
+    auto name = std::get<0>(param);
+    auto func = std::get<1>(param);
+
+    expectContent(name, "0");
+
+    EXPECT_TRUE(func(*mHwApi, false));
+}
+
+TEST_P(SetBoolTest, failure) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+
+    EXPECT_FALSE(func(*mNoApi, true));
+    EXPECT_FALSE(func(*mNoApi, false));
+}
+
+INSTANTIATE_TEST_CASE_P(HwApiTests, SetBoolTest,
+                        ValuesIn({
+                                SetBoolTest::MakeParam("default/f0_comp_enable",
+                                                       &Vibrator::HwApi::setF0CompEnable),
+                                SetBoolTest::MakeParam("default/redc_comp_enable",
+                                                       &Vibrator::HwApi::setRedcCompEnable),
+                        }),
+                        SetBoolTest::PrintParam);
+
+using SetUint32Test = HwApiTypedTest<bool(Vibrator::HwApi &, uint32_t)>;
+
+TEST_P(SetUint32Test, success) {
+    auto param = GetParam();
+    auto name = std::get<0>(param);
+    auto func = std::get<1>(param);
+    uint32_t value = std::rand();
+
+    expectContent(name, value);
+
+    EXPECT_TRUE(func(*mHwApi, value));
+}
+
+TEST_P(SetUint32Test, failure) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+    uint32_t value = std::rand();
+
+    EXPECT_FALSE(func(*mNoApi, value));
+}
+
+INSTANTIATE_TEST_CASE_P(HwApiTests, SetUint32Test,
+                        ValuesIn({
+                                SetUint32Test::MakeParam("default/f0_offset",
+                                                         &Vibrator::HwApi::setF0Offset),
+                                SetUint32Test::MakeParam("default/delay_before_stop_playback_us",
+                                                         &Vibrator::HwApi::setMinOnOffInterval),
+                        }),
+                        SetUint32Test::PrintParam);
+
+using SetStringTest = HwApiTypedTest<bool(Vibrator::HwApi &, std::string)>;
+
+TEST_P(SetStringTest, success) {
+    auto param = GetParam();
+    auto name = std::get<0>(param);
+    auto func = std::get<1>(param);
+    std::string value = TemporaryFile().path;
+
+    expectContent(name, value);
+
+    EXPECT_TRUE(func(*mHwApi, value));
+}
+
+TEST_P(SetStringTest, failure) {
+    auto param = GetParam();
+    auto func = std::get<1>(param);
+    std::string value = TemporaryFile().path;
+
+    EXPECT_FALSE(func(*mNoApi, value));
+}
+
+INSTANTIATE_TEST_CASE_P(
+        HwApiTests, SetStringTest,
+        ValuesIn({
+                SetStringTest::MakeParam("calibration/f0_stored", &Vibrator::HwApi::setF0),
+                SetStringTest::MakeParam("calibration/redc_stored", &Vibrator::HwApi::setRedc),
+                SetStringTest::MakeParam("calibration/q_stored", &Vibrator::HwApi::setQ),
+        }),
+        SetStringTest::PrintParam);
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/tests/test-hwcal.cpp b/vibrator/cs40l26/tests/test-hwcal.cpp
new file mode 100644
index 0000000..e482b6c
--- /dev/null
+++ b/vibrator/cs40l26/tests/test-hwcal.cpp
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <android-base/file.h>
+#include <gtest/gtest.h>
+
+#include <fstream>
+
+#include "Hardware.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+using ::testing::Test;
+
+class HwCalTest : public Test {
+  protected:
+    static constexpr std::array<uint32_t, 2> V_TICK_DEFAULT = {1, 100};
+    static constexpr std::array<uint32_t, 2> V_CLICK_DEFAULT = {1, 100};
+    static constexpr std::array<uint32_t, 2> V_LONG_DEFAULT = {1, 100};
+
+  public:
+    void SetUp() override { setenv("CALIBRATION_FILEPATH", mCalFile.path, true); }
+
+  private:
+    template <typename T>
+    static void pack(std::ostream &stream, const T &value, std::string lpad, std::string rpad) {
+        stream << lpad << value << rpad;
+    }
+
+    template <typename T, typename std::array<T, 0>::size_type N>
+    static void pack(std::ostream &stream, const std::array<T, N> &value, std::string lpad,
+                     std::string rpad) {
+        for (auto &entry : value) {
+            pack(stream, entry, lpad, rpad);
+        }
+    }
+
+  protected:
+    void createHwCal() { mHwCal = std::make_unique<HwCal>(); }
+
+    template <typename T>
+    void write(const std::string key, const T &value, std::string lpad = " ",
+               std::string rpad = "") {
+        std::ofstream calfile{mCalFile.path, std::ios_base::app};
+        calfile << key << ":";
+        pack(calfile, value, lpad, rpad);
+        calfile << std::endl;
+    }
+
+    void unlink() { ::unlink(mCalFile.path); }
+
+  protected:
+    std::unique_ptr<Vibrator::HwCal> mHwCal;
+    TemporaryFile mCalFile;
+};
+
+TEST_F(HwCalTest, f0_measured) {
+    uint32_t randInput = std::rand();
+    std::string expect = std::to_string(randInput);
+    std::string actual = std::to_string(~randInput);
+
+    write("f0_measured", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getF0(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, f0_missing) {
+    std::string actual;
+
+    createHwCal();
+
+    EXPECT_FALSE(mHwCal->getF0(&actual));
+}
+
+TEST_F(HwCalTest, redc_measured) {
+    uint32_t randInput = std::rand();
+    std::string expect = std::to_string(randInput);
+    std::string actual = std::to_string(~randInput);
+
+    write("redc_measured", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getRedc(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, redc_missing) {
+    std::string actual;
+
+    createHwCal();
+
+    EXPECT_FALSE(mHwCal->getRedc(&actual));
+}
+
+TEST_F(HwCalTest, q_measured) {
+    uint32_t randInput = std::rand();
+    std::string expect = std::to_string(randInput);
+    std::string actual = std::to_string(~randInput);
+
+    write("q_measured", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getQ(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, q_missing) {
+    std::string actual;
+
+    createHwCal();
+
+    EXPECT_FALSE(mHwCal->getQ(&actual));
+}
+
+TEST_F(HwCalTest, v_levels) {
+    std::array<uint32_t, 2> expect;
+    std::array<uint32_t, 2> actual;
+
+    // voltage for tick effects
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+
+    write("v_tick", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    // voltage for click effects
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+
+    write("v_click", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    // voltage for long effects
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+
+    write("v_long", expect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, v_missing) {
+    std::array<uint32_t, 2> expect = V_TICK_DEFAULT;
+    std::array<uint32_t, 2> actual;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_CLICK_DEFAULT;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_LONG_DEFAULT;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, v_short) {
+    std::array<uint32_t, 2> expect = V_TICK_DEFAULT;
+    std::array<uint32_t, 2> actual;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    write("v_tick", std::array<uint32_t, expect.size() - 1>());
+    write("v_click", std::array<uint32_t, expect.size() - 1>());
+    write("v_long", std::array<uint32_t, expect.size() - 1>());
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_CLICK_DEFAULT;
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_LONG_DEFAULT;
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, v_long) {
+    std::array<uint32_t, 2> expect = V_TICK_DEFAULT;
+    std::array<uint32_t, 2> actual;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    write("v_tick", std::array<uint32_t, expect.size() + 1>());
+    write("v_click", std::array<uint32_t, expect.size() + 1>());
+    write("v_long", std::array<uint32_t, expect.size() + 1>());
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_CLICK_DEFAULT;
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_LONG_DEFAULT;
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, v_nofile) {
+    std::array<uint32_t, 2> expect = V_TICK_DEFAULT;
+    std::array<uint32_t, 2> actual;
+
+    std::transform(expect.begin(), expect.end(), actual.begin(), [](uint32_t &e) { return ~e; });
+
+    write("v_tick", actual);
+    write("v_click", actual);
+    write("v_long", actual);
+    unlink();
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_CLICK_DEFAULT;
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+
+    expect = V_LONG_DEFAULT;
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&actual));
+    EXPECT_EQ(expect, actual);
+}
+
+TEST_F(HwCalTest, multiple) {
+    uint32_t randInput = std::rand();
+    std::string f0Expect = std::to_string(randInput);
+    std::string f0Actual = std::to_string(~randInput);
+    randInput = std::rand();
+    std::string redcExpect = std::to_string(randInput);
+    std::string redcActual = std::to_string(~randInput);
+    randInput = std::rand();
+    std::string qExpect = std::to_string(randInput);
+    std::string qActual = std::to_string(~randInput);
+    std::array<uint32_t, 2> volTickExpect, volClickExpect, volLongExpect;
+    std::array<uint32_t, 2> volActual;
+
+    std::transform(volTickExpect.begin(), volTickExpect.end(), volActual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+
+    write("f0_measured", f0Expect);
+    write("redc_measured", redcExpect);
+    write("q_measured", qExpect);
+    write("v_tick", volTickExpect);
+    std::transform(volClickExpect.begin(), volClickExpect.end(), volActual.begin(),
+                   [](uint32_t &e) {
+                       e = std::rand();
+                       return ~e;
+                   });
+    write("v_click", volClickExpect);
+    std::transform(volLongExpect.begin(), volLongExpect.end(), volActual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+    write("v_long", volLongExpect);
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getF0(&f0Actual));
+    EXPECT_EQ(f0Expect, f0Actual);
+    EXPECT_TRUE(mHwCal->getRedc(&redcActual));
+    EXPECT_EQ(redcExpect, redcActual);
+    EXPECT_TRUE(mHwCal->getQ(&qActual));
+    EXPECT_EQ(qExpect, qActual);
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&volActual));
+    EXPECT_EQ(volTickExpect, volActual);
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&volActual));
+    EXPECT_EQ(volClickExpect, volActual);
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&volActual));
+    EXPECT_EQ(volLongExpect, volActual);
+}
+
+TEST_F(HwCalTest, trimming) {
+    uint32_t randInput = std::rand();
+    std::string f0Expect = std::to_string(randInput);
+    std::string f0Actual = std::to_string(~randInput);
+    randInput = std::rand();
+    std::string redcExpect = std::to_string(randInput);
+    std::string redcActual = std::to_string(randInput);
+    randInput = std::rand();
+    std::string qExpect = std::to_string(randInput);
+    std::string qActual = std::to_string(randInput);
+    std::array<uint32_t, 2> volTickExpect, volClickExpect, volLongExpect;
+    std::array<uint32_t, 2> volActual;
+
+    std::transform(volTickExpect.begin(), volTickExpect.end(), volActual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+
+    write("f0_measured", f0Expect, " \t", "\t ");
+    write("redc_measured", redcExpect, " \t", "\t ");
+    write("q_measured", qExpect, " \t", "\t ");
+    write("v_tick", volTickExpect, " \t", "\t ");
+    std::transform(volClickExpect.begin(), volClickExpect.end(), volActual.begin(),
+                   [](uint32_t &e) {
+                       e = std::rand();
+                       return ~e;
+                   });
+    write("v_click", volClickExpect, " \t", "\t ");
+    std::transform(volLongExpect.begin(), volLongExpect.end(), volActual.begin(), [](uint32_t &e) {
+        e = std::rand();
+        return ~e;
+    });
+    write("v_long", volLongExpect, " \t", "\t ");
+
+    createHwCal();
+
+    EXPECT_TRUE(mHwCal->getF0(&f0Actual));
+    EXPECT_EQ(f0Expect, f0Actual);
+    EXPECT_TRUE(mHwCal->getRedc(&redcActual));
+    EXPECT_EQ(redcExpect, redcActual);
+    EXPECT_TRUE(mHwCal->getQ(&qActual));
+    EXPECT_EQ(qExpect, qActual);
+    EXPECT_TRUE(mHwCal->getTickVolLevels(&volActual));
+    EXPECT_EQ(volTickExpect, volActual);
+    EXPECT_TRUE(mHwCal->getClickVolLevels(&volActual));
+    EXPECT_EQ(volClickExpect, volActual);
+    EXPECT_TRUE(mHwCal->getLongVolLevels(&volActual));
+    EXPECT_EQ(volLongExpect, volActual);
+}
+
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/tests/test-vibrator.cpp b/vibrator/cs40l26/tests/test-vibrator.cpp
new file mode 100644
index 0000000..3ea6bda
--- /dev/null
+++ b/vibrator/cs40l26/tests/test-vibrator.cpp
@@ -0,0 +1,694 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <aidl/android/hardware/vibrator/BnVibratorCallback.h>
+#include <android-base/logging.h>
+#include <gmock/gmock.h>
+#include <gtest/gtest.h>
+#include <linux/input.h>
+#include <linux/uinput.h>
+
+#include <future>
+
+#include "Vibrator.h"
+#include "mocks.h"
+#include "types.h"
+#include "utils.h"
+
+namespace aidl {
+namespace android {
+namespace hardware {
+namespace vibrator {
+
+using ::testing::_;
+using ::testing::AnyNumber;
+using ::testing::Assign;
+using ::testing::AtLeast;
+using ::testing::AtMost;
+using ::testing::Combine;
+using ::testing::DoAll;
+using ::testing::DoDefault;
+using ::testing::Exactly;
+using ::testing::Expectation;
+using ::testing::ExpectationSet;
+using ::testing::Ge;
+using ::testing::Mock;
+using ::testing::MockFunction;
+using ::testing::Range;
+using ::testing::Return;
+using ::testing::Sequence;
+using ::testing::SetArgPointee;
+using ::testing::SetArgReferee;
+using ::testing::Test;
+using ::testing::TestParamInfo;
+using ::testing::ValuesIn;
+using ::testing::WithParamInterface;
+
+// Forward Declarations
+
+static EffectQueue Queue(const QueueEffect &effect);
+static EffectQueue Queue(const QueueDelay &delay);
+template <typename T, typename U, typename... Args>
+static EffectQueue Queue(const T &first, const U &second, Args... rest);
+
+static EffectLevel Level(float intensity, float levelLow, float levelHigh);
+static EffectScale Scale(float intensity, float levelLow, float levelHigh);
+
+// Constants With Arbitrary Values
+
+static constexpr uint32_t CAL_VERSION = 2;
+static constexpr std::array<EffectLevel, 2> V_TICK_DEFAULT = {1, 100};
+static constexpr std::array<EffectLevel, 2> V_CLICK_DEFAULT{1, 100};
+static constexpr std::array<EffectLevel, 2> V_LONG_DEFAULT{1, 100};
+static constexpr std::array<EffectDuration, 14> EFFECT_DURATIONS{
+        0, 100, 30, 1000, 300, 130, 150, 500, 100, 15, 20, 1000, 1000, 1000};
+
+// Constants With Prescribed Values
+
+static const std::map<Effect, EffectIndex> EFFECT_INDEX{
+        {Effect::CLICK, 2},
+        {Effect::TICK, 2},
+        {Effect::HEAVY_CLICK, 2},
+        {Effect::TEXTURE_TICK, 9},
+};
+static constexpr uint32_t MIN_ON_OFF_INTERVAL_US = 8500;
+static constexpr uint8_t VOLTAGE_SCALE_MAX = 100;
+static constexpr int8_t MAX_COLD_START_LATENCY_MS = 6;  // I2C Transaction + DSP Return-From-Standby
+static constexpr auto POLLING_TIMEOUT = 20;
+enum WaveformIndex : uint16_t {
+    /* Physical waveform */
+    WAVEFORM_LONG_VIBRATION_EFFECT_INDEX = 0,
+    WAVEFORM_RESERVED_INDEX_1 = 1,
+    WAVEFORM_CLICK_INDEX = 2,
+    WAVEFORM_SHORT_VIBRATION_EFFECT_INDEX = 3,
+    WAVEFORM_THUD_INDEX = 4,
+    WAVEFORM_SPIN_INDEX = 5,
+    WAVEFORM_QUICK_RISE_INDEX = 6,
+    WAVEFORM_SLOW_RISE_INDEX = 7,
+    WAVEFORM_QUICK_FALL_INDEX = 8,
+    WAVEFORM_LIGHT_TICK_INDEX = 9,
+    WAVEFORM_LOW_TICK_INDEX = 10,
+    WAVEFORM_RESERVED_MFG_1,
+    WAVEFORM_RESERVED_MFG_2,
+    WAVEFORM_RESERVED_MFG_3,
+    WAVEFORM_MAX_PHYSICAL_INDEX,
+    /* OWT waveform */
+    WAVEFORM_COMPOSE = WAVEFORM_MAX_PHYSICAL_INDEX,
+    WAVEFORM_PWLE,
+    /*
+     * Refer to <linux/input.h>, the WAVEFORM_MAX_INDEX must not exceed 96.
+     * #define FF_GAIN          0x60  // 96 in decimal
+     * #define FF_MAX_EFFECTS   FF_GAIN
+     */
+    WAVEFORM_MAX_INDEX,
+};
+
+static const EffectScale ON_GLOBAL_SCALE{levelToScale(V_LONG_DEFAULT[1])};
+static const EffectIndex ON_EFFECT_INDEX{0};
+
+static const std::map<EffectTuple, EffectScale> EFFECT_SCALE{
+        {{Effect::TICK, EffectStrength::LIGHT},
+         Scale(0.5f * 0.5f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::TICK, EffectStrength::MEDIUM},
+         Scale(0.5f * 0.7f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::TICK, EffectStrength::STRONG},
+         Scale(0.5f * 1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::CLICK, EffectStrength::LIGHT},
+         Scale(0.7f * 0.5f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::CLICK, EffectStrength::MEDIUM},
+         Scale(0.7f * 0.7f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::CLICK, EffectStrength::STRONG},
+         Scale(0.7f * 1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::HEAVY_CLICK, EffectStrength::LIGHT},
+         Scale(1.0f * 0.5f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::HEAVY_CLICK, EffectStrength::MEDIUM},
+         Scale(1.0f * 0.7f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::HEAVY_CLICK, EffectStrength::STRONG},
+         Scale(1.0f * 1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+        {{Effect::TEXTURE_TICK, EffectStrength::LIGHT},
+         Scale(0.5f * 0.5f, V_TICK_DEFAULT[0], V_TICK_DEFAULT[1])},
+        {{Effect::TEXTURE_TICK, EffectStrength::MEDIUM},
+         Scale(0.5f * 0.7f, V_TICK_DEFAULT[0], V_TICK_DEFAULT[1])},
+        {{Effect::TEXTURE_TICK, EffectStrength::STRONG},
+         Scale(0.5f * 1.0f, V_TICK_DEFAULT[0], V_TICK_DEFAULT[1])},
+};
+
+static const std::map<EffectTuple, EffectQueue> EFFECT_QUEUE{
+        {{Effect::DOUBLE_CLICK, EffectStrength::LIGHT},
+         Queue(QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(0.7f * 0.5f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+               100,
+               QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(1.0f * 0.5f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])})},
+        {{Effect::DOUBLE_CLICK, EffectStrength::MEDIUM},
+         Queue(QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(0.7f * 0.7f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+               100,
+               QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(1.0f * 0.7f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])})},
+        {{Effect::DOUBLE_CLICK, EffectStrength::STRONG},
+         Queue(QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(0.7f * 1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])},
+               100,
+               QueueEffect{EFFECT_INDEX.at(Effect::CLICK),
+                           Level(1.0f * 1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])})},
+};
+
+EffectQueue Queue(const QueueEffect &effect) {
+    auto index = std::get<0>(effect);
+    auto level = std::get<1>(effect);
+    auto string = std::to_string(index) + "." + std::to_string(level);
+    auto duration = EFFECT_DURATIONS[index];
+    return {string, duration};
+}
+
+EffectQueue Queue(const QueueDelay &delay) {
+    auto string = std::to_string(delay);
+    return {string, delay};
+}
+
+template <typename T, typename U, typename... Args>
+EffectQueue Queue(const T &first, const U &second, Args... rest) {
+    auto head = Queue(first);
+    auto tail = Queue(second, rest...);
+    auto string = std::get<0>(head) + "," + std::get<0>(tail);
+    auto duration = std::get<1>(head) + std::get<1>(tail);
+    return {string, duration};
+}
+
+static EffectLevel Level(float intensity, float levelLow, float levelHigh) {
+    return std::lround(intensity * (levelHigh - levelLow)) + levelLow;
+}
+
+static EffectScale Scale(float intensity, float levelLow, float levelHigh) {
+    return levelToScale(Level(intensity, levelLow, levelHigh));
+}
+
+class VibratorTest : public Test {
+  public:
+    void SetUp() override {
+        setenv("INPUT_EVENT_NAME", "CS40L26TestSuite", true);
+        std::unique_ptr<MockApi> mockapi;
+        std::unique_ptr<MockCal> mockcal;
+        std::unique_ptr<MockGPIO> mockgpio;
+
+        createMock(&mockapi, &mockcal, &mockgpio);
+        createVibrator(std::move(mockapi), std::move(mockcal), std::move(mockgpio));
+    }
+
+    void TearDown() override { deleteVibrator(); }
+
+  protected:
+    void createMock(std::unique_ptr<MockApi> *mockapi, std::unique_ptr<MockCal> *mockcal,
+                    std::unique_ptr<MockGPIO> *mockgpio) {
+        *mockapi = std::make_unique<MockApi>();
+        *mockcal = std::make_unique<MockCal>();
+        *mockgpio = std::make_unique<MockGPIO>();
+
+        mMockApi = mockapi->get();
+        mMockCal = mockcal->get();
+        mMockGpio = mockgpio->get();
+
+        ON_CALL(*mMockApi, destructor()).WillByDefault(Assign(&mMockApi, nullptr));
+
+        ON_CALL(*mMockApi, setFFGain(_, _)).WillByDefault(Return(true));
+        ON_CALL(*mMockApi, setFFEffect(_, _, _)).WillByDefault(Return(true));
+        ON_CALL(*mMockApi, setFFPlay(_, _, _)).WillByDefault(Return(true));
+        ON_CALL(*mMockApi, pollVibeState(_, _)).WillByDefault(Return(true));
+        ON_CALL(*mMockApi, uploadOwtEffect(_, _, _, _, _, _)).WillByDefault(Return(true));
+        ON_CALL(*mMockApi, eraseOwtEffect(_, _, _)).WillByDefault(Return(true));
+
+        ON_CALL(*mMockApi, getOwtFreeSpace(_))
+                .WillByDefault(DoAll(SetArgPointee<0>(11504), Return(true)));
+
+        ON_CALL(*mMockCal, destructor()).WillByDefault(Assign(&mMockCal, nullptr));
+
+        ON_CALL(*mMockCal, getVersion(_))
+                .WillByDefault(DoAll(SetArgPointee<0>(CAL_VERSION), Return(true)));
+
+        ON_CALL(*mMockCal, getTickVolLevels(_))
+                .WillByDefault(DoAll(SetArgPointee<0>(V_TICK_DEFAULT), Return(true)));
+        ON_CALL(*mMockCal, getClickVolLevels(_))
+                .WillByDefault(DoAll(SetArgPointee<0>(V_CLICK_DEFAULT), Return(true)));
+        ON_CALL(*mMockCal, getLongVolLevels(_))
+                .WillByDefault(DoAll(SetArgPointee<0>(V_LONG_DEFAULT), Return(true)));
+
+        ON_CALL(*mMockGpio, destructor()).WillByDefault(Assign(&mMockGpio, nullptr));
+
+        relaxMock(false);
+    }
+
+    void createVibrator(std::unique_ptr<MockApi> mockapi, std::unique_ptr<MockCal> mockcal,
+                        std::unique_ptr<MockGPIO> mockgpio, bool relaxed = true) {
+        if (relaxed) {
+            relaxMock(true);
+        }
+        // TODO(b/261415845): Need to add dual parameters to test the vibrator HAL's code in haptics
+        // mock test
+        mVibrator = ndk::SharedRefBase::make<Vibrator>(std::move(mockapi), std::move(mockcal),
+                                                       nullptr, nullptr, std::move(mockgpio));
+        if (relaxed) {
+            relaxMock(false);
+        }
+    }
+
+    void deleteVibrator(bool relaxed = true) {
+        if (relaxed) {
+            relaxMock(true);
+        }
+        mVibrator.reset();
+    }
+
+  private:
+    void relaxMock(bool relax) {
+        auto times = relax ? AnyNumber() : Exactly(0);
+
+        Mock::VerifyAndClearExpectations(mMockApi);
+        Mock::VerifyAndClearExpectations(mMockCal);
+
+        EXPECT_CALL(*mMockApi, destructor()).Times(times);
+        EXPECT_CALL(*mMockApi, setF0(_)).Times(times);
+        EXPECT_CALL(*mMockApi, setF0Offset(_)).Times(times);
+        EXPECT_CALL(*mMockApi, setRedc(_)).Times(times);
+        EXPECT_CALL(*mMockApi, setQ(_)).Times(times);
+        EXPECT_CALL(*mMockApi, hasOwtFreeSpace()).Times(times);
+        EXPECT_CALL(*mMockApi, getOwtFreeSpace(_)).Times(times);
+        EXPECT_CALL(*mMockApi, setF0CompEnable(_)).Times(times);
+        EXPECT_CALL(*mMockApi, setRedcCompEnable(_)).Times(times);
+        EXPECT_CALL(*mMockApi, pollVibeState(_, _)).Times(times);
+        EXPECT_CALL(*mMockApi, setFFGain(_, _)).Times(times);
+        EXPECT_CALL(*mMockApi, setFFEffect(_, _, _)).Times(times);
+        EXPECT_CALL(*mMockApi, setFFPlay(_, _, _)).Times(times);
+        EXPECT_CALL(*mMockApi, setMinOnOffInterval(_)).Times(times);
+        EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).Times(times);
+        EXPECT_CALL(*mMockApi, setHapticPcmAmp(_, _, _, _)).Times(times);
+
+        EXPECT_CALL(*mMockApi, debug(_)).Times(times);
+
+        EXPECT_CALL(*mMockCal, destructor()).Times(times);
+        EXPECT_CALL(*mMockCal, getF0(_)).Times(times);
+        EXPECT_CALL(*mMockCal, getRedc(_)).Times(times);
+        EXPECT_CALL(*mMockCal, getQ(_)).Times(times);
+        EXPECT_CALL(*mMockCal, getTickVolLevels(_)).Times(times);
+        EXPECT_CALL(*mMockCal, getClickVolLevels(_)).Times(times);
+        EXPECT_CALL(*mMockCal, getLongVolLevels(_)).Times(times);
+        EXPECT_CALL(*mMockCal, isChirpEnabled()).Times(times);
+        EXPECT_CALL(*mMockCal, getLongFrequencyShift(_)).Times(times);
+        EXPECT_CALL(*mMockCal, isF0CompEnabled()).Times(times);
+        EXPECT_CALL(*mMockCal, isRedcCompEnabled()).Times(times);
+        EXPECT_CALL(*mMockCal, debug(_)).Times(times);
+    }
+
+  protected:
+    MockApi *mMockApi;
+    MockCal *mMockCal;
+    MockGPIO *mMockGpio;
+    std::shared_ptr<IVibrator> mVibrator;
+    uint32_t mEffectIndex;
+};
+
+TEST_F(VibratorTest, Constructor) {
+    std::unique_ptr<MockApi> mockapi;
+    std::unique_ptr<MockCal> mockcal;
+    std::unique_ptr<MockGPIO> mockgpio;
+    std::string f0Val = std::to_string(std::rand());
+    std::string redcVal = std::to_string(std::rand());
+    std::string qVal = std::to_string(std::rand());
+    uint32_t calVer;
+    uint32_t supportedPrimitivesBits = 0x0;
+    Expectation volGet;
+    Sequence f0Seq, redcSeq, qSeq, supportedPrimitivesSeq;
+
+    EXPECT_CALL(*mMockApi, destructor()).WillOnce(DoDefault());
+    EXPECT_CALL(*mMockCal, destructor()).WillOnce(DoDefault());
+    EXPECT_CALL(*mMockGpio, destructor()).WillOnce(DoDefault());
+
+    deleteVibrator(false);
+
+    createMock(&mockapi, &mockcal, &mockgpio);
+
+    EXPECT_CALL(*mMockCal, getF0(_))
+            .InSequence(f0Seq)
+            .WillOnce(DoAll(SetArgReferee<0>(f0Val), Return(true)));
+    EXPECT_CALL(*mMockApi, setF0(f0Val)).InSequence(f0Seq).WillOnce(Return(true));
+
+    EXPECT_CALL(*mMockCal, getRedc(_))
+            .InSequence(redcSeq)
+            .WillOnce(DoAll(SetArgReferee<0>(redcVal), Return(true)));
+    EXPECT_CALL(*mMockApi, setRedc(redcVal)).InSequence(redcSeq).WillOnce(Return(true));
+
+    EXPECT_CALL(*mMockCal, getQ(_))
+            .InSequence(qSeq)
+            .WillOnce(DoAll(SetArgReferee<0>(qVal), Return(true)));
+    EXPECT_CALL(*mMockApi, setQ(qVal)).InSequence(qSeq).WillOnce(Return(true));
+
+    EXPECT_CALL(*mMockCal, getLongFrequencyShift(_)).WillOnce(Return(true));
+
+    mMockCal->getVersion(&calVer);
+    if (calVer == 2) {
+        volGet = EXPECT_CALL(*mMockCal, getTickVolLevels(_)).WillOnce(DoDefault());
+        volGet = EXPECT_CALL(*mMockCal, getClickVolLevels(_)).WillOnce(DoDefault());
+        volGet = EXPECT_CALL(*mMockCal, getLongVolLevels(_)).WillOnce(DoDefault());
+    }
+
+    EXPECT_CALL(*mMockCal, isF0CompEnabled()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, setF0CompEnable(true)).WillOnce(Return(true));
+    EXPECT_CALL(*mMockCal, isRedcCompEnabled()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, setRedcCompEnable(true)).WillOnce(Return(true));
+
+    EXPECT_CALL(*mMockCal, isChirpEnabled()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockCal, getSupportedPrimitives(_))
+            .InSequence(supportedPrimitivesSeq)
+            .WillOnce(DoAll(SetArgPointee<0>(supportedPrimitivesBits), Return(true)));
+
+    EXPECT_CALL(*mMockApi, setMinOnOffInterval(MIN_ON_OFF_INTERVAL_US)).WillOnce(Return(true));
+    createVibrator(std::move(mockapi), std::move(mockcal), std::move(mockgpio), false);
+}
+
+TEST_F(VibratorTest, on) {
+    Sequence s1, s2;
+    uint16_t duration = std::rand() + 1;
+
+    EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE)).InSequence(s1).WillOnce(DoDefault());
+    EXPECT_CALL(*mMockApi, setFFEffect(_, _, duration + MAX_COLD_START_LATENCY_MS))
+            .InSequence(s2)
+            .WillOnce(DoDefault());
+    EXPECT_CALL(*mMockApi, setFFPlay(_, ON_EFFECT_INDEX, true))
+            .InSequence(s1, s2)
+            .WillOnce(DoDefault());
+    EXPECT_TRUE(mVibrator->on(duration, nullptr).isOk());
+}
+
+TEST_F(VibratorTest, off) {
+    Sequence s1;
+    EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE)).InSequence(s1).WillOnce(DoDefault());
+    EXPECT_TRUE(mVibrator->off().isOk());
+}
+
+TEST_F(VibratorTest, supportsAmplitudeControl_supported) {
+    int32_t capabilities;
+    EXPECT_CALL(*mMockApi, hasOwtFreeSpace()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->getCapabilities(&capabilities).isOk());
+    EXPECT_GT(capabilities & IVibrator::CAP_AMPLITUDE_CONTROL, 0);
+}
+
+TEST_F(VibratorTest, supportsExternalAmplitudeControl_unsupported) {
+    int32_t capabilities;
+    EXPECT_CALL(*mMockApi, hasOwtFreeSpace()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->getCapabilities(&capabilities).isOk());
+    EXPECT_EQ(capabilities & IVibrator::CAP_EXTERNAL_AMPLITUDE_CONTROL, 0);
+}
+
+TEST_F(VibratorTest, setAmplitude_supported) {
+    EffectAmplitude amplitude = static_cast<float>(std::rand()) / RAND_MAX ?: 1.0f;
+
+    EXPECT_CALL(*mMockApi, setFFGain(_, amplitudeToScale(amplitude))).WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->setAmplitude(amplitude).isOk());
+}
+
+TEST_F(VibratorTest, supportsExternalControl_supported) {
+    int32_t capabilities;
+    EXPECT_CALL(*mMockApi, hasOwtFreeSpace()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->getCapabilities(&capabilities).isOk());
+    EXPECT_GT(capabilities & IVibrator::CAP_EXTERNAL_CONTROL, 0);
+}
+
+TEST_F(VibratorTest, supportsExternalControl_unsupported) {
+    int32_t capabilities;
+    EXPECT_CALL(*mMockApi, hasOwtFreeSpace()).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).WillOnce(Return(false));
+
+    EXPECT_TRUE(mVibrator->getCapabilities(&capabilities).isOk());
+    EXPECT_EQ(capabilities & IVibrator::CAP_EXTERNAL_CONTROL, 0);
+}
+
+TEST_F(VibratorTest, setExternalControl_enable) {
+    Sequence s1, s2;
+    EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE)).InSequence(s1).WillOnce(DoDefault());
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).InSequence(s2).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, setHapticPcmAmp(_, true, _, _))
+            .InSequence(s1, s2)
+            .WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->setExternalControl(true).isOk());
+}
+
+TEST_F(VibratorTest, setExternalControl_disable) {
+    Sequence s1, s2, s3, s4;
+
+    // The default mIsUnderExternalControl is false, so it needs to turn on the External Control
+    // to make mIsUnderExternalControl become true.
+    EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE))
+            .InSequence(s1)
+            .InSequence(s1)
+            .WillOnce(DoDefault());
+    EXPECT_CALL(*mMockApi, getHapticAlsaDevice(_, _)).InSequence(s2).WillOnce(Return(true));
+    EXPECT_CALL(*mMockApi, setHapticPcmAmp(_, true, _, _)).InSequence(s3).WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->setExternalControl(true).isOk());
+
+    EXPECT_CALL(*mMockApi, setFFGain(_, levelToScale(VOLTAGE_SCALE_MAX)))
+            .InSequence(s4)
+            .WillOnce(DoDefault());
+    EXPECT_CALL(*mMockApi, setHapticPcmAmp(_, false, _, _))
+            .InSequence(s1, s2, s3, s4)
+            .WillOnce(Return(true));
+
+    EXPECT_TRUE(mVibrator->setExternalControl(false).isOk());
+}
+
+class EffectsTest : public VibratorTest, public WithParamInterface<EffectTuple> {
+  public:
+    static auto PrintParam(const TestParamInfo<ParamType> &info) {
+        auto param = info.param;
+        auto effect = std::get<0>(param);
+        auto strength = std::get<1>(param);
+        return toString(effect) + "_" + toString(strength);
+    }
+};
+
+TEST_P(EffectsTest, perform) {
+    auto param = GetParam();
+    auto effect = std::get<0>(param);
+    auto strength = std::get<1>(param);
+    auto scale = EFFECT_SCALE.find(param);
+    auto queue = EFFECT_QUEUE.find(param);
+    EffectDuration duration;
+    auto callback = ndk::SharedRefBase::make<MockVibratorCallback>();
+    std::promise<void> promise;
+    std::future<void> future{promise.get_future()};
+    auto complete = [&promise] {
+        promise.set_value();
+        return ndk::ScopedAStatus::ok();
+    };
+    bool composeEffect;
+
+    ExpectationSet eSetup;
+    Expectation eActivate, ePollHaptics, ePollStop, eEraseDone;
+
+    if (scale != EFFECT_SCALE.end()) {
+        EffectIndex index = EFFECT_INDEX.at(effect);
+        duration = EFFECT_DURATIONS[index];
+
+        eSetup += EXPECT_CALL(*mMockApi, setFFGain(_, levelToScale(scale->second)))
+                          .WillOnce(DoDefault());
+        eActivate = EXPECT_CALL(*mMockApi, setFFPlay(_, index, true))
+                            .After(eSetup)
+                            .WillOnce(DoDefault());
+    } else if (queue != EFFECT_QUEUE.end()) {
+        duration = std::get<1>(queue->second);
+        eSetup += EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE))
+                          .After(eSetup)
+                          .WillOnce(DoDefault());
+        eSetup += EXPECT_CALL(*mMockApi, getOwtFreeSpace(_)).WillOnce(DoDefault());
+        eSetup += EXPECT_CALL(*mMockApi, uploadOwtEffect(_, _, _, _, _, _))
+                          .After(eSetup)
+                          .WillOnce(DoDefault());
+        eActivate = EXPECT_CALL(*mMockApi, setFFPlay(_, WAVEFORM_COMPOSE, true))
+                            .After(eSetup)
+                            .WillOnce(DoDefault());
+        composeEffect = true;
+    } else {
+        duration = 0;
+    }
+
+    if (duration) {
+        ePollHaptics = EXPECT_CALL(*mMockApi, pollVibeState(1, POLLING_TIMEOUT))
+                               .After(eActivate)
+                               .WillOnce(DoDefault());
+        ePollStop = EXPECT_CALL(*mMockApi, pollVibeState(0, -1))
+                            .After(ePollHaptics)
+                            .WillOnce(DoDefault());
+        if (composeEffect) {
+            eEraseDone = EXPECT_CALL(*mMockApi, eraseOwtEffect(_, _, _))
+                                 .After(ePollStop)
+                                 .WillOnce(DoDefault());
+            EXPECT_CALL(*callback, onComplete()).After(eEraseDone).WillOnce(complete);
+        } else {
+            EXPECT_CALL(*callback, onComplete()).After(ePollStop).WillOnce(complete);
+        }
+    }
+
+    int32_t lengthMs;
+    ndk::ScopedAStatus status = mVibrator->perform(effect, strength, callback, &lengthMs);
+    if (status.isOk()) {
+        EXPECT_LE(duration, lengthMs);
+    } else {
+        EXPECT_EQ(EX_UNSUPPORTED_OPERATION, status.getExceptionCode());
+        EXPECT_EQ(0, lengthMs);
+    }
+
+    if (duration) {
+        EXPECT_EQ(future.wait_for(std::chrono::milliseconds(100)), std::future_status::ready);
+    }
+}
+
+const std::vector<Effect> kEffects{ndk::enum_range<Effect>().begin(),
+                                   ndk::enum_range<Effect>().end()};
+const std::vector<EffectStrength> kEffectStrengths{ndk::enum_range<EffectStrength>().begin(),
+                                                   ndk::enum_range<EffectStrength>().end()};
+
+INSTANTIATE_TEST_CASE_P(VibratorTests, EffectsTest,
+                        Combine(ValuesIn(kEffects.begin(), kEffects.end()),
+                                ValuesIn(kEffectStrengths.begin(), kEffectStrengths.end())),
+                        EffectsTest::PrintParam);
+
+struct PrimitiveParam {
+    CompositePrimitive primitive;
+    EffectIndex index;
+};
+
+class PrimitiveTest : public VibratorTest, public WithParamInterface<PrimitiveParam> {
+  public:
+    static auto PrintParam(const TestParamInfo<ParamType> &info) {
+        return toString(info.param.primitive);
+    }
+};
+
+const std::vector<PrimitiveParam> kPrimitiveParams = {
+        {CompositePrimitive::CLICK, 2},      {CompositePrimitive::THUD, 4},
+        {CompositePrimitive::SPIN, 5},       {CompositePrimitive::QUICK_RISE, 6},
+        {CompositePrimitive::SLOW_RISE, 7},  {CompositePrimitive::QUICK_FALL, 8},
+        {CompositePrimitive::LIGHT_TICK, 9}, {CompositePrimitive::LOW_TICK, 10},
+};
+
+TEST_P(PrimitiveTest, getPrimitiveDuration) {
+    auto param = GetParam();
+    auto primitive = param.primitive;
+    auto index = param.index;
+    int32_t duration;
+
+    EXPECT_EQ(EX_NONE, mVibrator->getPrimitiveDuration(primitive, &duration).getExceptionCode());
+    EXPECT_EQ(EFFECT_DURATIONS[index], duration);
+}
+
+INSTANTIATE_TEST_CASE_P(VibratorTests, PrimitiveTest,
+                        ValuesIn(kPrimitiveParams.begin(), kPrimitiveParams.end()),
+                        PrimitiveTest::PrintParam);
+
+struct ComposeParam {
+    std::string name;
+    std::vector<CompositeEffect> composite;
+    EffectQueue queue;
+};
+
+class ComposeTest : public VibratorTest, public WithParamInterface<ComposeParam> {
+  public:
+    static auto PrintParam(const TestParamInfo<ParamType> &info) { return info.param.name; }
+};
+
+TEST_P(ComposeTest, compose) {
+    auto param = GetParam();
+    auto composite = param.composite;
+    auto queue = std::get<0>(param.queue);
+    ExpectationSet eSetup;
+    Expectation eActivate, ePollHaptics, ePollStop, eEraseDone;
+    auto callback = ndk::SharedRefBase::make<MockVibratorCallback>();
+    std::promise<void> promise;
+    std::future<void> future{promise.get_future()};
+    auto complete = [&promise] {
+        promise.set_value();
+        return ndk::ScopedAStatus::ok();
+    };
+
+    eSetup += EXPECT_CALL(*mMockApi, setFFGain(_, ON_GLOBAL_SCALE))
+                      .After(eSetup)
+                      .WillOnce(DoDefault());
+    eSetup += EXPECT_CALL(*mMockApi, getOwtFreeSpace(_)).WillOnce(DoDefault());
+    eSetup += EXPECT_CALL(*mMockApi, uploadOwtEffect(_, _, _, _, _, _))
+                      .After(eSetup)
+                      .WillOnce(DoDefault());
+    eActivate = EXPECT_CALL(*mMockApi, setFFPlay(_, WAVEFORM_COMPOSE, true))
+                        .After(eSetup)
+                        .WillOnce(DoDefault());
+
+    ePollHaptics = EXPECT_CALL(*mMockApi, pollVibeState(1, POLLING_TIMEOUT))
+                           .After(eActivate)
+                           .WillOnce(DoDefault());
+    ePollStop =
+            EXPECT_CALL(*mMockApi, pollVibeState(0, -1)).After(ePollHaptics).WillOnce(DoDefault());
+    eEraseDone =
+            EXPECT_CALL(*mMockApi, eraseOwtEffect(_, _, _)).After(ePollStop).WillOnce(DoDefault());
+    EXPECT_CALL(*callback, onComplete()).After(eEraseDone).WillOnce(complete);
+
+    EXPECT_EQ(EX_NONE, mVibrator->compose(composite, callback).getExceptionCode());
+
+    EXPECT_EQ(future.wait_for(std::chrono::milliseconds(100)), std::future_status::ready);
+}
+
+const std::vector<ComposeParam> kComposeParams = {
+        {"click",
+         {{0, CompositePrimitive::CLICK, 1.0f}},
+         Queue(QueueEffect(2, Level(1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 0)},
+        {"thud",
+         {{1, CompositePrimitive::THUD, 0.8f}},
+         Queue(1, QueueEffect(4, Level(0.8f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 0)},
+        {"spin",
+         {{2, CompositePrimitive::SPIN, 0.6f}},
+         Queue(2, QueueEffect(5, Level(0.6f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 0)},
+        {"quick_rise",
+         {{3, CompositePrimitive::QUICK_RISE, 0.4f}},
+         Queue(3, QueueEffect(6, Level(0.4f, V_LONG_DEFAULT[0], V_LONG_DEFAULT[1])), 0)},
+        {"slow_rise",
+         {{4, CompositePrimitive::SLOW_RISE, 0.0f}},
+         Queue(4, QueueEffect(7, Level(0.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 0)},
+        {"quick_fall",
+         {{5, CompositePrimitive::QUICK_FALL, 1.0f}},
+         Queue(5, QueueEffect(8, Level(1.0f, V_LONG_DEFAULT[0], V_LONG_DEFAULT[1])), 0)},
+        {"pop",
+         {{6, CompositePrimitive::SLOW_RISE, 1.0f}, {50, CompositePrimitive::THUD, 1.0f}},
+         Queue(6, QueueEffect(7, Level(1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 50,
+               QueueEffect(4, Level(1.0f, V_CLICK_DEFAULT[0], V_CLICK_DEFAULT[1])), 0)},
+        {"snap",
+         {{7, CompositePrimitive::QUICK_RISE, 1.0f}, {0, CompositePrimitive::QUICK_FALL, 1.0f}},
+         Queue(7, QueueEffect(6, Level(1.0f, V_LONG_DEFAULT[0], V_LONG_DEFAULT[1])),
+               QueueEffect(8, Level(1.0f, V_LONG_DEFAULT[0], V_LONG_DEFAULT[1])), 0)},
+};
+
+INSTANTIATE_TEST_CASE_P(VibratorTests, ComposeTest,
+                        ValuesIn(kComposeParams.begin(), kComposeParams.end()),
+                        ComposeTest::PrintParam);
+}  // namespace vibrator
+}  // namespace hardware
+}  // namespace android
+}  // namespace aidl
diff --git a/vibrator/cs40l26/tests/types.h b/vibrator/cs40l26/tests/types.h
new file mode 100644
index 0000000..e05c648
--- /dev/null
+++ b/vibrator/cs40l26/tests/types.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ANDROID_HARDWARE_VIBRATOR_TEST_TYPES_H
+#define ANDROID_HARDWARE_VIBRATOR_TEST_TYPES_H
+
+#include <aidl/android/hardware/vibrator/IVibrator.h>
+
+using EffectIndex = uint16_t;
+using EffectLevel = uint32_t;
+using EffectAmplitude = float;
+using EffectScale = uint16_t;
+using EffectDuration = uint32_t;
+using EffectQueue = std::tuple<std::string, EffectDuration>;
+using EffectTuple = std::tuple<::aidl::android::hardware::vibrator::Effect,
+                               ::aidl::android::hardware::vibrator::EffectStrength>;
+
+using QueueEffect = std::tuple<EffectIndex, EffectLevel>;
+using QueueDelay = uint32_t;
+
+#endif  // ANDROID_HARDWARE_VIBRATOR_TEST_TYPES_H
diff --git a/vibrator/cs40l26/tests/utils.h b/vibrator/cs40l26/tests/utils.h
new file mode 100644
index 0000000..e7f6055
--- /dev/null
+++ b/vibrator/cs40l26/tests/utils.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ANDROID_HARDWARE_VIBRATOR_TEST_UTILS_H
+#define ANDROID_HARDWARE_VIBRATOR_TEST_UTILS_H
+
+#include <cmath>
+
+#include "types.h"
+
+static inline EffectScale toScale(float amplitude, float maximum) {
+    float ratio = 100; /* Unit: % */
+    if (maximum != 0)
+        ratio = amplitude / maximum * 100;
+
+    if (maximum == 0 || ratio > 100)
+        ratio = 100;
+
+    return std::round(ratio);
+}
+
+static inline EffectScale levelToScale(EffectLevel level) {
+    return toScale(level, 100);
+}
+
+static inline EffectScale amplitudeToScale(EffectAmplitude amplitude) {
+    return toScale(amplitude, 1.0f);
+}
+
+static inline uint32_t msToCycles(EffectDuration ms) {
+    return ms * 48;
+}
+
+#endif  // ANDROID_HARDWARE_VIBRATOR_TEST_UTILS_H
diff --git a/wifi/BoardConfig-wifi.mk b/wifi/BoardConfig-wifi.mk
new file mode 100644
index 0000000..ab7708c
--- /dev/null
+++ b/wifi/BoardConfig-wifi.mk
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2022 The Android Open-Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# WiFi
+BOARD_WLAN_DEVICE := bcmdhd
+BOARD_WPA_SUPPLICANT_PRIVATE_LIB := lib_driver_cmd_bcmdhd
+BOARD_HOSTAPD_PRIVATE_LIB := lib_driver_cmd_bcmdhd
+WPA_SUPPLICANT_VERSION := VER_0_8_X
+BOARD_WPA_SUPPLICANT_DRIVER := NL80211
+BOARD_HOSTAPD_DRIVER := NL80211
+# Wifi interface combination - {1 STA + 1 AP} or {1 STA + 1 AP_BRIDGED} or {1 STA + 1 P2P}
+# or {1 STA + 1 NAN} or {2 STA}
+WIFI_HAL_INTERFACE_COMBINATIONS := {{{STA}, 1}, {{P2P, NAN, AP, AP_BRIDGED}, 1}}, {{{STA}, 2}}
+WIFI_FEATURE_WIFI_EXT_HAL := true
+WIFI_FEATURE_IMU_DETECTION := true
+# Avoid Wifi reset on MAC Address change
+WIFI_AVOID_IFACE_RESET_MAC_CHANGE := true
+WIFI_FEATURE_HOSTAPD_11AX := true
+BOARD_HOSTAPD_CONFIG_80211W_MFP_OPTIONAL := true
+WIFI_HIDL_UNIFIED_SUPPLICANT_SERVICE_RC_ENTRY := true
+
+PRODUCT_COPY_FILES += \
+    device/google/felix/wifi/p2p_supplicant_overlay.conf:$(TARGET_COPY_OUT_VENDOR)/etc/wifi/p2p_supplicant_overlay.conf \
+    device/google/felix/wifi/wpa_supplicant_overlay.conf:$(TARGET_COPY_OUT_VENDOR)/etc/wifi/wpa_supplicant_overlay.conf
+
diff --git a/wifi/p2p_supplicant_overlay.conf b/wifi/p2p_supplicant_overlay.conf
new file mode 100644
index 0000000..74d24d8
--- /dev/null
+++ b/wifi/p2p_supplicant_overlay.conf
@@ -0,0 +1,11 @@
+driver_param=use_p2p_group_interface=1p2p_device=1
+update_config=1
+eapol_version=1
+ap_scan=1
+fast_reauth=1
+pmf=1
+p2p_add_cli_chan=1
+disable_scan_offload=1
+p2p_go_vht=1
+p2p_pref_chan=124:149, 115:36
+p2p_6ghz_disable=1
diff --git a/wifi/wpa_supplicant_overlay.conf b/wifi/wpa_supplicant_overlay.conf
new file mode 100644
index 0000000..6f274c1
--- /dev/null
+++ b/wifi/wpa_supplicant_overlay.conf
@@ -0,0 +1,10 @@
+sae_pwe=2
+driver_param=use_p2p_group_interface=1p2p_device=1
+disable_scan_offload=1
+wowlan_triggers=any
+bss_max_count=512
+interworking=1
+hs20=1
+auto_interworking=0
+bss_no_flush_when_down=1
+btm_offload=1