)]}'
{
  "commit": "08f051eda33b51e8ee0f45f05bcfe49d0f0caf6b",
  "tree": "46a1e3577de686377e859c7f346299e9ea726260",
  "parents": [
    "28dfbe6ed483e8a589cce88095d7787d61bf9c16"
  ],
  "author": {
    "name": "Andrew Waterman",
    "email": "andrew@sifive.com",
    "time": "Wed Oct 25 14:30:32 2017 -0700"
  },
  "committer": {
    "name": "Palmer Dabbelt",
    "email": "palmer@sifive.com",
    "time": "Thu Nov 30 12:58:25 2017 -0800"
  },
  "message": "RISC-V: Flush I$ when making a dirty page executable\n\nThe RISC-V ISA allows for instruction caches that are not coherent WRT\nstores, even on a single hart.  As a result, we need to explicitly flush\nthe instruction cache whenever marking a dirty page as executable in\norder to preserve the correct system behavior.\n\nLocal instruction caches aren\u0027t that scary (our implementations actually\nflush the cache, but RISC-V is defined to allow higher-performance\nimplementations to exist), but RISC-V defines no way to perform an\ninstruction cache shootdown.  When explicitly asked to do so we can\nshoot down remote instruction caches via an IPI, but this is a bit on\nthe slow side.\n\nInstead of requiring an IPI to all harts whenever marking a page as\nexecutable, we simply flush the currently running harts.  In order to\nmaintain correct behavior, we additionally mark every other hart as\nneeding a deferred instruction cache which will be taken before anything\nruns on it.\n\nSigned-off-by: Andrew Waterman \u003candrew@sifive.com\u003e\nSigned-off-by: Palmer Dabbelt \u003cpalmer@sifive.com\u003e\n",
  "tree_diff": [
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