0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f - kernel/common

commit	0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f	[log] [tgz]
author	Peter De Schrijver <[email protected]>	Wed Apr 03 17:40:39 2013 +0300
committer	Stephen Warren <[email protected]>	Thu Apr 04 16:10:45 2013 -0600
tree	989c920b532d4d5d7372c275ed828356cff9c581
parent	7ba28813b41120dd67329fd04dc732ea7fef05a0 [diff]

clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>

drivers/clk/tegra/clk-pll.c[diff]
drivers/clk/tegra/clk-tegra20.c[diff]
drivers/clk/tegra/clk-tegra30.c[diff]
drivers/clk/tegra/clk.h[diff]

4 files changed

tree: 989c920b532d4d5d7372c275ed828356cff9c581