watchdog: renesas_wdt: Add a few cycles delay
According to the hardware manual of R-Car Gen2 and Gen3,
software should wait a few RLCK cycles as following:
- Delay 2 cycles before setting watchdog counter.
- Delay 3 cycles before disabling module clock.
So, this patch adds such delays.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
1 file changed
