clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
4 files changed